Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1177643377	155188	0	0
ctrl_regwen_rd_A	1177643377	8891	0	0
exec_rd_A	1177643377	7757	0	0
exec_regwen_rd_A	1177643377	8449	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1177643377	155188	0	0
T17	13483	0	0	0
T25	78916	2145	0	0
T26	0	3002	0	0
T27	0	1027	0	0
T29	33846	0	0	0
T30	33551	0	0	0
T33	77322	0	0	0
T34	75875	0	0	0
T35	307559	0	0	0
T36	71016	0	0	0
T41	0	1395	0	0
T42	0	3307	0	0
T43	0	2643	0	0
T44	0	1219	0	0
T45	0	1108	0	0
T46	0	4030	0	0
T47	0	5821	0	0
T48	71726	0	0	0
T49	165427	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1177643377	8891	0	0
T21	767	0	0	0
T26	132554	467	0	0
T28	973928	0	0	0
T38	160720	0	0	0
T39	1278	0	0	0
T42	0	559	0	0
T43	0	684	0	0
T52	638427	0	0	0
T90	231841	0	0	0
T101	0	125	0	0
T102	0	156	0	0
T103	0	877	0	0
T104	0	288	0	0
T105	0	742	0	0
T106	0	608	0	0
T107	0	121	0	0
T108	35562	0	0	0
T109	682	0	0	0
T110	94767	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1177643377	7757	0	0
T21	767	0	0	0
T26	132554	371	0	0
T28	973928	0	0	0
T38	160720	0	0	0
T39	1278	0	0	0
T42	0	582	0	0
T43	0	588	0	0
T52	638427	0	0	0
T90	231841	0	0	0
T101	0	117	0	0
T102	0	131	0	0
T103	0	713	0	0
T104	0	195	0	0
T105	0	524	0	0
T106	0	544	0	0
T107	0	188	0	0
T108	35562	0	0	0
T109	682	0	0	0
T110	94767	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1177643377	8449	0	0
T21	767	0	0	0
T26	132554	391	0	0
T28	973928	0	0	0
T38	160720	0	0	0
T39	1278	0	0	0
T42	0	612	0	0
T43	0	760	0	0
T52	638427	0	0	0
T90	231841	0	0	0
T101	0	42	0	0
T102	0	118	0	0
T103	0	808	0	0
T104	0	224	0	0
T105	0	556	0	0
T106	0	531	0	0
T107	0	165	0	0
T108	35562	0	0	0
T109	682	0	0	0
T110	94767	0	0	0