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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 97.02 100.00 100.00 98.61 99.70 98.52


Total test records in report: 1039
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T789 /workspace/coverage/default/44.sram_ctrl_executable.3385402986 Apr 16 02:16:18 PM PDT 24 Apr 16 02:26:09 PM PDT 24 10416783742 ps
T790 /workspace/coverage/default/44.sram_ctrl_max_throughput.3196649744 Apr 16 02:16:09 PM PDT 24 Apr 16 02:18:47 PM PDT 24 3026779084 ps
T791 /workspace/coverage/default/21.sram_ctrl_multiple_keys.4220831894 Apr 16 02:12:51 PM PDT 24 Apr 16 02:14:11 PM PDT 24 2327364253 ps
T792 /workspace/coverage/default/44.sram_ctrl_smoke.3933900336 Apr 16 02:16:10 PM PDT 24 Apr 16 02:16:28 PM PDT 24 1194564495 ps
T793 /workspace/coverage/default/3.sram_ctrl_stress_all.2612795776 Apr 16 02:11:28 PM PDT 24 Apr 16 02:46:49 PM PDT 24 302935927733 ps
T794 /workspace/coverage/default/29.sram_ctrl_max_throughput.3389018815 Apr 16 02:13:57 PM PDT 24 Apr 16 02:14:24 PM PDT 24 746336927 ps
T795 /workspace/coverage/default/11.sram_ctrl_smoke.2807046774 Apr 16 02:11:54 PM PDT 24 Apr 16 02:12:07 PM PDT 24 884833607 ps
T796 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3694835277 Apr 16 02:12:11 PM PDT 24 Apr 16 02:12:15 PM PDT 24 1822595411 ps
T797 /workspace/coverage/default/32.sram_ctrl_smoke.756257400 Apr 16 02:14:58 PM PDT 24 Apr 16 02:15:59 PM PDT 24 1212035373 ps
T798 /workspace/coverage/default/17.sram_ctrl_lc_escalation.696106539 Apr 16 02:12:19 PM PDT 24 Apr 16 02:13:17 PM PDT 24 9649844903 ps
T799 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3009470404 Apr 16 02:14:12 PM PDT 24 Apr 16 02:29:31 PM PDT 24 29213783635 ps
T800 /workspace/coverage/default/25.sram_ctrl_regwen.3398680661 Apr 16 02:13:24 PM PDT 24 Apr 16 02:24:13 PM PDT 24 36004200716 ps
T801 /workspace/coverage/default/3.sram_ctrl_executable.1968021159 Apr 16 02:11:27 PM PDT 24 Apr 16 02:22:03 PM PDT 24 69297281124 ps
T802 /workspace/coverage/default/10.sram_ctrl_bijection.33883912 Apr 16 02:11:47 PM PDT 24 Apr 16 02:53:33 PM PDT 24 138937780261 ps
T803 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1989760052 Apr 16 02:11:56 PM PDT 24 Apr 16 02:14:18 PM PDT 24 815513327 ps
T804 /workspace/coverage/default/44.sram_ctrl_multiple_keys.3438938702 Apr 16 02:16:10 PM PDT 24 Apr 16 02:21:04 PM PDT 24 7154636722 ps
T805 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2739903026 Apr 16 02:16:52 PM PDT 24 Apr 16 02:17:02 PM PDT 24 718988245 ps
T806 /workspace/coverage/default/11.sram_ctrl_regwen.3814029338 Apr 16 02:11:57 PM PDT 24 Apr 16 02:21:46 PM PDT 24 9479262311 ps
T807 /workspace/coverage/default/39.sram_ctrl_smoke.3373983424 Apr 16 02:15:25 PM PDT 24 Apr 16 02:15:34 PM PDT 24 2713610281 ps
T808 /workspace/coverage/default/14.sram_ctrl_ram_cfg.3959622132 Apr 16 02:12:11 PM PDT 24 Apr 16 02:12:15 PM PDT 24 1457267451 ps
T809 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2221131458 Apr 16 02:11:32 PM PDT 24 Apr 16 02:16:31 PM PDT 24 4856435757 ps
T810 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.247281220 Apr 16 02:13:47 PM PDT 24 Apr 16 02:21:05 PM PDT 24 37573549930 ps
T811 /workspace/coverage/default/21.sram_ctrl_bijection.3885653628 Apr 16 02:12:56 PM PDT 24 Apr 16 02:24:14 PM PDT 24 43864189019 ps
T812 /workspace/coverage/default/22.sram_ctrl_ram_cfg.61617070 Apr 16 02:13:04 PM PDT 24 Apr 16 02:13:08 PM PDT 24 365896360 ps
T813 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.1609527209 Apr 16 02:15:02 PM PDT 24 Apr 16 02:17:32 PM PDT 24 4888012931 ps
T814 /workspace/coverage/default/19.sram_ctrl_ram_cfg.58978049 Apr 16 02:12:36 PM PDT 24 Apr 16 02:12:40 PM PDT 24 2002350040 ps
T815 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.102857960 Apr 16 02:14:46 PM PDT 24 Apr 16 02:18:49 PM PDT 24 5758272094 ps
T816 /workspace/coverage/default/6.sram_ctrl_max_throughput.3378953238 Apr 16 02:11:31 PM PDT 24 Apr 16 02:11:38 PM PDT 24 669519271 ps
T817 /workspace/coverage/default/37.sram_ctrl_regwen.4217751741 Apr 16 02:15:11 PM PDT 24 Apr 16 02:24:44 PM PDT 24 11929058652 ps
T818 /workspace/coverage/default/8.sram_ctrl_max_throughput.1036716011 Apr 16 02:11:43 PM PDT 24 Apr 16 02:11:59 PM PDT 24 694363296 ps
T819 /workspace/coverage/default/33.sram_ctrl_stress_all.3059474209 Apr 16 02:14:38 PM PDT 24 Apr 16 03:07:37 PM PDT 24 148223064134 ps
T820 /workspace/coverage/default/18.sram_ctrl_smoke.46870920 Apr 16 02:12:25 PM PDT 24 Apr 16 02:12:36 PM PDT 24 940635362 ps
T821 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.898050410 Apr 16 02:12:27 PM PDT 24 Apr 16 02:14:33 PM PDT 24 1655033226 ps
T822 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1752925270 Apr 16 02:11:34 PM PDT 24 Apr 16 02:12:51 PM PDT 24 1036241855 ps
T823 /workspace/coverage/default/46.sram_ctrl_multiple_keys.3400349317 Apr 16 02:16:26 PM PDT 24 Apr 16 02:22:31 PM PDT 24 52274732874 ps
T824 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.821277733 Apr 16 02:14:06 PM PDT 24 Apr 16 02:24:33 PM PDT 24 99863451615 ps
T825 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3161830240 Apr 16 02:12:12 PM PDT 24 Apr 16 02:13:16 PM PDT 24 2005657820 ps
T826 /workspace/coverage/default/1.sram_ctrl_executable.4266482891 Apr 16 02:11:13 PM PDT 24 Apr 16 02:28:21 PM PDT 24 43381882983 ps
T827 /workspace/coverage/default/6.sram_ctrl_regwen.3215122012 Apr 16 02:11:33 PM PDT 24 Apr 16 02:20:24 PM PDT 24 2259669756 ps
T828 /workspace/coverage/default/13.sram_ctrl_smoke.882083483 Apr 16 02:11:57 PM PDT 24 Apr 16 02:13:54 PM PDT 24 3189270072 ps
T829 /workspace/coverage/default/22.sram_ctrl_smoke.2533727337 Apr 16 02:13:01 PM PDT 24 Apr 16 02:13:08 PM PDT 24 401735014 ps
T830 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.2609562860 Apr 16 02:13:53 PM PDT 24 Apr 16 02:18:13 PM PDT 24 2999662085 ps
T831 /workspace/coverage/default/27.sram_ctrl_smoke.3873223792 Apr 16 02:13:32 PM PDT 24 Apr 16 02:15:55 PM PDT 24 1877784790 ps
T832 /workspace/coverage/default/13.sram_ctrl_bijection.3677632912 Apr 16 02:11:56 PM PDT 24 Apr 16 02:59:03 PM PDT 24 634350000167 ps
T833 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2178405428 Apr 16 02:15:24 PM PDT 24 Apr 16 02:20:43 PM PDT 24 23181180292 ps
T834 /workspace/coverage/default/47.sram_ctrl_alert_test.544534180 Apr 16 02:16:47 PM PDT 24 Apr 16 02:16:48 PM PDT 24 16720456 ps
T835 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3318102043 Apr 16 02:12:54 PM PDT 24 Apr 16 02:13:25 PM PDT 24 1469214380 ps
T836 /workspace/coverage/default/5.sram_ctrl_lc_escalation.3201884922 Apr 16 02:11:33 PM PDT 24 Apr 16 02:12:00 PM PDT 24 14801697302 ps
T837 /workspace/coverage/default/23.sram_ctrl_alert_test.2188101795 Apr 16 02:13:16 PM PDT 24 Apr 16 02:13:17 PM PDT 24 14961162 ps
T838 /workspace/coverage/default/9.sram_ctrl_multiple_keys.1901765471 Apr 16 02:11:54 PM PDT 24 Apr 16 02:31:04 PM PDT 24 10750239442 ps
T839 /workspace/coverage/default/37.sram_ctrl_mem_walk.3242830233 Apr 16 02:15:13 PM PDT 24 Apr 16 02:19:58 PM PDT 24 13774455187 ps
T840 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1082933194 Apr 16 02:11:28 PM PDT 24 Apr 16 02:18:50 PM PDT 24 23415912039 ps
T841 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.4265867411 Apr 16 02:13:15 PM PDT 24 Apr 16 02:14:09 PM PDT 24 2083287027 ps
T842 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2571827032 Apr 16 02:14:11 PM PDT 24 Apr 16 02:18:16 PM PDT 24 11914470512 ps
T843 /workspace/coverage/default/13.sram_ctrl_alert_test.3853322934 Apr 16 02:12:11 PM PDT 24 Apr 16 02:12:12 PM PDT 24 44622042 ps
T844 /workspace/coverage/default/40.sram_ctrl_executable.2726075615 Apr 16 02:15:34 PM PDT 24 Apr 16 02:17:33 PM PDT 24 3336977744 ps
T845 /workspace/coverage/default/12.sram_ctrl_ram_cfg.75776480 Apr 16 02:11:57 PM PDT 24 Apr 16 02:12:01 PM PDT 24 1409844222 ps
T846 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2522769146 Apr 16 02:11:42 PM PDT 24 Apr 16 02:14:52 PM PDT 24 10709619244 ps
T847 /workspace/coverage/default/24.sram_ctrl_max_throughput.3213751153 Apr 16 02:13:19 PM PDT 24 Apr 16 02:14:00 PM PDT 24 743696209 ps
T848 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1323751323 Apr 16 02:11:56 PM PDT 24 Apr 16 02:12:58 PM PDT 24 1852961115 ps
T849 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2802843738 Apr 16 02:16:15 PM PDT 24 Apr 16 02:22:35 PM PDT 24 16454027615 ps
T850 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4100082009 Apr 16 02:11:36 PM PDT 24 Apr 16 02:15:34 PM PDT 24 18413081694 ps
T851 /workspace/coverage/default/40.sram_ctrl_lc_escalation.3950584308 Apr 16 02:15:39 PM PDT 24 Apr 16 02:16:29 PM PDT 24 9027636107 ps
T852 /workspace/coverage/default/3.sram_ctrl_ram_cfg.3408819904 Apr 16 02:11:28 PM PDT 24 Apr 16 02:11:32 PM PDT 24 351286743 ps
T853 /workspace/coverage/default/15.sram_ctrl_partial_access.2950286820 Apr 16 02:12:12 PM PDT 24 Apr 16 02:13:34 PM PDT 24 2385374028 ps
T854 /workspace/coverage/default/49.sram_ctrl_executable.1254050972 Apr 16 02:16:59 PM PDT 24 Apr 16 02:22:16 PM PDT 24 25899756117 ps
T855 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3666580590 Apr 16 02:16:56 PM PDT 24 Apr 16 02:17:04 PM PDT 24 1852216956 ps
T856 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1615636225 Apr 16 02:16:43 PM PDT 24 Apr 16 02:49:41 PM PDT 24 83544743558 ps
T857 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2311783601 Apr 16 02:14:42 PM PDT 24 Apr 16 02:32:54 PM PDT 24 22524772663 ps
T858 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1427564123 Apr 16 02:17:02 PM PDT 24 Apr 16 02:17:33 PM PDT 24 5234461390 ps
T859 /workspace/coverage/default/34.sram_ctrl_executable.1305440728 Apr 16 02:14:48 PM PDT 24 Apr 16 02:26:41 PM PDT 24 5940345437 ps
T860 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3290947492 Apr 16 02:16:07 PM PDT 24 Apr 16 02:16:23 PM PDT 24 2610332950 ps
T861 /workspace/coverage/default/8.sram_ctrl_stress_all.3282210827 Apr 16 02:11:43 PM PDT 24 Apr 16 03:08:50 PM PDT 24 81270128490 ps
T862 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.459495333 Apr 16 02:14:13 PM PDT 24 Apr 16 02:14:25 PM PDT 24 2663411060 ps
T863 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.321726738 Apr 16 02:15:56 PM PDT 24 Apr 16 02:18:47 PM PDT 24 4912407319 ps
T864 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2528659676 Apr 16 02:12:26 PM PDT 24 Apr 16 02:17:42 PM PDT 24 15220600265 ps
T865 /workspace/coverage/default/34.sram_ctrl_stress_all.1622231942 Apr 16 02:14:47 PM PDT 24 Apr 16 03:14:26 PM PDT 24 155985008638 ps
T866 /workspace/coverage/default/12.sram_ctrl_max_throughput.1168958897 Apr 16 02:11:58 PM PDT 24 Apr 16 02:14:10 PM PDT 24 780943882 ps
T867 /workspace/coverage/default/13.sram_ctrl_ram_cfg.1597136787 Apr 16 02:12:01 PM PDT 24 Apr 16 02:12:05 PM PDT 24 2288950529 ps
T868 /workspace/coverage/default/15.sram_ctrl_regwen.3338706064 Apr 16 02:12:12 PM PDT 24 Apr 16 02:23:57 PM PDT 24 54886255674 ps
T869 /workspace/coverage/default/47.sram_ctrl_lc_escalation.1847338887 Apr 16 02:16:38 PM PDT 24 Apr 16 02:18:23 PM PDT 24 54296361333 ps
T870 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2802357865 Apr 16 02:11:39 PM PDT 24 Apr 16 02:14:00 PM PDT 24 10192748633 ps
T871 /workspace/coverage/default/46.sram_ctrl_ram_cfg.3088144945 Apr 16 02:16:35 PM PDT 24 Apr 16 02:16:39 PM PDT 24 364965374 ps
T872 /workspace/coverage/default/3.sram_ctrl_partial_access.3281949772 Apr 16 02:11:26 PM PDT 24 Apr 16 02:11:34 PM PDT 24 760811903 ps
T873 /workspace/coverage/default/15.sram_ctrl_multiple_keys.3336580497 Apr 16 02:12:14 PM PDT 24 Apr 16 02:32:41 PM PDT 24 50849447221 ps
T874 /workspace/coverage/default/25.sram_ctrl_smoke.2154529418 Apr 16 02:13:22 PM PDT 24 Apr 16 02:13:29 PM PDT 24 6896749629 ps
T875 /workspace/coverage/default/40.sram_ctrl_bijection.2512890908 Apr 16 02:15:30 PM PDT 24 Apr 16 02:27:50 PM PDT 24 60128043190 ps
T876 /workspace/coverage/default/43.sram_ctrl_smoke.2787963599 Apr 16 02:15:59 PM PDT 24 Apr 16 02:18:26 PM PDT 24 5010378909 ps
T877 /workspace/coverage/default/28.sram_ctrl_stress_all.4022722274 Apr 16 02:13:51 PM PDT 24 Apr 16 03:17:01 PM PDT 24 62543512546 ps
T878 /workspace/coverage/default/26.sram_ctrl_mem_walk.1612123615 Apr 16 02:13:33 PM PDT 24 Apr 16 02:16:13 PM PDT 24 35651123017 ps
T879 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3519680394 Apr 16 02:14:33 PM PDT 24 Apr 16 02:19:52 PM PDT 24 4730870618 ps
T880 /workspace/coverage/default/45.sram_ctrl_mem_walk.957802890 Apr 16 02:16:25 PM PDT 24 Apr 16 02:19:02 PM PDT 24 21514184548 ps
T881 /workspace/coverage/default/4.sram_ctrl_multiple_keys.199355371 Apr 16 02:11:27 PM PDT 24 Apr 16 02:33:15 PM PDT 24 7053703435 ps
T882 /workspace/coverage/default/12.sram_ctrl_lc_escalation.3766471778 Apr 16 02:11:57 PM PDT 24 Apr 16 02:12:33 PM PDT 24 6468258369 ps
T883 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3004699375 Apr 16 02:13:31 PM PDT 24 Apr 16 02:25:47 PM PDT 24 191469619676 ps
T884 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.357133629 Apr 16 02:15:28 PM PDT 24 Apr 16 02:19:41 PM PDT 24 51220536582 ps
T885 /workspace/coverage/default/14.sram_ctrl_stress_all.218129419 Apr 16 02:12:12 PM PDT 24 Apr 16 03:10:51 PM PDT 24 19506393348 ps
T886 /workspace/coverage/default/5.sram_ctrl_multiple_keys.1244119737 Apr 16 02:11:33 PM PDT 24 Apr 16 02:21:49 PM PDT 24 9814300502 ps
T887 /workspace/coverage/default/29.sram_ctrl_lc_escalation.4100446851 Apr 16 02:13:57 PM PDT 24 Apr 16 02:15:13 PM PDT 24 39319592357 ps
T888 /workspace/coverage/default/42.sram_ctrl_partial_access.2461699554 Apr 16 02:15:55 PM PDT 24 Apr 16 02:16:05 PM PDT 24 2848269922 ps
T889 /workspace/coverage/default/49.sram_ctrl_max_throughput.3811784966 Apr 16 02:17:03 PM PDT 24 Apr 16 02:19:08 PM PDT 24 3983184766 ps
T890 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3011748061 Apr 16 02:11:33 PM PDT 24 Apr 16 02:12:53 PM PDT 24 10459582962 ps
T891 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.4259904250 Apr 16 02:16:56 PM PDT 24 Apr 16 02:30:04 PM PDT 24 7776188016 ps
T892 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2253833080 Apr 16 02:11:48 PM PDT 24 Apr 16 02:12:44 PM PDT 24 919190357 ps
T893 /workspace/coverage/default/40.sram_ctrl_multiple_keys.2048161942 Apr 16 02:15:32 PM PDT 24 Apr 16 02:31:32 PM PDT 24 33079329948 ps
T894 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2464144687 Apr 16 02:16:19 PM PDT 24 Apr 16 02:23:06 PM PDT 24 42959998859 ps
T895 /workspace/coverage/default/26.sram_ctrl_smoke.1049885189 Apr 16 02:13:28 PM PDT 24 Apr 16 02:15:54 PM PDT 24 3186241277 ps
T896 /workspace/coverage/default/9.sram_ctrl_alert_test.1040412817 Apr 16 02:11:47 PM PDT 24 Apr 16 02:11:48 PM PDT 24 14407918 ps
T897 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1778029370 Apr 16 02:12:36 PM PDT 24 Apr 16 02:17:30 PM PDT 24 52554632182 ps
T898 /workspace/coverage/default/26.sram_ctrl_bijection.1973123685 Apr 16 02:13:29 PM PDT 24 Apr 16 02:31:47 PM PDT 24 61842723893 ps
T899 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2163880031 Apr 16 02:12:12 PM PDT 24 Apr 16 02:14:41 PM PDT 24 2788571102 ps
T900 /workspace/coverage/default/40.sram_ctrl_smoke.3192360232 Apr 16 02:15:30 PM PDT 24 Apr 16 02:15:48 PM PDT 24 2204462885 ps
T901 /workspace/coverage/default/8.sram_ctrl_executable.1278033713 Apr 16 02:11:54 PM PDT 24 Apr 16 02:27:11 PM PDT 24 73432852250 ps
T902 /workspace/coverage/default/13.sram_ctrl_max_throughput.111889778 Apr 16 02:12:08 PM PDT 24 Apr 16 02:12:14 PM PDT 24 699135800 ps
T903 /workspace/coverage/default/13.sram_ctrl_stress_all.338653889 Apr 16 02:12:02 PM PDT 24 Apr 16 03:11:09 PM PDT 24 48950684636 ps
T904 /workspace/coverage/default/16.sram_ctrl_partial_access.3241319666 Apr 16 02:12:19 PM PDT 24 Apr 16 02:12:39 PM PDT 24 1463668765 ps
T905 /workspace/coverage/default/31.sram_ctrl_lc_escalation.2432099553 Apr 16 02:14:12 PM PDT 24 Apr 16 02:15:31 PM PDT 24 62002413589 ps
T906 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2417270760 Apr 16 02:16:35 PM PDT 24 Apr 16 02:18:04 PM PDT 24 5590227788 ps
T907 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.822614646 Apr 16 02:12:56 PM PDT 24 Apr 16 02:35:17 PM PDT 24 15532855700 ps
T908 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.613551277 Apr 16 02:11:34 PM PDT 24 Apr 16 02:11:40 PM PDT 24 621470848 ps
T909 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1410213791 Apr 16 02:13:57 PM PDT 24 Apr 16 02:17:28 PM PDT 24 3322242679 ps
T910 /workspace/coverage/default/37.sram_ctrl_executable.1282942500 Apr 16 02:15:06 PM PDT 24 Apr 16 02:33:08 PM PDT 24 95908968298 ps
T911 /workspace/coverage/default/49.sram_ctrl_multiple_keys.4191488355 Apr 16 02:16:56 PM PDT 24 Apr 16 02:27:06 PM PDT 24 5474293352 ps
T912 /workspace/coverage/default/25.sram_ctrl_stress_all.3921080219 Apr 16 02:13:31 PM PDT 24 Apr 16 04:10:58 PM PDT 24 161297296040 ps
T913 /workspace/coverage/default/18.sram_ctrl_ram_cfg.1520725552 Apr 16 02:12:29 PM PDT 24 Apr 16 02:12:33 PM PDT 24 1697914002 ps
T914 /workspace/coverage/default/3.sram_ctrl_regwen.1178196955 Apr 16 02:11:29 PM PDT 24 Apr 16 02:33:27 PM PDT 24 45002947114 ps
T915 /workspace/coverage/default/4.sram_ctrl_stress_all.535201024 Apr 16 02:11:31 PM PDT 24 Apr 16 03:22:47 PM PDT 24 356864443831 ps
T916 /workspace/coverage/default/34.sram_ctrl_regwen.1211623342 Apr 16 02:14:42 PM PDT 24 Apr 16 02:15:04 PM PDT 24 3657643681 ps
T917 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2295522930 Apr 16 02:15:35 PM PDT 24 Apr 16 02:29:32 PM PDT 24 47222008415 ps
T918 /workspace/coverage/default/3.sram_ctrl_lc_escalation.3637942802 Apr 16 02:11:27 PM PDT 24 Apr 16 02:11:58 PM PDT 24 7953121864 ps
T919 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3796792370 Apr 16 02:13:20 PM PDT 24 Apr 16 02:22:58 PM PDT 24 95316108352 ps
T920 /workspace/coverage/default/10.sram_ctrl_mem_walk.338656233 Apr 16 02:11:46 PM PDT 24 Apr 16 02:15:46 PM PDT 24 3947840941 ps
T921 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3652836240 Apr 16 02:14:21 PM PDT 24 Apr 16 02:20:00 PM PDT 24 5029907343 ps
T922 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1632207570 Apr 16 02:12:19 PM PDT 24 Apr 16 02:15:34 PM PDT 24 2955210595 ps
T923 /workspace/coverage/default/21.sram_ctrl_regwen.2336651822 Apr 16 02:12:54 PM PDT 24 Apr 16 02:22:19 PM PDT 24 4460598209 ps
T924 /workspace/coverage/default/7.sram_ctrl_regwen.769196774 Apr 16 02:11:38 PM PDT 24 Apr 16 02:28:09 PM PDT 24 3839901637 ps
T925 /workspace/coverage/default/16.sram_ctrl_bijection.1543863674 Apr 16 02:12:16 PM PDT 24 Apr 16 02:25:06 PM PDT 24 50557591310 ps
T926 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4092433550 Apr 16 02:13:38 PM PDT 24 Apr 16 02:14:51 PM PDT 24 4791832096 ps
T927 /workspace/coverage/default/48.sram_ctrl_multiple_keys.2795317097 Apr 16 02:16:47 PM PDT 24 Apr 16 02:27:49 PM PDT 24 7298407892 ps
T928 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2088960836 Apr 16 02:11:56 PM PDT 24 Apr 16 02:16:16 PM PDT 24 11663969446 ps
T929 /workspace/coverage/default/6.sram_ctrl_executable.1567949607 Apr 16 02:11:32 PM PDT 24 Apr 16 02:13:03 PM PDT 24 1729155714 ps
T930 /workspace/coverage/default/41.sram_ctrl_alert_test.1307254111 Apr 16 02:15:49 PM PDT 24 Apr 16 02:15:51 PM PDT 24 11691080 ps
T931 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1217258164 Apr 16 02:11:51 PM PDT 24 Apr 16 02:14:28 PM PDT 24 18222301809 ps
T932 /workspace/coverage/default/15.sram_ctrl_bijection.1889539039 Apr 16 02:12:11 PM PDT 24 Apr 16 02:35:54 PM PDT 24 59999587568 ps
T933 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2864548487 Apr 16 02:13:23 PM PDT 24 Apr 16 02:29:02 PM PDT 24 86353167587 ps
T934 /workspace/coverage/default/20.sram_ctrl_multiple_keys.2642272896 Apr 16 02:12:44 PM PDT 24 Apr 16 02:35:41 PM PDT 24 26436168263 ps
T935 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.3251085242 Apr 16 02:14:12 PM PDT 24 Apr 16 02:18:25 PM PDT 24 7235636969 ps
T936 /workspace/coverage/default/15.sram_ctrl_smoke.1581291832 Apr 16 02:12:11 PM PDT 24 Apr 16 02:12:28 PM PDT 24 1105261059 ps
T937 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1067288913 Apr 16 02:16:49 PM PDT 24 Apr 16 02:17:00 PM PDT 24 1216237091 ps
T938 /workspace/coverage/default/16.sram_ctrl_stress_all.972871890 Apr 16 02:12:21 PM PDT 24 Apr 16 04:09:09 PM PDT 24 94468919840 ps
T939 /workspace/coverage/default/22.sram_ctrl_multiple_keys.3364832875 Apr 16 02:12:58 PM PDT 24 Apr 16 02:29:12 PM PDT 24 10142864989 ps
T940 /workspace/coverage/default/11.sram_ctrl_stress_all.1216439399 Apr 16 02:11:54 PM PDT 24 Apr 16 03:27:15 PM PDT 24 165343103344 ps
T941 /workspace/coverage/default/48.sram_ctrl_stress_all.3443700104 Apr 16 02:16:58 PM PDT 24 Apr 16 03:06:44 PM PDT 24 50374374962 ps
T942 /workspace/coverage/default/16.sram_ctrl_mem_walk.901840189 Apr 16 02:12:21 PM PDT 24 Apr 16 02:17:48 PM PDT 24 82537999978 ps
T86 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3627066088 Apr 16 02:06:39 PM PDT 24 Apr 16 02:07:07 PM PDT 24 3896563133 ps
T943 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2953879240 Apr 16 02:06:35 PM PDT 24 Apr 16 02:06:38 PM PDT 24 142705753 ps
T97 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1244532547 Apr 16 02:06:56 PM PDT 24 Apr 16 02:06:59 PM PDT 24 299754949 ps
T944 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.802675718 Apr 16 02:06:45 PM PDT 24 Apr 16 02:06:49 PM PDT 24 1122831118 ps
T945 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.630445898 Apr 16 02:06:23 PM PDT 24 Apr 16 02:06:28 PM PDT 24 1456799878 ps
T53 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2353675101 Apr 16 02:06:24 PM PDT 24 Apr 16 02:07:13 PM PDT 24 7282960781 ps
T87 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1859623576 Apr 16 02:06:24 PM PDT 24 Apr 16 02:06:25 PM PDT 24 37164398 ps
T54 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2168638156 Apr 16 02:06:47 PM PDT 24 Apr 16 02:06:49 PM PDT 24 35709888 ps
T946 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.182979676 Apr 16 02:06:05 PM PDT 24 Apr 16 02:06:08 PM PDT 24 28740044 ps
T55 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.202087919 Apr 16 02:06:26 PM PDT 24 Apr 16 02:07:24 PM PDT 24 54078421106 ps
T947 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4221718743 Apr 16 02:06:49 PM PDT 24 Apr 16 02:06:54 PM PDT 24 57803272 ps
T948 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.15036154 Apr 16 02:06:48 PM PDT 24 Apr 16 02:06:53 PM PDT 24 351926565 ps
T949 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2417914993 Apr 16 02:06:18 PM PDT 24 Apr 16 02:06:20 PM PDT 24 217996053 ps
T56 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3327549229 Apr 16 02:06:47 PM PDT 24 Apr 16 02:07:17 PM PDT 24 15333600303 ps
T88 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.165618293 Apr 16 02:06:15 PM PDT 24 Apr 16 02:06:17 PM PDT 24 15440796 ps
T57 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3591512208 Apr 16 02:06:43 PM PDT 24 Apr 16 02:07:35 PM PDT 24 7043346847 ps
T58 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1013783225 Apr 16 02:06:37 PM PDT 24 Apr 16 02:06:38 PM PDT 24 15920425 ps
T950 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4045154127 Apr 16 02:06:05 PM PDT 24 Apr 16 02:06:10 PM PDT 24 1454000168 ps
T951 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2320548067 Apr 16 02:06:51 PM PDT 24 Apr 16 02:06:56 PM PDT 24 2422883700 ps
T59 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1812088076 Apr 16 02:06:48 PM PDT 24 Apr 16 02:06:50 PM PDT 24 32178646 ps
T98 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.706959818 Apr 16 02:06:23 PM PDT 24 Apr 16 02:06:25 PM PDT 24 124501444 ps
T952 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2932398814 Apr 16 02:06:47 PM PDT 24 Apr 16 02:06:51 PM PDT 24 350811739 ps
T953 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1195882140 Apr 16 02:06:23 PM PDT 24 Apr 16 02:06:25 PM PDT 24 213456006 ps
T60 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1460374179 Apr 16 02:06:19 PM PDT 24 Apr 16 02:06:20 PM PDT 24 83051858 ps
T954 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2168044665 Apr 16 02:06:06 PM PDT 24 Apr 16 02:06:09 PM PDT 24 68358996 ps
T955 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2530366210 Apr 16 02:06:39 PM PDT 24 Apr 16 02:06:40 PM PDT 24 12779613 ps
T956 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1366080129 Apr 16 02:06:42 PM PDT 24 Apr 16 02:06:43 PM PDT 24 30045263 ps
T957 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3461447691 Apr 16 02:06:00 PM PDT 24 Apr 16 02:06:03 PM PDT 24 84364992 ps
T99 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2663674595 Apr 16 02:06:29 PM PDT 24 Apr 16 02:06:32 PM PDT 24 496767341 ps
T61 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1424256726 Apr 16 02:06:52 PM PDT 24 Apr 16 02:06:53 PM PDT 24 31912321 ps
T62 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3399275106 Apr 16 02:06:49 PM PDT 24 Apr 16 02:06:51 PM PDT 24 53265135 ps
T958 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1230750545 Apr 16 02:06:12 PM PDT 24 Apr 16 02:06:13 PM PDT 24 45298477 ps
T959 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1838349075 Apr 16 02:06:35 PM PDT 24 Apr 16 02:06:41 PM PDT 24 2034880463 ps
T960 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3883701696 Apr 16 02:06:15 PM PDT 24 Apr 16 02:06:17 PM PDT 24 23680187 ps
T961 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2990810252 Apr 16 02:06:24 PM PDT 24 Apr 16 02:06:25 PM PDT 24 96091613 ps
T962 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.304280263 Apr 16 02:06:28 PM PDT 24 Apr 16 02:06:30 PM PDT 24 110876857 ps
T64 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1313141903 Apr 16 02:06:07 PM PDT 24 Apr 16 02:06:09 PM PDT 24 26597596 ps
T65 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3830446568 Apr 16 02:06:12 PM PDT 24 Apr 16 02:06:14 PM PDT 24 48135003 ps
T66 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1255679753 Apr 16 02:06:03 PM PDT 24 Apr 16 02:06:54 PM PDT 24 29344932686 ps
T963 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2735426877 Apr 16 02:06:48 PM PDT 24 Apr 16 02:07:19 PM PDT 24 14733014576 ps
T964 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3987323999 Apr 16 02:06:47 PM PDT 24 Apr 16 02:06:48 PM PDT 24 16841983 ps
T67 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.700244220 Apr 16 02:06:42 PM PDT 24 Apr 16 02:07:32 PM PDT 24 7108144076 ps
T965 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.528301009 Apr 16 02:06:40 PM PDT 24 Apr 16 02:06:45 PM PDT 24 119596521 ps
T111 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1066806116 Apr 16 02:06:36 PM PDT 24 Apr 16 02:06:39 PM PDT 24 559348736 ps
T966 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2705527794 Apr 16 02:06:11 PM PDT 24 Apr 16 02:06:14 PM PDT 24 649127960 ps
T967 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1445915854 Apr 16 02:06:22 PM PDT 24 Apr 16 02:06:23 PM PDT 24 17460595 ps
T968 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1986598546 Apr 16 02:06:08 PM PDT 24 Apr 16 02:06:10 PM PDT 24 224255433 ps
T112 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.523930473 Apr 16 02:06:16 PM PDT 24 Apr 16 02:06:18 PM PDT 24 375443986 ps
T969 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2933028765 Apr 16 02:06:36 PM PDT 24 Apr 16 02:06:37 PM PDT 24 51597861 ps
T68 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.807455707 Apr 16 02:06:15 PM PDT 24 Apr 16 02:07:06 PM PDT 24 14776286839 ps
T76 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2282174146 Apr 16 02:06:48 PM PDT 24 Apr 16 02:07:20 PM PDT 24 15397507431 ps
T970 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3149513896 Apr 16 02:06:19 PM PDT 24 Apr 16 02:06:21 PM PDT 24 81540019 ps
T971 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4031130750 Apr 16 02:06:37 PM PDT 24 Apr 16 02:06:41 PM PDT 24 327691241 ps
T972 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.470292497 Apr 16 02:06:16 PM PDT 24 Apr 16 02:07:24 PM PDT 24 44012761336 ps
T973 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2164827552 Apr 16 02:06:04 PM PDT 24 Apr 16 02:06:05 PM PDT 24 71361620 ps
T974 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2863447940 Apr 16 02:06:11 PM PDT 24 Apr 16 02:06:16 PM PDT 24 40649770 ps
T975 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.250394259 Apr 16 02:06:11 PM PDT 24 Apr 16 02:06:14 PM PDT 24 122465364 ps
T976 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1813527542 Apr 16 02:06:11 PM PDT 24 Apr 16 02:06:17 PM PDT 24 1438790967 ps
T113 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2533343906 Apr 16 02:06:47 PM PDT 24 Apr 16 02:06:50 PM PDT 24 320903671 ps
T977 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2515554034 Apr 16 02:06:24 PM PDT 24 Apr 16 02:06:25 PM PDT 24 13846423 ps
T978 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2808011614 Apr 16 02:06:43 PM PDT 24 Apr 16 02:06:45 PM PDT 24 21760393 ps
T115 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1103368830 Apr 16 02:06:41 PM PDT 24 Apr 16 02:06:45 PM PDT 24 223158600 ps
T979 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.541442490 Apr 16 02:06:35 PM PDT 24 Apr 16 02:06:36 PM PDT 24 12419847 ps
T980 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2164640805 Apr 16 02:06:15 PM PDT 24 Apr 16 02:06:20 PM PDT 24 678483330 ps
T981 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2031012235 Apr 16 02:06:04 PM PDT 24 Apr 16 02:06:05 PM PDT 24 17093242 ps
T982 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.95349519 Apr 16 02:06:30 PM PDT 24 Apr 16 02:06:34 PM PDT 24 317588552 ps
T983 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.914335982 Apr 16 02:06:41 PM PDT 24 Apr 16 02:06:44 PM PDT 24 25384563 ps
T117 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4021898462 Apr 16 02:06:28 PM PDT 24 Apr 16 02:06:31 PM PDT 24 1505289660 ps
T984 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1855079858 Apr 16 02:06:47 PM PDT 24 Apr 16 02:06:50 PM PDT 24 62775319 ps
T985 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4198293228 Apr 16 02:06:17 PM PDT 24 Apr 16 02:06:18 PM PDT 24 41183368 ps
T986 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1927204210 Apr 16 02:06:30 PM PDT 24 Apr 16 02:06:31 PM PDT 24 35245538 ps
T987 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4168356086 Apr 16 02:06:35 PM PDT 24 Apr 16 02:06:40 PM PDT 24 2691621530 ps
T988 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1878738723 Apr 16 02:06:36 PM PDT 24 Apr 16 02:06:37 PM PDT 24 19233714 ps
T116 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1989846726 Apr 16 02:06:11 PM PDT 24 Apr 16 02:06:15 PM PDT 24 4285727037 ps
T989 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3646204815 Apr 16 02:06:41 PM PDT 24 Apr 16 02:06:43 PM PDT 24 83912747 ps
T114 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2089503222 Apr 16 02:06:07 PM PDT 24 Apr 16 02:06:10 PM PDT 24 717954022 ps
T990 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2013820221 Apr 16 02:06:41 PM PDT 24 Apr 16 02:06:44 PM PDT 24 414217447 ps
T991 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3811897308 Apr 16 02:06:43 PM PDT 24 Apr 16 02:07:38 PM PDT 24 41581656376 ps
T992 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2090192010 Apr 16 02:06:45 PM PDT 24 Apr 16 02:06:49 PM PDT 24 43142965 ps
T993 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.561916733 Apr 16 02:06:48 PM PDT 24 Apr 16 02:06:50 PM PDT 24 15687600 ps
T994 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3505848198 Apr 16 02:06:48 PM PDT 24 Apr 16 02:06:52 PM PDT 24 1351928262 ps
T995 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3739451352 Apr 16 02:06:05 PM PDT 24 Apr 16 02:06:08 PM PDT 24 131190797 ps
T996 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2879461610 Apr 16 02:06:45 PM PDT 24 Apr 16 02:06:46 PM PDT 24 16478318 ps
T997 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2399130511 Apr 16 02:06:30 PM PDT 24 Apr 16 02:06:33 PM PDT 24 60061979 ps
T998 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3442202372 Apr 16 02:06:05 PM PDT 24 Apr 16 02:06:08 PM PDT 24 392480297 ps
T999 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2267737316 Apr 16 02:06:47 PM PDT 24 Apr 16 02:06:50 PM PDT 24 85487588 ps
T1000 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1158241507 Apr 16 02:06:55 PM PDT 24 Apr 16 02:08:00 PM PDT 24 33531483006 ps
T1001 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2958187625 Apr 16 02:06:50 PM PDT 24 Apr 16 02:06:51 PM PDT 24 33546648 ps
T1002 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2751320044 Apr 16 02:06:18 PM PDT 24 Apr 16 02:06:19 PM PDT 24 60565064 ps
T1003 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1052293730 Apr 16 02:06:48 PM PDT 24 Apr 16 02:06:52 PM PDT 24 96798677 ps
T120 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1846381881 Apr 16 02:06:50 PM PDT 24 Apr 16 02:06:53 PM PDT 24 1532441901 ps
T121 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.583675337 Apr 16 02:06:19 PM PDT 24 Apr 16 02:06:21 PM PDT 24 355163955 ps
T1004 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2267093412 Apr 16 02:06:18 PM PDT 24 Apr 16 02:06:23 PM PDT 24 377681165 ps
T1005 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.228976713 Apr 16 02:06:34 PM PDT 24 Apr 16 02:06:39 PM PDT 24 367714946 ps
T1006 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.658256039 Apr 16 02:06:47 PM PDT 24 Apr 16 02:06:51 PM PDT 24 1953980169 ps
T1007 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3976190812 Apr 16 02:06:47 PM PDT 24 Apr 16 02:06:49 PM PDT 24 23243612 ps
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