Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15994348	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

158424022

1

T1

3215

T2

98303

T3

52858

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85968182	1			T1	32038		T2	32768		T3	145896
values[0x0]	42636366	1			T1	10207		T2	32778		T3	49083
values[0x1]	45813822	1			T1	21965		T2	32757		T3	96908

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8147187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

166271183

1

T1

29214

T2

98303

T3

172962

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	568371	1			T1	267		T2	364		T3	1181
valid_sources[0x01]	633166	1			T1	260		T2	427		T3	1141
valid_sources[0x02]	575752	1			T1	255		T2	301		T3	1105
valid_sources[0x03]	751592	1			T1	225		T2	358		T3	1117
valid_sources[0x04]	596941	1			T1	267		T2	403		T3	1171
valid_sources[0x05]	610159	1			T1	279		T2	446		T3	1205
valid_sources[0x06]	558872	1			T1	259		T2	382		T3	1092
valid_sources[0x07]	818567	1			T1	288		T2	395		T3	1157
valid_sources[0x08]	593586	1			T1	248		T2	359		T3	1133
valid_sources[0x09]	651764	1			T1	307		T2	365		T3	1153
valid_sources[0x0a]	595161	1			T1	251		T2	404		T3	1127
valid_sources[0x0b]	1585029	1			T1	203		T2	402		T3	1092
valid_sources[0x0c]	590720	1			T1	237		T2	326		T3	1193
valid_sources[0x0d]	663869	1			T1	242		T2	349		T3	1103
valid_sources[0x0e]	607313	1			T1	265		T2	413		T3	1178
valid_sources[0x0f]	535688	1			T1	285		T2	431		T3	1076
valid_sources[0x10]	577230	1			T1	239		T2	422		T3	1158
valid_sources[0x11]	534205	1			T1	250		T2	412		T3	1156
valid_sources[0x12]	557204	1			T1	225		T2	310		T3	1116
valid_sources[0x13]	625813	1			T1	264		T2	389		T3	1131
valid_sources[0x14]	647472	1			T1	229		T2	356		T3	1194
valid_sources[0x15]	596642	1			T1	289		T2	400		T3	1135
valid_sources[0x16]	559640	1			T1	262		T2	405		T3	1110
valid_sources[0x17]	556433	1			T1	258		T2	387		T3	1179
valid_sources[0x18]	566552	1			T1	289		T2	458		T3	1145
valid_sources[0x19]	554810	1			T1	251		T2	340		T3	1128
valid_sources[0x1a]	598609	1			T1	240		T2	429		T3	1141
valid_sources[0x1b]	588735	1			T1	213		T2	393		T3	1163
valid_sources[0x1c]	611511	1			T1	220		T2	414		T3	1229
valid_sources[0x1d]	543292	1			T1	258		T2	375		T3	1124
valid_sources[0x1e]	571639	1			T1	263		T2	413		T3	1164
valid_sources[0x1f]	560643	1			T1	197		T2	484		T3	1164
valid_sources[0x20]	547246	1			T1	260		T2	329		T3	1047
valid_sources[0x21]	685052	1			T1	273		T2	376		T3	1178
valid_sources[0x22]	565415	1			T1	274		T2	333		T3	1183
valid_sources[0x23]	579350	1			T1	250		T2	472		T3	1101
valid_sources[0x24]	642582	1			T1	237		T2	362		T3	1094
valid_sources[0x25]	581817	1			T1	229		T2	361		T3	1121
valid_sources[0x26]	621542	1			T1	231		T2	349		T3	1086
valid_sources[0x27]	639358	1			T1	228		T2	433		T3	1099
valid_sources[0x28]	545942	1			T1	239		T2	392		T3	1105
valid_sources[0x29]	596616	1			T1	231		T2	384		T3	1098
valid_sources[0x2a]	1122168	1			T1	216		T2	366		T3	1161
valid_sources[0x2b]	577843	1			T1	327		T2	378		T3	1135
valid_sources[0x2c]	591525	1			T1	296		T2	380		T3	1140
valid_sources[0x2d]	561979	1			T1	330		T2	385		T3	1199
valid_sources[0x2e]	592506	1			T1	269		T2	375		T3	1103
valid_sources[0x2f]	2178824	1			T1	259		T2	398		T3	1176
valid_sources[0x30]	1687772	1			T1	258		T2	335		T3	1120
valid_sources[0x31]	615009	1			T1	250		T2	392		T3	1113
valid_sources[0x32]	596011	1			T1	263		T2	434		T3	1231
valid_sources[0x33]	584538	1			T1	231		T2	411		T3	1104
valid_sources[0x34]	569816	1			T1	266		T2	350		T3	1170
valid_sources[0x35]	597125	1			T1	269		T2	397		T3	1150
valid_sources[0x36]	656562	1			T1	248		T2	439		T3	1157
valid_sources[0x37]	987056	1			T1	269		T2	344		T3	1169
valid_sources[0x38]	553448	1			T1	273		T2	303		T3	1119
valid_sources[0x39]	586576	1			T1	248		T2	370		T3	1235
valid_sources[0x3a]	604408	1			T1	236		T2	357		T3	1115
valid_sources[0x3b]	600276	1			T1	257		T2	369		T3	1117
valid_sources[0x3c]	606518	1			T1	192		T2	385		T3	1130
valid_sources[0x3d]	551038	1			T1	235		T2	416		T3	1134
valid_sources[0x3e]	579633	1			T1	197		T2	351		T3	1112
valid_sources[0x3f]	695407	1			T1	273		T2	409		T3	1140
valid_sources[0x40]	548663	1			T1	229		T2	434		T3	1138
valid_sources[0x41]	566946	1			T1	241		T2	437		T3	1196
valid_sources[0x42]	587792	1			T1	263		T2	355		T3	1210
valid_sources[0x43]	577637	1			T1	270		T2	369		T3	1136
valid_sources[0x44]	538936	1			T1	296		T2	372		T3	1087
valid_sources[0x45]	599541	1			T1	220		T2	441		T3	1093
valid_sources[0x46]	657620	1			T1	243		T2	329		T3	1151
valid_sources[0x47]	609183	1			T1	234		T2	453		T3	1185
valid_sources[0x48]	678135	1			T1	246		T2	402		T3	1094
valid_sources[0x49]	570029	1			T1	218		T2	312		T3	1128
valid_sources[0x4a]	551448	1			T1	229		T2	422		T3	1053
valid_sources[0x4b]	539378	1			T1	228		T2	348		T3	1171
valid_sources[0x4c]	545929	1			T1	236		T2	349		T3	1134
valid_sources[0x4d]	1051902	1			T1	221		T2	413		T3	1140
valid_sources[0x4e]	553045	1			T1	250		T2	396		T3	1159
valid_sources[0x4f]	568959	1			T1	213		T2	395		T3	1055
valid_sources[0x50]	551918	1			T1	229		T2	373		T3	1189
valid_sources[0x51]	551270	1			T1	208		T2	424		T3	1130
valid_sources[0x52]	552240	1			T1	275		T2	400		T3	1172
valid_sources[0x53]	607990	1			T1	259		T2	410		T3	1042
valid_sources[0x54]	569213	1			T1	243		T2	383		T3	1092
valid_sources[0x55]	598234	1			T1	313		T2	419		T3	1102
valid_sources[0x56]	539029	1			T1	240		T2	378		T3	1141
valid_sources[0x57]	1933045	1			T1	251		T2	427		T3	1098
valid_sources[0x58]	551831	1			T1	219		T2	337		T3	1143
valid_sources[0x59]	607199	1			T1	252		T2	341		T3	1174
valid_sources[0x5a]	602540	1			T1	229		T2	390		T3	1158
valid_sources[0x5b]	544408	1			T1	260		T2	395		T3	1123
valid_sources[0x5c]	643927	1			T1	307		T2	463		T3	1152
valid_sources[0x5d]	623693	1			T1	238		T2	397		T3	1153
valid_sources[0x5e]	567066	1			T1	240		T2	309		T3	1168
valid_sources[0x5f]	644213	1			T1	285		T2	423		T3	1122
valid_sources[0x60]	555736	1			T1	279		T2	405		T3	1130
valid_sources[0x61]	569894	1			T1	278		T2	430		T3	1122
valid_sources[0x62]	543899	1			T1	274		T2	367		T3	1108
valid_sources[0x63]	548925	1			T1	294		T2	357		T3	1166
valid_sources[0x64]	594099	1			T1	246		T2	409		T3	1098
valid_sources[0x65]	578292	1			T1	292		T2	389		T3	1089
valid_sources[0x66]	631821	1			T1	264		T2	367		T3	1137
valid_sources[0x67]	584469	1			T1	263		T2	371		T3	1221
valid_sources[0x68]	557191	1			T1	268		T2	393		T3	1156
valid_sources[0x69]	785543	1			T1	302		T2	428		T3	1150
valid_sources[0x6a]	558946	1			T1	254		T2	374		T3	1177
valid_sources[0x6b]	764728	1			T1	247		T2	381		T3	1127
valid_sources[0x6c]	591431	1			T1	262		T2	359		T3	1174
valid_sources[0x6d]	577733	1			T1	227		T2	479		T3	1149
valid_sources[0x6e]	560385	1			T1	236		T2	393		T3	1178
valid_sources[0x6f]	542009	1			T1	243		T2	424		T3	1143
valid_sources[0x70]	556718	1			T1	232		T2	401		T3	1187
valid_sources[0x71]	563754	1			T1	339		T2	376		T3	1134
valid_sources[0x72]	564110	1			T1	308		T2	412		T3	1188
valid_sources[0x73]	546350	1			T1	247		T2	425		T3	1033
valid_sources[0x74]	573392	1			T1	221		T2	411		T3	1144
valid_sources[0x75]	2208189	1			T1	296		T2	358		T3	1166
valid_sources[0x76]	534685	1			T1	186		T2	348		T3	1130
valid_sources[0x77]	610187	1			T1	273		T2	418		T3	1151
valid_sources[0x78]	656657	1			T1	246		T2	385		T3	1168
valid_sources[0x79]	737768	1			T1	250		T2	394		T3	1122
valid_sources[0x7a]	547549	1			T1	227		T2	443		T3	1157
valid_sources[0x7b]	586043	1			T1	271		T2	383		T3	1096
valid_sources[0x7c]	614386	1			T1	221		T2	371		T3	1172
valid_sources[0x7d]	553736	1			T1	290		T2	423		T3	1071
valid_sources[0x7e]	611671	1			T1	184		T2	393		T3	1159
valid_sources[0x7f]	618049	1			T1	207		T2	362		T3	1206
valid_sources[0x80]	604651	1			T1	221		T2	379		T3	1128

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

77926175

1

T1

290

T2

32768

T3

26335

values[0x0]

all_enables

biggest_size

40251196

1

T1

1475

T2

32778

T3

13307

values[0x1]

all_enables

biggest_size

40246651

1

T1

1450

T2

32757

T3

13216

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35277	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

163787

1

T1

1

T3

2

T8

731

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57397	1			T8	216		T10	1002		T5	34
values[0x0]	68218	1			T1	1		T3	4		T8	248
values[0x1]	73449	1			T3	4		T4	1		T8	320

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26500	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

172564

1

T1

1

T3

2

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	864	1			T13	6		T7	3		T48	9
valid_sources[0x01]	1053	1			T8	2		T12	1		T13	15
valid_sources[0x02]	898	1			T8	2		T10	3		T13	14
valid_sources[0x03]	632	1			T8	2		T13	8		T32	99
valid_sources[0x04]	1015	1			T8	4		T13	8		T32	71
valid_sources[0x05]	1222	1			T8	2		T10	2		T13	9
valid_sources[0x06]	612	1			T8	1		T10	78		T13	6
valid_sources[0x07]	751	1			T8	3		T13	3		T32	11
valid_sources[0x08]	886	1			T8	5		T10	8		T13	9
valid_sources[0x09]	966	1			T8	1		T10	3		T13	5
valid_sources[0x0a]	704	1			T8	4		T13	2		T32	107
valid_sources[0x0b]	622	1			T8	3		T13	8		T32	4
valid_sources[0x0c]	665	1			T8	1		T13	10		T32	5
valid_sources[0x0d]	574	1			T8	1		T13	9		T26	4
valid_sources[0x0e]	621	1			T8	5		T13	14		T121	1
valid_sources[0x0f]	646	1			T8	3		T13	7		T32	5
valid_sources[0x10]	630	1			T8	4		T13	3		T32	7
valid_sources[0x11]	914	1			T8	2		T13	10		T7	3
valid_sources[0x12]	673	1			T8	4		T10	2		T13	3
valid_sources[0x13]	724	1			T8	3		T10	1		T13	5
valid_sources[0x14]	974	1			T8	4		T10	3		T13	7
valid_sources[0x15]	621	1			T8	3		T13	6		T32	11
valid_sources[0x16]	673	1			T8	4		T13	6		T32	40
valid_sources[0x17]	774	1			T8	6		T12	5		T13	11
valid_sources[0x18]	1097	1			T8	1		T13	4		T32	1
valid_sources[0x19]	882	1			T8	5		T13	13		T32	1
valid_sources[0x1a]	626	1			T8	2		T13	2		T32	15
valid_sources[0x1b]	847	1			T8	3		T10	24		T13	8
valid_sources[0x1c]	624	1			T8	5		T13	16		T32	16
valid_sources[0x1d]	1201	1			T8	3		T13	7		T32	111
valid_sources[0x1e]	781	1			T8	2		T13	3		T30	1
valid_sources[0x1f]	576	1			T8	2		T13	8		T92	5
valid_sources[0x20]	597	1			T13	7		T32	2		T7	1
valid_sources[0x21]	794	1			T8	1		T13	10		T32	51
valid_sources[0x22]	803	1			T8	6		T13	10		T6	11
valid_sources[0x23]	801	1			T13	7		T47	198		T121	1
valid_sources[0x24]	859	1			T8	2		T13	4		T32	15
valid_sources[0x25]	639	1			T8	2		T10	2		T13	13
valid_sources[0x26]	695	1			T8	6		T13	9		T32	1
valid_sources[0x27]	660	1			T8	4		T13	8		T32	1
valid_sources[0x28]	718	1			T8	5		T10	27		T13	9
valid_sources[0x29]	538	1			T8	2		T10	2		T13	8
valid_sources[0x2a]	771	1			T8	4		T13	3		T32	2
valid_sources[0x2b]	678	1			T8	11		T10	2		T13	11
valid_sources[0x2c]	606	1			T8	2		T13	8		T32	3
valid_sources[0x2d]	608	1			T8	3		T13	20		T7	3
valid_sources[0x2e]	790	1			T8	3		T13	7		T32	20
valid_sources[0x2f]	765	1			T8	1		T10	3		T13	6
valid_sources[0x30]	965	1			T8	6		T10	134		T13	9
valid_sources[0x31]	660	1			T8	2		T13	4		T32	1
valid_sources[0x32]	716	1			T8	2		T13	5		T32	31
valid_sources[0x33]	594	1			T8	2		T13	9		T30	1
valid_sources[0x34]	513	1			T8	3		T13	2		T32	4
valid_sources[0x35]	651	1			T8	2		T13	1		T32	1
valid_sources[0x36]	695	1			T13	9		T32	23		T7	2
valid_sources[0x37]	1124	1			T8	5		T13	6		T30	1
valid_sources[0x38]	900	1			T8	6		T10	3		T13	9
valid_sources[0x39]	865	1			T8	3		T13	8		T30	1
valid_sources[0x3a]	611	1			T13	7		T30	2		T28	14
valid_sources[0x3b]	529	1			T8	4		T13	8		T131	1
valid_sources[0x3c]	628	1			T8	3		T13	7		T132	16
valid_sources[0x3d]	680	1			T8	3		T13	9		T55	2
valid_sources[0x3e]	755	1			T8	3		T13	5		T32	43
valid_sources[0x3f]	742	1			T8	3		T10	1		T13	9
valid_sources[0x40]	626	1			T8	3		T13	7		T7	1
valid_sources[0x41]	776	1			T8	5		T13	4		T32	1
valid_sources[0x42]	656	1			T8	4		T13	6		T46	1
valid_sources[0x43]	629	1			T8	4		T13	7		T32	3
valid_sources[0x44]	899	1			T1	1		T8	4		T13	10
valid_sources[0x45]	897	1			T8	2		T13	9		T28	1
valid_sources[0x46]	974	1			T8	2		T13	9		T32	93
valid_sources[0x47]	605	1			T8	2		T10	3		T13	7
valid_sources[0x48]	548	1			T8	3		T10	23		T13	9
valid_sources[0x49]	1043	1			T8	2		T10	155		T13	5
valid_sources[0x4a]	605	1			T8	2		T13	5		T32	77
valid_sources[0x4b]	739	1			T8	2		T13	6		T32	1
valid_sources[0x4c]	671	1			T8	6		T13	1		T32	1
valid_sources[0x4d]	1280	1			T8	4		T10	240		T13	3
valid_sources[0x4e]	1181	1			T8	4		T10	100		T13	7
valid_sources[0x4f]	1101	1			T8	2		T10	219		T13	12
valid_sources[0x50]	578	1			T8	2		T13	7		T29	1
valid_sources[0x51]	1097	1			T8	7		T10	6		T13	4
valid_sources[0x52]	606	1			T8	1		T10	3		T13	4
valid_sources[0x53]	717	1			T8	2		T13	8		T32	56
valid_sources[0x54]	811	1			T8	8		T10	3		T13	10
valid_sources[0x55]	733	1			T8	2		T10	1		T13	10
valid_sources[0x56]	728	1			T8	3		T10	1		T13	16
valid_sources[0x57]	756	1			T8	6		T10	6		T13	4
valid_sources[0x58]	770	1			T8	6		T10	1		T13	6
valid_sources[0x59]	639	1			T4	1		T8	3		T13	4
valid_sources[0x5a]	910	1			T8	2		T13	8		T30	1
valid_sources[0x5b]	887	1			T8	3		T13	10		T32	29
valid_sources[0x5c]	779	1			T8	7		T13	11		T32	1
valid_sources[0x5d]	674	1			T8	3		T10	98		T13	6
valid_sources[0x5e]	743	1			T8	1		T13	12		T32	19
valid_sources[0x5f]	635	1			T8	1		T13	2		T30	3
valid_sources[0x60]	871	1			T8	2		T10	90		T13	6
valid_sources[0x61]	1085	1			T8	1		T10	355		T13	13
valid_sources[0x62]	670	1			T8	4		T7	1		T17	1
valid_sources[0x63]	734	1			T8	3		T10	1		T13	10
valid_sources[0x64]	834	1			T8	2		T10	145		T13	5
valid_sources[0x65]	505	1			T8	7		T13	5		T7	1
valid_sources[0x66]	850	1			T8	1		T13	7		T32	26
valid_sources[0x67]	971	1			T8	2		T10	217		T32	1
valid_sources[0x68]	628	1			T8	2		T13	8		T32	7
valid_sources[0x69]	755	1			T8	4		T10	1		T13	4
valid_sources[0x6a]	768	1			T8	4		T10	2		T13	7
valid_sources[0x6b]	628	1			T8	4		T11	2		T13	7
valid_sources[0x6c]	949	1			T8	2		T10	3		T13	8
valid_sources[0x6d]	818	1			T8	5		T13	3		T32	28
valid_sources[0x6e]	546	1			T8	4		T13	7		T7	1
valid_sources[0x6f]	785	1			T8	1		T10	36		T13	4
valid_sources[0x70]	920	1			T8	7		T13	15		T32	52
valid_sources[0x71]	632	1			T13	14		T32	1		T7	1
valid_sources[0x72]	699	1			T8	3		T13	1		T46	1
valid_sources[0x73]	656	1			T8	4		T13	8		T26	4
valid_sources[0x74]	860	1			T8	1		T13	11		T32	125
valid_sources[0x75]	963	1			T8	3		T19	1		T13	6
valid_sources[0x76]	660	1			T8	2		T13	6		T30	1
valid_sources[0x77]	963	1			T8	4		T10	95		T13	2
valid_sources[0x78]	629	1			T8	2		T13	5		T32	2
valid_sources[0x79]	914	1			T8	2		T13	7		T133	2
valid_sources[0x7a]	734	1			T8	6		T13	4		T32	54
valid_sources[0x7b]	841	1			T8	3		T9	2		T10	1
valid_sources[0x7c]	617	1			T8	6		T13	13		T32	3
valid_sources[0x7d]	645	1			T8	1		T13	7		T32	24
valid_sources[0x7e]	837	1			T8	2		T13	8		T7	1
valid_sources[0x7f]	623	1			T8	4		T10	3		T13	1
valid_sources[0x80]	574	1			T8	5		T10	1		T13	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44699

1

T8

200

T10

931

T5

15

values[0x0]

all_enables

biggest_size

60135

1

T1

1

T3

1

T8

246

values[0x1]

all_enables

biggest_size

58953

1

T3

1

T8

285

T10

1389