Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15918306

1

T1

60995

T3

239029

T4

4523

full_word

155262436

1

T1

3215

T2

98303

T3

52858

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	171180452	1			T1	64210		T2	98303		T3	291887
auto[TlIntgErrCmd]	95	1			T99	8		T100	11		T101	10
auto[TlIntgErrData]	84	1			T99	9		T100	5		T101	5
auto[TlIntgErrBoth]	111	1			T99	3		T100	4		T101	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82629733

1

T1

32038

T2

32768

T3

145896

auto[1]

88551009

1

T1

32172

T2

65535

T3

145991

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7783515	1			T1	31748		T3	119561		T4	2256
auto[TlIntgErrNone]	partial	auto[1]	8134528	1			T1	29247		T3	119468		T4	2267
auto[TlIntgErrNone]	full_word	auto[0]	74846085	1			T1	290		T2	32768		T3	26335
auto[TlIntgErrNone]	full_word	auto[1]	80416324	1			T1	2925		T2	65535		T3	26523
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T99	3		T100	5		T101	4
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T99	5		T100	6		T101	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T101	1		T116	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T109	1		T117	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T99	1		T100	1		T101	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T99	6		T100	3		T101	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T99	1		T100	1		T113	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T99	1		T112	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T99	2		T100	1		T101	4
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T99	1		T100	3		T101	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T111	1		T116	1		T118	2
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T109	1		T119	1		T120	3