Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	628935	1			T1	4261		T13	63		T14	1510
auto[1]	10739709	1			T1	4724		T3	16892		T4	12
auto[2]	469164	1			T1	4274		T13	80		T14	1328
auto[3]	10473491	1			T1	4822		T3	16870		T4	19

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13796739	1			T1	14		T3	424		T9	336
auto[1]	2050059	1			T1	401		T3	3797		T4	1
auto[2]	2091296	1			T1	811		T3	3862		T9	2749
auto[3]	4373205	1			T1	16855		T3	25679		T4	30

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9256582

1

T1

18080

T4

31

T9

4

auto[1]

13054717

1

T1

1

T3

33762

T9

24662

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	282626	1			T13	50		T14	1234		T7	6088
auto[0]	auto[0]	auto[1]	29488	1			T1	34		T13	6		T14	133
auto[0]	auto[0]	auto[2]	29612	1			T1	27		T13	7		T14	131
auto[0]	auto[0]	auto[3]	77964	1			T1	4200		T14	12		T7	58
auto[0]	auto[1]	auto[0]	3086159	1			T1	4		T10	33		T11	1537
auto[0]	auto[1]	auto[1]	325383	1			T1	41		T4	1		T9	1
auto[0]	auto[1]	auto[2]	360336	1			T1	266		T10	1		T11	336
auto[0]	auto[1]	auto[3]	617656	1			T1	4413		T4	11		T9	3
auto[0]	auto[2]	auto[0]	189980	1			T1	1		T13	74		T14	1099
auto[0]	auto[2]	auto[1]	24842	1			T1	234		T13	1		T14	112
auto[0]	auto[2]	auto[2]	19212	1			T1	40		T13	4		T14	106
auto[0]	auto[2]	auto[3]	58360	1			T1	3999		T13	1		T14	11
auto[0]	auto[3]	auto[0]	2905671	1			T1	9		T10	31		T11	1466
auto[0]	auto[3]	auto[1]	337499	1			T1	92		T10	2		T11	331
auto[0]	auto[3]	auto[2]	349711	1			T1	478		T10	13		T11	331
auto[0]	auto[3]	auto[3]	562083	1			T1	4242		T4	19		T10	1
auto[1]	auto[0]	auto[0]	6897	1			T124	303		T125	1		T126	1
auto[1]	auto[0]	auto[1]	31107	1			T124	1422		T127	5556		T128	1762
auto[1]	auto[0]	auto[2]	31213	1			T124	1454		T127	5596		T128	1798
auto[1]	auto[0]	auto[3]	140028	1			T87	3		T43	2		T124	6426
auto[1]	auto[1]	auto[0]	3660554	1			T3	215		T9	185		T12	69204
auto[1]	auto[1]	auto[1]	648575	1			T3	2854		T9	2067		T12	7227
auto[1]	auto[1]	auto[2]	630761	1			T3	979		T9	739		T12	6856
auto[1]	auto[1]	auto[3]	1410285	1			T3	12844		T9	9354		T12	682
auto[1]	auto[2]	auto[0]	6014	1			T124	189		T129	1		T130	1
auto[1]	auto[2]	auto[1]	26823	1			T124	872		T127	5202		T128	1062
auto[1]	auto[2]	auto[2]	26281	1			T108	1		T124	1601		T127	4710
auto[1]	auto[2]	auto[3]	117652	1			T124	7113		T127	21319		T128	7483
auto[1]	auto[3]	auto[0]	3658838	1			T3	209		T9	151		T12	68823
auto[1]	auto[3]	auto[1]	626342	1			T3	943		T9	808		T12	7059
auto[1]	auto[3]	auto[2]	644170	1			T3	2883		T9	2010		T12	7006
auto[1]	auto[3]	auto[3]	1389177	1			T1	1		T3	12835		T9	9348