Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1106252911	162815	0	0
ctrl_regwen_rd_A	1106252911	7438	0	0
exec_rd_A	1106252911	7181	0	0
exec_regwen_rd_A	1106252911	7842	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106252911	162815	0	0
T5	111146	0	0	0
T8	15123	456	0	0
T9	166248	0	0	0
T10	176955	2686	0	0
T11	72468	0	0	0
T12	430940	0	0	0
T13	135317	2878	0	0
T15	206523	0	0	0
T19	34514	0	0	0
T23	697	0	0	0
T32	0	4096	0	0
T47	0	661	0	0
T48	0	1964	0	0
T49	0	9021	0	0
T50	0	859	0	0
T51	0	428	0	0
T52	0	5601	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106252911	7438	0	0
T5	111146	0	0	0
T8	15123	99	0	0
T9	166248	0	0	0
T10	176955	350	0	0
T11	72468	0	0	0
T12	430940	0	0	0
T13	135317	0	0	0
T15	206523	0	0	0
T19	34514	0	0	0
T23	697	0	0	0
T48	0	578	0	0
T50	0	136	0	0
T51	0	109	0	0
T102	0	690	0	0
T103	0	476	0	0
T104	0	185	0	0
T105	0	762	0	0
T106	0	289	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106252911	7181	0	0
T5	111146	0	0	0
T8	15123	46	0	0
T9	166248	0	0	0
T10	176955	294	0	0
T11	72468	0	0	0
T12	430940	0	0	0
T13	135317	0	0	0
T15	206523	0	0	0
T19	34514	0	0	0
T23	697	0	0	0
T48	0	525	0	0
T50	0	216	0	0
T51	0	123	0	0
T102	0	671	0	0
T103	0	403	0	0
T104	0	155	0	0
T105	0	745	0	0
T106	0	248	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106252911	7842	0	0
T5	111146	0	0	0
T8	15123	62	0	0
T9	166248	0	0	0
T10	176955	358	0	0
T11	72468	0	0	0
T12	430940	0	0	0
T13	135317	0	0	0
T15	206523	0	0	0
T19	34514	0	0	0
T23	697	0	0	0
T48	0	543	0	0
T50	0	213	0	0
T51	0	187	0	0
T102	0	761	0	0
T103	0	562	0	0
T104	0	179	0	0
T105	0	768	0	0
T106	0	327	0	0