| T792 |
/workspace/coverage/default/19.sram_ctrl_partial_access.1711863563 |
|
|
Apr 18 02:34:03 PM PDT 24 |
Apr 18 02:36:58 PM PDT 24 |
5637531394 ps |
| T793 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2616084756 |
|
|
Apr 18 02:31:46 PM PDT 24 |
Apr 18 02:40:54 PM PDT 24 |
14317490612 ps |
| T794 |
/workspace/coverage/default/28.sram_ctrl_regwen.4067343062 |
|
|
Apr 18 02:37:23 PM PDT 24 |
Apr 18 02:59:55 PM PDT 24 |
16454327688 ps |
| T795 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3528080407 |
|
|
Apr 18 02:35:31 PM PDT 24 |
Apr 18 02:39:53 PM PDT 24 |
4939094518 ps |
| T796 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1538608758 |
|
|
Apr 18 02:45:09 PM PDT 24 |
Apr 18 02:45:10 PM PDT 24 |
18694336 ps |
| T797 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1418406912 |
|
|
Apr 18 02:39:41 PM PDT 24 |
Apr 18 02:39:48 PM PDT 24 |
3541183522 ps |
| T798 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.375328366 |
|
|
Apr 18 02:37:35 PM PDT 24 |
Apr 18 02:38:34 PM PDT 24 |
6613101254 ps |
| T799 |
/workspace/coverage/default/23.sram_ctrl_bijection.3995107135 |
|
|
Apr 18 02:35:31 PM PDT 24 |
Apr 18 02:44:48 PM PDT 24 |
37065516906 ps |
| T800 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2754867535 |
|
|
Apr 18 02:33:39 PM PDT 24 |
Apr 18 02:34:31 PM PDT 24 |
5241023473 ps |
| T801 |
/workspace/coverage/default/2.sram_ctrl_alert_test.3619184097 |
|
|
Apr 18 02:30:51 PM PDT 24 |
Apr 18 02:30:52 PM PDT 24 |
13145392 ps |
| T802 |
/workspace/coverage/default/9.sram_ctrl_alert_test.2561871793 |
|
|
Apr 18 02:31:46 PM PDT 24 |
Apr 18 02:31:47 PM PDT 24 |
18824774 ps |
| T803 |
/workspace/coverage/default/2.sram_ctrl_smoke.450060357 |
|
|
Apr 18 02:30:41 PM PDT 24 |
Apr 18 02:32:37 PM PDT 24 |
1855927832 ps |
| T804 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1552425337 |
|
|
Apr 18 02:38:35 PM PDT 24 |
Apr 18 02:38:49 PM PDT 24 |
744244271 ps |
| T805 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3671305935 |
|
|
Apr 18 02:37:59 PM PDT 24 |
Apr 18 02:38:00 PM PDT 24 |
35655704 ps |
| T806 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1737215498 |
|
|
Apr 18 02:38:56 PM PDT 24 |
Apr 18 02:39:57 PM PDT 24 |
1532303944 ps |
| T807 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.3023723164 |
|
|
Apr 18 02:35:10 PM PDT 24 |
Apr 18 02:50:59 PM PDT 24 |
16711649414 ps |
| T808 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.2622382034 |
|
|
Apr 18 02:34:32 PM PDT 24 |
Apr 18 02:35:13 PM PDT 24 |
2989457640 ps |
| T809 |
/workspace/coverage/default/40.sram_ctrl_partial_access.2506333463 |
|
|
Apr 18 02:41:56 PM PDT 24 |
Apr 18 02:42:01 PM PDT 24 |
805765253 ps |
| T810 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3894543651 |
|
|
Apr 18 02:32:17 PM PDT 24 |
Apr 18 02:34:50 PM PDT 24 |
6550091930 ps |
| T811 |
/workspace/coverage/default/7.sram_ctrl_smoke.2904669497 |
|
|
Apr 18 02:31:23 PM PDT 24 |
Apr 18 02:31:50 PM PDT 24 |
1517065939 ps |
| T812 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1172632748 |
|
|
Apr 18 02:36:07 PM PDT 24 |
Apr 18 02:38:04 PM PDT 24 |
1623276747 ps |
| T813 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1895103323 |
|
|
Apr 18 02:41:42 PM PDT 24 |
Apr 18 02:41:46 PM PDT 24 |
345439948 ps |
| T814 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2865898854 |
|
|
Apr 18 02:31:46 PM PDT 24 |
Apr 18 02:33:52 PM PDT 24 |
3270284039 ps |
| T815 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3804644132 |
|
|
Apr 18 02:33:15 PM PDT 24 |
Apr 18 02:37:18 PM PDT 24 |
49740462805 ps |
| T816 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.3799929394 |
|
|
Apr 18 02:42:01 PM PDT 24 |
Apr 18 02:44:11 PM PDT 24 |
4296835933 ps |
| T817 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.1185057749 |
|
|
Apr 18 02:33:36 PM PDT 24 |
Apr 18 02:33:40 PM PDT 24 |
351502178 ps |
| T818 |
/workspace/coverage/default/23.sram_ctrl_partial_access.740971411 |
|
|
Apr 18 02:35:32 PM PDT 24 |
Apr 18 02:35:51 PM PDT 24 |
2087519619 ps |
| T819 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.4104636516 |
|
|
Apr 18 02:41:48 PM PDT 24 |
Apr 18 02:42:00 PM PDT 24 |
747379799 ps |
| T820 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1893987972 |
|
|
Apr 18 02:45:18 PM PDT 24 |
Apr 18 02:45:30 PM PDT 24 |
1421892422 ps |
| T821 |
/workspace/coverage/default/24.sram_ctrl_partial_access.429227915 |
|
|
Apr 18 02:35:57 PM PDT 24 |
Apr 18 02:36:03 PM PDT 24 |
433512359 ps |
| T822 |
/workspace/coverage/default/46.sram_ctrl_partial_access.382405537 |
|
|
Apr 18 02:44:19 PM PDT 24 |
Apr 18 02:44:45 PM PDT 24 |
2459020877 ps |
| T823 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1011808420 |
|
|
Apr 18 02:41:06 PM PDT 24 |
Apr 18 02:44:23 PM PDT 24 |
3944835021 ps |
| T824 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.4121243713 |
|
|
Apr 18 02:44:35 PM PDT 24 |
Apr 18 02:48:41 PM PDT 24 |
16410273045 ps |
| T825 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.3575119763 |
|
|
Apr 18 02:38:36 PM PDT 24 |
Apr 18 02:42:38 PM PDT 24 |
16422262616 ps |
| T826 |
/workspace/coverage/default/4.sram_ctrl_stress_all.4286150813 |
|
|
Apr 18 02:30:57 PM PDT 24 |
Apr 18 03:02:35 PM PDT 24 |
132438172880 ps |
| T827 |
/workspace/coverage/default/41.sram_ctrl_bijection.816075321 |
|
|
Apr 18 02:42:07 PM PDT 24 |
Apr 18 03:03:04 PM PDT 24 |
19481929683 ps |
| T828 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.277003255 |
|
|
Apr 18 02:37:13 PM PDT 24 |
Apr 18 02:44:23 PM PDT 24 |
23389611407 ps |
| T829 |
/workspace/coverage/default/20.sram_ctrl_alert_test.631839461 |
|
|
Apr 18 02:34:46 PM PDT 24 |
Apr 18 02:34:47 PM PDT 24 |
15119642 ps |
| T830 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2946262224 |
|
|
Apr 18 02:36:23 PM PDT 24 |
Apr 18 02:55:55 PM PDT 24 |
17910244220 ps |
| T831 |
/workspace/coverage/default/37.sram_ctrl_partial_access.943579495 |
|
|
Apr 18 02:40:44 PM PDT 24 |
Apr 18 02:41:30 PM PDT 24 |
490400118 ps |
| T832 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1468242096 |
|
|
Apr 18 02:39:25 PM PDT 24 |
Apr 18 02:40:08 PM PDT 24 |
1190497159 ps |
| T833 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1389204564 |
|
|
Apr 18 02:38:03 PM PDT 24 |
Apr 18 02:41:21 PM PDT 24 |
3709069757 ps |
| T834 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.615629226 |
|
|
Apr 18 02:34:09 PM PDT 24 |
Apr 18 02:35:05 PM PDT 24 |
780062251 ps |
| T835 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.263650228 |
|
|
Apr 18 02:40:52 PM PDT 24 |
Apr 18 02:40:56 PM PDT 24 |
1462446006 ps |
| T836 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.2185499998 |
|
|
Apr 18 02:39:55 PM PDT 24 |
Apr 18 02:45:05 PM PDT 24 |
4520056435 ps |
| T837 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.1734954510 |
|
|
Apr 18 02:41:12 PM PDT 24 |
Apr 18 02:43:50 PM PDT 24 |
43063505469 ps |
| T838 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3776107400 |
|
|
Apr 18 02:32:09 PM PDT 24 |
Apr 18 02:32:25 PM PDT 24 |
1148856872 ps |
| T839 |
/workspace/coverage/default/39.sram_ctrl_bijection.3703600398 |
|
|
Apr 18 02:41:28 PM PDT 24 |
Apr 18 02:56:36 PM PDT 24 |
43406758260 ps |
| T840 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3324252844 |
|
|
Apr 18 02:43:35 PM PDT 24 |
Apr 18 02:43:52 PM PDT 24 |
708919615 ps |
| T841 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.1440905229 |
|
|
Apr 18 02:35:25 PM PDT 24 |
Apr 18 02:49:56 PM PDT 24 |
52725437979 ps |
| T842 |
/workspace/coverage/default/27.sram_ctrl_executable.2639962420 |
|
|
Apr 18 02:37:02 PM PDT 24 |
Apr 18 02:44:48 PM PDT 24 |
7205407596 ps |
| T843 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1015867903 |
|
|
Apr 18 02:33:47 PM PDT 24 |
Apr 18 02:34:09 PM PDT 24 |
5803743112 ps |
| T844 |
/workspace/coverage/default/43.sram_ctrl_partial_access.3577813274 |
|
|
Apr 18 02:43:06 PM PDT 24 |
Apr 18 02:43:41 PM PDT 24 |
8520857450 ps |
| T845 |
/workspace/coverage/default/45.sram_ctrl_regwen.458702626 |
|
|
Apr 18 02:44:14 PM PDT 24 |
Apr 18 02:52:34 PM PDT 24 |
3558944232 ps |
| T846 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.13541860 |
|
|
Apr 18 02:32:03 PM PDT 24 |
Apr 18 02:32:06 PM PDT 24 |
710531326 ps |
| T847 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.84607897 |
|
|
Apr 18 02:31:22 PM PDT 24 |
Apr 18 02:33:29 PM PDT 24 |
812106180 ps |
| T848 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3699177509 |
|
|
Apr 18 02:30:39 PM PDT 24 |
Apr 18 02:32:41 PM PDT 24 |
30943292367 ps |
| T849 |
/workspace/coverage/default/43.sram_ctrl_executable.1329605722 |
|
|
Apr 18 02:43:09 PM PDT 24 |
Apr 18 03:01:42 PM PDT 24 |
9803109579 ps |
| T850 |
/workspace/coverage/default/1.sram_ctrl_bijection.3688042061 |
|
|
Apr 18 02:30:38 PM PDT 24 |
Apr 18 03:09:36 PM PDT 24 |
579827364549 ps |
| T851 |
/workspace/coverage/default/6.sram_ctrl_executable.120580982 |
|
|
Apr 18 02:31:08 PM PDT 24 |
Apr 18 02:32:25 PM PDT 24 |
6956200279 ps |
| T852 |
/workspace/coverage/default/28.sram_ctrl_partial_access.882945548 |
|
|
Apr 18 02:37:18 PM PDT 24 |
Apr 18 02:37:28 PM PDT 24 |
1551385937 ps |
| T853 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1440366733 |
|
|
Apr 18 02:33:26 PM PDT 24 |
Apr 18 02:35:32 PM PDT 24 |
2477143433 ps |
| T854 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.1218880163 |
|
|
Apr 18 02:34:45 PM PDT 24 |
Apr 18 02:39:10 PM PDT 24 |
43776896117 ps |
| T855 |
/workspace/coverage/default/46.sram_ctrl_executable.3487717557 |
|
|
Apr 18 02:44:28 PM PDT 24 |
Apr 18 02:46:11 PM PDT 24 |
44227872362 ps |
| T856 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2894419382 |
|
|
Apr 18 02:36:39 PM PDT 24 |
Apr 18 02:38:20 PM PDT 24 |
1557363581 ps |
| T857 |
/workspace/coverage/default/2.sram_ctrl_regwen.1441456168 |
|
|
Apr 18 02:30:53 PM PDT 24 |
Apr 18 02:38:11 PM PDT 24 |
7806007434 ps |
| T858 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2949390451 |
|
|
Apr 18 02:32:13 PM PDT 24 |
Apr 18 02:32:20 PM PDT 24 |
2834831136 ps |
| T859 |
/workspace/coverage/default/34.sram_ctrl_regwen.3247571760 |
|
|
Apr 18 02:39:47 PM PDT 24 |
Apr 18 02:47:02 PM PDT 24 |
17683199659 ps |
| T860 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1524759796 |
|
|
Apr 18 02:44:17 PM PDT 24 |
Apr 18 03:24:07 PM PDT 24 |
100353260847 ps |
| T861 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3455778957 |
|
|
Apr 18 02:40:09 PM PDT 24 |
Apr 18 02:46:05 PM PDT 24 |
10185496183 ps |
| T862 |
/workspace/coverage/default/5.sram_ctrl_regwen.2355780261 |
|
|
Apr 18 02:31:09 PM PDT 24 |
Apr 18 02:33:57 PM PDT 24 |
9272603909 ps |
| T863 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4125556798 |
|
|
Apr 18 02:38:36 PM PDT 24 |
Apr 18 02:38:44 PM PDT 24 |
973187853 ps |
| T864 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2071720489 |
|
|
Apr 18 02:44:03 PM PDT 24 |
Apr 18 02:46:13 PM PDT 24 |
758869335 ps |
| T865 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3671224615 |
|
|
Apr 18 02:30:38 PM PDT 24 |
Apr 18 02:31:07 PM PDT 24 |
3959046686 ps |
| T866 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.2225018920 |
|
|
Apr 18 02:33:30 PM PDT 24 |
Apr 18 02:34:39 PM PDT 24 |
19983865977 ps |
| T867 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.517656158 |
|
|
Apr 18 02:36:22 PM PDT 24 |
Apr 18 02:38:33 PM PDT 24 |
7589960297 ps |
| T868 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.2274346077 |
|
|
Apr 18 02:30:33 PM PDT 24 |
Apr 18 02:31:20 PM PDT 24 |
5634232154 ps |
| T869 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.472009197 |
|
|
Apr 18 02:30:54 PM PDT 24 |
Apr 18 02:35:12 PM PDT 24 |
25883313878 ps |
| T870 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.855996572 |
|
|
Apr 18 02:37:02 PM PDT 24 |
Apr 18 02:38:57 PM PDT 24 |
128197772420 ps |
| T871 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.4269802176 |
|
|
Apr 18 02:32:25 PM PDT 24 |
Apr 18 02:32:28 PM PDT 24 |
346026362 ps |
| T872 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1766363071 |
|
|
Apr 18 02:39:11 PM PDT 24 |
Apr 18 02:45:17 PM PDT 24 |
33645998435 ps |
| T873 |
/workspace/coverage/default/40.sram_ctrl_stress_all.3266139882 |
|
|
Apr 18 02:42:02 PM PDT 24 |
Apr 18 03:45:53 PM PDT 24 |
170618680128 ps |
| T874 |
/workspace/coverage/default/5.sram_ctrl_smoke.1163845590 |
|
|
Apr 18 02:30:58 PM PDT 24 |
Apr 18 02:31:28 PM PDT 24 |
2661239572 ps |
| T875 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.4124422197 |
|
|
Apr 18 02:41:57 PM PDT 24 |
Apr 18 02:46:40 PM PDT 24 |
9979498588 ps |
| T876 |
/workspace/coverage/default/25.sram_ctrl_stress_all.3823416168 |
|
|
Apr 18 02:36:27 PM PDT 24 |
Apr 18 04:26:54 PM PDT 24 |
155557987230 ps |
| T877 |
/workspace/coverage/default/44.sram_ctrl_alert_test.469590828 |
|
|
Apr 18 02:43:54 PM PDT 24 |
Apr 18 02:43:55 PM PDT 24 |
24639888 ps |
| T878 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1937787397 |
|
|
Apr 18 02:40:42 PM PDT 24 |
Apr 18 02:43:30 PM PDT 24 |
2934290090 ps |
| T879 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3622090403 |
|
|
Apr 18 02:42:28 PM PDT 24 |
Apr 18 02:42:29 PM PDT 24 |
111871985 ps |
| T880 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.416377557 |
|
|
Apr 18 02:30:39 PM PDT 24 |
Apr 18 02:31:11 PM PDT 24 |
4852429934 ps |
| T881 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.370868589 |
|
|
Apr 18 02:41:06 PM PDT 24 |
Apr 18 02:41:56 PM PDT 24 |
3112019926 ps |
| T882 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.984520614 |
|
|
Apr 18 02:42:22 PM PDT 24 |
Apr 18 02:42:30 PM PDT 24 |
1421646116 ps |
| T883 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.32322304 |
|
|
Apr 18 02:37:43 PM PDT 24 |
Apr 18 02:43:45 PM PDT 24 |
28277882088 ps |
| T884 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3594455890 |
|
|
Apr 18 02:31:35 PM PDT 24 |
Apr 18 02:32:25 PM PDT 24 |
3855207908 ps |
| T885 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4139341272 |
|
|
Apr 18 02:38:51 PM PDT 24 |
Apr 18 02:41:34 PM PDT 24 |
3922649016 ps |
| T80 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3845471884 |
|
|
Apr 18 02:40:34 PM PDT 24 |
Apr 18 02:41:53 PM PDT 24 |
14503364886 ps |
| T886 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.2475417977 |
|
|
Apr 18 02:39:45 PM PDT 24 |
Apr 18 02:39:48 PM PDT 24 |
1341840628 ps |
| T887 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1208312807 |
|
|
Apr 18 02:30:58 PM PDT 24 |
Apr 18 02:33:06 PM PDT 24 |
1618668851 ps |
| T888 |
/workspace/coverage/default/43.sram_ctrl_smoke.1561015809 |
|
|
Apr 18 02:42:58 PM PDT 24 |
Apr 18 02:43:03 PM PDT 24 |
383714572 ps |
| T889 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1918151688 |
|
|
Apr 18 02:45:57 PM PDT 24 |
Apr 18 02:46:19 PM PDT 24 |
3174409849 ps |
| T890 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1637916264 |
|
|
Apr 18 02:45:39 PM PDT 24 |
Apr 18 02:45:55 PM PDT 24 |
3514735093 ps |
| T891 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.413515306 |
|
|
Apr 18 02:32:23 PM PDT 24 |
Apr 18 02:34:52 PM PDT 24 |
11819819128 ps |
| T892 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.285882779 |
|
|
Apr 18 02:40:05 PM PDT 24 |
Apr 18 02:42:04 PM PDT 24 |
1604872100 ps |
| T893 |
/workspace/coverage/default/41.sram_ctrl_regwen.3203528520 |
|
|
Apr 18 02:42:22 PM PDT 24 |
Apr 18 03:00:15 PM PDT 24 |
2339219331 ps |
| T894 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2885306993 |
|
|
Apr 18 02:31:30 PM PDT 24 |
Apr 18 02:39:26 PM PDT 24 |
384717083349 ps |
| T895 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1600600667 |
|
|
Apr 18 02:34:56 PM PDT 24 |
Apr 18 02:38:37 PM PDT 24 |
14289443258 ps |
| T896 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.883164524 |
|
|
Apr 18 02:39:15 PM PDT 24 |
Apr 18 02:40:09 PM PDT 24 |
1479316316 ps |
| T897 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.3344427920 |
|
|
Apr 18 02:42:17 PM PDT 24 |
Apr 18 02:43:43 PM PDT 24 |
119166154644 ps |
| T898 |
/workspace/coverage/default/16.sram_ctrl_alert_test.1287637284 |
|
|
Apr 18 02:33:26 PM PDT 24 |
Apr 18 02:33:26 PM PDT 24 |
16530257 ps |
| T899 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3537210307 |
|
|
Apr 18 02:30:50 PM PDT 24 |
Apr 18 02:37:23 PM PDT 24 |
34382879593 ps |
| T900 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.2970076865 |
|
|
Apr 18 02:31:08 PM PDT 24 |
Apr 18 02:42:23 PM PDT 24 |
52444197321 ps |
| T901 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2749196027 |
|
|
Apr 18 02:34:45 PM PDT 24 |
Apr 18 02:36:11 PM PDT 24 |
32625164576 ps |
| T902 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3484136168 |
|
|
Apr 18 02:43:56 PM PDT 24 |
Apr 18 02:47:35 PM PDT 24 |
35644929560 ps |
| T903 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1540257434 |
|
|
Apr 18 02:35:38 PM PDT 24 |
Apr 18 02:42:45 PM PDT 24 |
18225134618 ps |
| T904 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.3260582668 |
|
|
Apr 18 02:42:23 PM PDT 24 |
Apr 18 02:44:47 PM PDT 24 |
27512426026 ps |
| T905 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4184864112 |
|
|
Apr 18 02:41:57 PM PDT 24 |
Apr 18 02:46:41 PM PDT 24 |
16374812405 ps |
| T906 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2092508350 |
|
|
Apr 18 02:30:51 PM PDT 24 |
Apr 18 02:39:32 PM PDT 24 |
23207419941 ps |
| T907 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1826179270 |
|
|
Apr 18 02:43:04 PM PDT 24 |
Apr 18 02:43:22 PM PDT 24 |
709739459 ps |
| T908 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3318364441 |
|
|
Apr 18 02:30:32 PM PDT 24 |
Apr 18 02:30:36 PM PDT 24 |
697341242 ps |
| T909 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.2627133688 |
|
|
Apr 18 02:41:07 PM PDT 24 |
Apr 18 02:42:28 PM PDT 24 |
89951105614 ps |
| T910 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1291365123 |
|
|
Apr 18 02:31:57 PM PDT 24 |
Apr 18 02:35:23 PM PDT 24 |
7657923279 ps |
| T911 |
/workspace/coverage/default/48.sram_ctrl_partial_access.1866239055 |
|
|
Apr 18 02:45:20 PM PDT 24 |
Apr 18 02:47:33 PM PDT 24 |
3702480061 ps |
| T912 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.681385043 |
|
|
Apr 18 02:38:07 PM PDT 24 |
Apr 18 02:39:34 PM PDT 24 |
68524469204 ps |
| T913 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.4129358088 |
|
|
Apr 18 02:30:41 PM PDT 24 |
Apr 18 02:47:40 PM PDT 24 |
36784690824 ps |
| T914 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2744910328 |
|
|
Apr 18 02:30:57 PM PDT 24 |
Apr 18 02:36:53 PM PDT 24 |
55617881037 ps |
| T915 |
/workspace/coverage/default/20.sram_ctrl_stress_all.3626820506 |
|
|
Apr 18 02:34:47 PM PDT 24 |
Apr 18 03:25:27 PM PDT 24 |
40190826075 ps |
| T916 |
/workspace/coverage/default/40.sram_ctrl_executable.4234088463 |
|
|
Apr 18 02:42:00 PM PDT 24 |
Apr 18 03:05:36 PM PDT 24 |
19642740250 ps |
| T917 |
/workspace/coverage/default/0.sram_ctrl_stress_all.210812029 |
|
|
Apr 18 02:30:36 PM PDT 24 |
Apr 18 05:02:34 PM PDT 24 |
94128044228 ps |
| T918 |
/workspace/coverage/default/0.sram_ctrl_bijection.834554371 |
|
|
Apr 18 02:30:35 PM PDT 24 |
Apr 18 02:44:34 PM PDT 24 |
173250767753 ps |
| T919 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1685208417 |
|
|
Apr 18 02:34:24 PM PDT 24 |
Apr 18 02:34:48 PM PDT 24 |
1934253384 ps |
| T920 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.1204532444 |
|
|
Apr 18 02:32:23 PM PDT 24 |
Apr 18 02:34:48 PM PDT 24 |
7341349378 ps |
| T921 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1936685316 |
|
|
Apr 18 02:31:10 PM PDT 24 |
Apr 18 02:35:54 PM PDT 24 |
27727507234 ps |
| T922 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1353720689 |
|
|
Apr 18 02:31:41 PM PDT 24 |
Apr 18 04:07:56 PM PDT 24 |
311924675218 ps |
| T923 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2784872151 |
|
|
Apr 18 02:39:15 PM PDT 24 |
Apr 18 02:39:34 PM PDT 24 |
6658666789 ps |
| T924 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1078105248 |
|
|
Apr 18 02:43:39 PM PDT 24 |
Apr 18 02:44:03 PM PDT 24 |
19799292748 ps |
| T925 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3394056367 |
|
|
Apr 18 02:30:41 PM PDT 24 |
Apr 18 02:40:13 PM PDT 24 |
29866661775 ps |
| T926 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.2319483519 |
|
|
Apr 18 02:36:02 PM PDT 24 |
Apr 18 02:38:42 PM PDT 24 |
1501916435 ps |
| T927 |
/workspace/coverage/default/35.sram_ctrl_executable.3651101 |
|
|
Apr 18 02:40:00 PM PDT 24 |
Apr 18 02:57:56 PM PDT 24 |
9839458035 ps |
| T928 |
/workspace/coverage/default/36.sram_ctrl_regwen.1808867830 |
|
|
Apr 18 02:40:27 PM PDT 24 |
Apr 18 02:52:05 PM PDT 24 |
4712677210 ps |
| T929 |
/workspace/coverage/default/32.sram_ctrl_regwen.2717754865 |
|
|
Apr 18 02:38:57 PM PDT 24 |
Apr 18 02:40:04 PM PDT 24 |
3701186971 ps |
| T930 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.426105350 |
|
|
Apr 18 02:30:33 PM PDT 24 |
Apr 18 02:31:14 PM PDT 24 |
1489412658 ps |
| T931 |
/workspace/coverage/default/23.sram_ctrl_regwen.1517663122 |
|
|
Apr 18 02:35:46 PM PDT 24 |
Apr 18 02:58:23 PM PDT 24 |
2800304438 ps |
| T932 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2089272649 |
|
|
Apr 18 02:36:33 PM PDT 24 |
Apr 18 02:37:07 PM PDT 24 |
2421553683 ps |
| T933 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3393949470 |
|
|
Apr 18 02:39:06 PM PDT 24 |
Apr 18 02:39:23 PM PDT 24 |
1450443252 ps |
| T934 |
/workspace/coverage/default/20.sram_ctrl_regwen.2302077832 |
|
|
Apr 18 02:34:35 PM PDT 24 |
Apr 18 02:46:20 PM PDT 24 |
7849382417 ps |
| T935 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.96223053 |
|
|
Apr 18 02:44:05 PM PDT 24 |
Apr 18 02:54:57 PM PDT 24 |
117788093024 ps |
| T936 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.225935296 |
|
|
Apr 18 02:44:34 PM PDT 24 |
Apr 18 02:44:37 PM PDT 24 |
363766032 ps |
| T937 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.770865329 |
|
|
Apr 18 02:31:14 PM PDT 24 |
Apr 18 02:35:32 PM PDT 24 |
23758356473 ps |
| T89 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2326538321 |
|
|
Apr 18 01:51:25 PM PDT 24 |
Apr 18 01:51:27 PM PDT 24 |
50860384 ps |
| T56 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1475593784 |
|
|
Apr 18 01:50:55 PM PDT 24 |
Apr 18 01:50:56 PM PDT 24 |
31517400 ps |
| T98 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3495850907 |
|
|
Apr 18 01:51:11 PM PDT 24 |
Apr 18 01:51:13 PM PDT 24 |
10646421 ps |
| T938 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2341928086 |
|
|
Apr 18 01:51:08 PM PDT 24 |
Apr 18 01:51:11 PM PDT 24 |
772003183 ps |
| T90 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1979536026 |
|
|
Apr 18 01:51:29 PM PDT 24 |
Apr 18 01:51:30 PM PDT 24 |
27011872 ps |
| T939 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2494294431 |
|
|
Apr 18 01:51:07 PM PDT 24 |
Apr 18 01:51:11 PM PDT 24 |
457160711 ps |
| T940 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.287308885 |
|
|
Apr 18 01:51:25 PM PDT 24 |
Apr 18 01:51:30 PM PDT 24 |
102402856 ps |
| T99 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2642223567 |
|
|
Apr 18 01:51:08 PM PDT 24 |
Apr 18 01:51:12 PM PDT 24 |
325740729 ps |
| T57 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1960977274 |
|
|
Apr 18 01:51:12 PM PDT 24 |
Apr 18 01:51:13 PM PDT 24 |
88932057 ps |
| T58 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2525787514 |
|
|
Apr 18 01:51:17 PM PDT 24 |
Apr 18 01:51:56 PM PDT 24 |
36940315168 ps |
| T941 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1999687439 |
|
|
Apr 18 01:51:21 PM PDT 24 |
Apr 18 01:51:26 PM PDT 24 |
41212155 ps |
| T59 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.419667169 |
|
|
Apr 18 01:51:26 PM PDT 24 |
Apr 18 01:51:28 PM PDT 24 |
19616296 ps |
| T60 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.839392645 |
|
|
Apr 18 01:51:22 PM PDT 24 |
Apr 18 01:51:23 PM PDT 24 |
36251519 ps |
| T91 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2300497207 |
|
|
Apr 18 01:51:01 PM PDT 24 |
Apr 18 01:51:02 PM PDT 24 |
15345107 ps |
| T61 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3824785998 |
|
|
Apr 18 01:51:09 PM PDT 24 |
Apr 18 01:51:39 PM PDT 24 |
16051796320 ps |
| T62 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3513739082 |
|
|
Apr 18 01:51:07 PM PDT 24 |
Apr 18 01:51:08 PM PDT 24 |
70033980 ps |
| T942 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1900422207 |
|
|
Apr 18 01:51:09 PM PDT 24 |
Apr 18 01:51:11 PM PDT 24 |
12735149 ps |
| T63 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.905703315 |
|
|
Apr 18 01:51:03 PM PDT 24 |
Apr 18 01:51:04 PM PDT 24 |
29710688 ps |
| T943 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.68351616 |
|
|
Apr 18 01:51:12 PM PDT 24 |
Apr 18 01:51:14 PM PDT 24 |
44817521 ps |
| T64 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3920290407 |
|
|
Apr 18 01:51:27 PM PDT 24 |
Apr 18 01:51:29 PM PDT 24 |
23361719 ps |
| T65 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.884560199 |
|
|
Apr 18 01:51:21 PM PDT 24 |
Apr 18 01:52:11 PM PDT 24 |
7152791787 ps |
| T68 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2659714811 |
|
|
Apr 18 01:51:22 PM PDT 24 |
Apr 18 01:51:23 PM PDT 24 |
93317309 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3794355404 |
|
|
Apr 18 01:50:53 PM PDT 24 |
Apr 18 01:51:24 PM PDT 24 |
8027875260 ps |
| T945 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1807642511 |
|
|
Apr 18 01:51:08 PM PDT 24 |
Apr 18 01:51:11 PM PDT 24 |
91379283 ps |
| T946 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1723748514 |
|
|
Apr 18 01:51:35 PM PDT 24 |
Apr 18 01:51:36 PM PDT 24 |
18703529 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2172671323 |
|
|
Apr 18 01:51:14 PM PDT 24 |
Apr 18 01:51:17 PM PDT 24 |
508052927 ps |
| T948 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1298043743 |
|
|
Apr 18 01:51:13 PM PDT 24 |
Apr 18 01:51:14 PM PDT 24 |
37760397 ps |
| T949 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1698128099 |
|
|
Apr 18 01:51:22 PM PDT 24 |
Apr 18 01:51:23 PM PDT 24 |
37771794 ps |
| T950 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3661954804 |
|
|
Apr 18 01:51:12 PM PDT 24 |
Apr 18 01:51:15 PM PDT 24 |
332835055 ps |
| T951 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4222473904 |
|
|
Apr 18 01:51:07 PM PDT 24 |
Apr 18 01:51:09 PM PDT 24 |
28949518 ps |
| T952 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3313904199 |
|
|
Apr 18 01:51:14 PM PDT 24 |
Apr 18 01:51:19 PM PDT 24 |
567102553 ps |
| T100 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4216621909 |
|
|
Apr 18 01:51:24 PM PDT 24 |
Apr 18 01:51:27 PM PDT 24 |
240782124 ps |
| T953 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2834300231 |
|
|
Apr 18 01:51:08 PM PDT 24 |
Apr 18 01:51:11 PM PDT 24 |
381445271 ps |
| T69 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.29096943 |
|
|
Apr 18 01:51:03 PM PDT 24 |
Apr 18 01:51:34 PM PDT 24 |
14212210368 ps |
| T70 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1168160475 |
|
|
Apr 18 01:51:19 PM PDT 24 |
Apr 18 01:51:21 PM PDT 24 |
14380172 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1579216738 |
|
|
Apr 18 01:50:55 PM PDT 24 |
Apr 18 01:50:56 PM PDT 24 |
15225325 ps |
| T955 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1750158312 |
|
|
Apr 18 01:51:10 PM PDT 24 |
Apr 18 01:51:14 PM PDT 24 |
328079287 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2739250690 |
|
|
Apr 18 01:51:22 PM PDT 24 |
Apr 18 01:51:23 PM PDT 24 |
34225242 ps |
| T71 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1796629538 |
|
|
Apr 18 01:50:58 PM PDT 24 |
Apr 18 01:51:00 PM PDT 24 |
18568167 ps |
| T957 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.931556471 |
|
|
Apr 18 01:51:08 PM PDT 24 |
Apr 18 01:51:13 PM PDT 24 |
1460240059 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3475236970 |
|
|
Apr 18 01:51:13 PM PDT 24 |
Apr 18 01:51:17 PM PDT 24 |
397512524 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2160735699 |
|
|
Apr 18 01:50:54 PM PDT 24 |
Apr 18 01:50:55 PM PDT 24 |
16051128 ps |
| T960 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1411450921 |
|
|
Apr 18 01:51:26 PM PDT 24 |
Apr 18 01:51:30 PM PDT 24 |
179320928 ps |
| T961 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3845260556 |
|
|
Apr 18 01:50:59 PM PDT 24 |
Apr 18 01:51:02 PM PDT 24 |
218750249 ps |
| T101 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2080723888 |
|
|
Apr 18 01:51:11 PM PDT 24 |
Apr 18 01:51:14 PM PDT 24 |
2203945217 ps |
| T110 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2912092871 |
|
|
Apr 18 01:51:20 PM PDT 24 |
Apr 18 01:51:23 PM PDT 24 |
623062284 ps |
| T113 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2129076614 |
|
|
Apr 18 01:51:20 PM PDT 24 |
Apr 18 01:51:22 PM PDT 24 |
140422996 ps |
| T962 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.743673045 |
|
|
Apr 18 01:51:15 PM PDT 24 |
Apr 18 01:51:19 PM PDT 24 |
719647842 ps |
| T963 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3250266093 |
|
|
Apr 18 01:51:12 PM PDT 24 |
Apr 18 01:51:16 PM PDT 24 |
707084730 ps |
| T109 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1647864594 |
|
|
Apr 18 01:51:09 PM PDT 24 |
Apr 18 01:51:11 PM PDT 24 |
169286188 ps |
| T964 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2170440899 |
|
|
Apr 18 01:51:10 PM PDT 24 |
Apr 18 01:51:15 PM PDT 24 |
382271300 ps |
| T965 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3992857223 |
|
|
Apr 18 01:51:35 PM PDT 24 |
Apr 18 01:51:40 PM PDT 24 |
1431249120 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2494099426 |
|
|
Apr 18 01:50:59 PM PDT 24 |
Apr 18 01:51:00 PM PDT 24 |
138877450 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2356050557 |
|
|
Apr 18 01:51:12 PM PDT 24 |
Apr 18 01:52:06 PM PDT 24 |
14705347079 ps |
| T967 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3704517305 |
|
|
Apr 18 01:51:22 PM PDT 24 |
Apr 18 01:51:24 PM PDT 24 |
24246643 ps |
| T968 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2318086747 |
|
|
Apr 18 01:51:17 PM PDT 24 |
Apr 18 01:51:19 PM PDT 24 |
28136313 ps |
| T969 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1998700559 |
|
|
Apr 18 01:51:15 PM PDT 24 |
Apr 18 01:51:20 PM PDT 24 |
123984372 ps |
| T970 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3387007841 |
|
|
Apr 18 01:52:06 PM PDT 24 |
Apr 18 01:52:07 PM PDT 24 |
17130921 ps |
| T81 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1523586304 |
|
|
Apr 18 01:51:06 PM PDT 24 |
Apr 18 01:51:34 PM PDT 24 |
14745863213 ps |
| T971 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3938694405 |
|
|
Apr 18 01:51:20 PM PDT 24 |
Apr 18 01:51:47 PM PDT 24 |
7427817466 ps |
| T972 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.912190083 |
|
|
Apr 18 01:50:59 PM PDT 24 |
Apr 18 01:51:01 PM PDT 24 |
304886398 ps |
| T973 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1096050825 |
|
|
Apr 18 01:51:10 PM PDT 24 |
Apr 18 01:51:12 PM PDT 24 |
52482817 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3565731304 |
|
|
Apr 18 01:50:59 PM PDT 24 |
Apr 18 01:51:01 PM PDT 24 |
265615079 ps |
| T975 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2904256933 |
|
|
Apr 18 01:51:19 PM PDT 24 |
Apr 18 01:51:24 PM PDT 24 |
574290266 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3800598409 |
|
|
Apr 18 01:51:02 PM PDT 24 |
Apr 18 01:51:06 PM PDT 24 |
2334568989 ps |
| T977 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3497474644 |
|
|
Apr 18 01:51:25 PM PDT 24 |
Apr 18 01:51:30 PM PDT 24 |
2307974903 ps |
| T978 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3348669198 |
|
|
Apr 18 01:50:56 PM PDT 24 |
Apr 18 01:51:00 PM PDT 24 |
476796796 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1436105608 |
|
|
Apr 18 01:50:58 PM PDT 24 |
Apr 18 01:50:59 PM PDT 24 |
20487981 ps |
| T980 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.862315648 |
|
|
Apr 18 01:51:07 PM PDT 24 |
Apr 18 01:51:09 PM PDT 24 |
25245486 ps |
| T981 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2233504987 |
|
|
Apr 18 01:51:21 PM PDT 24 |
Apr 18 01:51:24 PM PDT 24 |
69684164 ps |
| T982 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1938319149 |
|
|
Apr 18 01:51:09 PM PDT 24 |
Apr 18 01:51:13 PM PDT 24 |
476815794 ps |
| T983 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3061553071 |
|
|
Apr 18 01:51:22 PM PDT 24 |
Apr 18 01:51:23 PM PDT 24 |
56142480 ps |
| T984 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3435614790 |
|
|
Apr 18 01:51:10 PM PDT 24 |
Apr 18 01:52:03 PM PDT 24 |
7518183481 ps |
| T119 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2473071009 |
|
|
Apr 18 01:51:08 PM PDT 24 |
Apr 18 01:51:11 PM PDT 24 |
130753283 ps |
| T120 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4246026938 |
|
|
Apr 18 01:50:58 PM PDT 24 |
Apr 18 01:51:01 PM PDT 24 |
170822000 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3130658299 |
|
|
Apr 18 01:50:59 PM PDT 24 |
Apr 18 01:51:01 PM PDT 24 |
495347443 ps |
| T986 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2419831128 |
|
|
Apr 18 01:51:17 PM PDT 24 |
Apr 18 01:51:18 PM PDT 24 |
14107832 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.129030471 |
|
|
Apr 18 01:51:08 PM PDT 24 |
Apr 18 01:51:13 PM PDT 24 |
134677022 ps |
| T988 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.677081466 |
|
|
Apr 18 01:51:14 PM PDT 24 |
Apr 18 01:51:19 PM PDT 24 |
1446537653 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2491867465 |
|
|
Apr 18 01:51:21 PM PDT 24 |
Apr 18 01:51:50 PM PDT 24 |
14781724374 ps |
| T82 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2915745555 |
|
|
Apr 18 01:51:10 PM PDT 24 |
Apr 18 01:51:12 PM PDT 24 |
645393366 ps |
| T990 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3977122029 |
|
|
Apr 18 01:51:18 PM PDT 24 |
Apr 18 01:51:21 PM PDT 24 |
322375401 ps |
| T83 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2929337470 |
|
|
Apr 18 01:51:26 PM PDT 24 |
Apr 18 01:52:18 PM PDT 24 |
29306707384 ps |
| T991 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3766443864 |
|
|
Apr 18 01:51:22 PM PDT 24 |
Apr 18 01:52:20 PM PDT 24 |
88064164655 ps |
| T86 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2782934593 |
|
|
Apr 18 01:51:09 PM PDT 24 |
Apr 18 01:51:35 PM PDT 24 |
3880278696 ps |
| T84 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2743563359 |
|
|
Apr 18 01:51:17 PM PDT 24 |
Apr 18 01:51:44 PM PDT 24 |
4562598328 ps |
| T111 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3402986797 |
|
|
Apr 18 01:50:58 PM PDT 24 |
Apr 18 01:51:01 PM PDT 24 |
486905045 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3561097979 |
|
|
Apr 18 01:51:17 PM PDT 24 |
Apr 18 01:51:18 PM PDT 24 |
53318510 ps |
| T993 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1204719234 |
|
|
Apr 18 01:51:20 PM PDT 24 |
Apr 18 01:51:21 PM PDT 24 |
23673760 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2306416721 |
|
|
Apr 18 01:51:24 PM PDT 24 |
Apr 18 01:51:25 PM PDT 24 |
31687160 ps |
| T995 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3391237811 |
|
|
Apr 18 01:51:08 PM PDT 24 |
Apr 18 01:51:09 PM PDT 24 |
13341771 ps |
| T996 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3639202027 |
|
|
Apr 18 01:51:04 PM PDT 24 |
Apr 18 01:51:08 PM PDT 24 |
349896556 ps |
| T997 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1863886295 |
|
|
Apr 18 01:51:11 PM PDT 24 |
Apr 18 01:51:14 PM PDT 24 |
44507519 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.691118970 |
|
|
Apr 18 01:50:52 PM PDT 24 |
Apr 18 01:50:53 PM PDT 24 |
40451417 ps |
| T85 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1364146668 |
|
|
Apr 18 01:51:23 PM PDT 24 |
Apr 18 01:52:14 PM PDT 24 |
29365656406 ps |
| T115 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1709291419 |
|
|
Apr 18 01:51:19 PM PDT 24 |
Apr 18 01:51:22 PM PDT 24 |
630348091 ps |
| T999 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1475853792 |
|
|
Apr 18 01:51:03 PM PDT 24 |
Apr 18 01:51:30 PM PDT 24 |
9254702020 ps |
| T1000 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3919143609 |
|
|
Apr 18 01:51:22 PM PDT 24 |
Apr 18 01:52:11 PM PDT 24 |
7063357638 ps |
| T1001 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2338243128 |
|
|
Apr 18 01:51:07 PM PDT 24 |
Apr 18 01:51:09 PM PDT 24 |
313986863 ps |
| T114 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2198917120 |
|
|
Apr 18 01:50:56 PM PDT 24 |
Apr 18 01:50:58 PM PDT 24 |
299186380 ps |
| T1002 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4196605207 |
|
|
Apr 18 01:51:10 PM PDT 24 |
Apr 18 01:51:14 PM PDT 24 |
712194019 ps |
| T1003 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3249344808 |
|
|
Apr 18 01:51:09 PM PDT 24 |
Apr 18 01:51:35 PM PDT 24 |
4087949829 ps |
| T117 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2889635887 |
|
|
Apr 18 01:51:19 PM PDT 24 |
Apr 18 01:51:21 PM PDT 24 |
124596285 ps |