Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.07	99.81	97.02	100.00	100.00	98.61	99.70	98.33

Total test records in report: 1032

T1004	/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3205777101	Apr 18 01:51:25 PM PDT 24	Apr 18 01:51:27 PM PDT 24	18197690 ps
T1005	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.209755049	Apr 18 01:51:14 PM PDT 24	Apr 18 01:51:19 PM PDT 24	360168811 ps
T1006	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.384194617	Apr 18 01:50:56 PM PDT 24	Apr 18 01:50:58 PM PDT 24	16575906 ps
T1007	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1111639375	Apr 18 01:51:19 PM PDT 24	Apr 18 01:51:20 PM PDT 24	22121660 ps
T1008	/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.424492843	Apr 18 01:51:28 PM PDT 24	Apr 18 01:52:25 PM PDT 24	7397193211 ps
T1009	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.894316814	Apr 18 01:51:02 PM PDT 24	Apr 18 01:51:06 PM PDT 24	1244438211 ps
T1010	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.377132683	Apr 18 01:50:57 PM PDT 24	Apr 18 01:51:01 PM PDT 24	43809184 ps
T112	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2914986624	Apr 18 01:51:28 PM PDT 24	Apr 18 01:51:32 PM PDT 24	363834290 ps
T1011	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1399838297	Apr 18 01:51:20 PM PDT 24	Apr 18 01:51:22 PM PDT 24	122498423 ps
T1012	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4232348455	Apr 18 01:50:56 PM PDT 24	Apr 18 01:51:03 PM PDT 24	6786768365 ps
T1013	/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1848341517	Apr 18 01:51:18 PM PDT 24	Apr 18 01:51:20 PM PDT 24	16831634 ps
T116	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.973198837	Apr 18 01:51:10 PM PDT 24	Apr 18 01:51:13 PM PDT 24	253153020 ps
T1014	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3489332129	Apr 18 01:51:02 PM PDT 24	Apr 18 01:51:04 PM PDT 24	358432809 ps
T1015	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3933974482	Apr 18 01:51:03 PM PDT 24	Apr 18 01:51:07 PM PDT 24	360572930 ps
T1016	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1775446183	Apr 18 01:51:23 PM PDT 24	Apr 18 01:51:25 PM PDT 24	21870223 ps
T1017	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4075291918	Apr 18 01:51:01 PM PDT 24	Apr 18 01:51:02 PM PDT 24	27101186 ps
T1018	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2162146016	Apr 18 01:51:23 PM PDT 24	Apr 18 01:51:28 PM PDT 24	1370773466 ps
T1019	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1828910266	Apr 18 01:51:26 PM PDT 24	Apr 18 01:51:31 PM PDT 24	740213395 ps
T1020	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2813960077	Apr 18 01:51:03 PM PDT 24	Apr 18 01:51:04 PM PDT 24	10721193 ps
T1021	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2240786057	Apr 18 01:50:56 PM PDT 24	Apr 18 01:50:58 PM PDT 24	13509596 ps
T1022	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2818888451	Apr 18 01:51:27 PM PDT 24	Apr 18 01:51:30 PM PDT 24	448432895 ps
T1023	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2046699994	Apr 18 01:51:19 PM PDT 24	Apr 18 01:51:24 PM PDT 24	348503883 ps
T1024	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3314495792	Apr 18 01:51:03 PM PDT 24	Apr 18 01:51:04 PM PDT 24	21540715 ps
T1025	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2314753837	Apr 18 01:51:04 PM PDT 24	Apr 18 01:51:08 PM PDT 24	985691562 ps
T118	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1054403372	Apr 18 01:51:25 PM PDT 24	Apr 18 01:51:29 PM PDT 24	359295950 ps
T1026	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.224908304	Apr 18 01:50:58 PM PDT 24	Apr 18 01:51:00 PM PDT 24	33494334 ps
T1027	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2396925203	Apr 18 01:51:14 PM PDT 24	Apr 18 01:51:16 PM PDT 24	33349086 ps
T1028	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3180696553	Apr 18 01:51:18 PM PDT 24	Apr 18 01:51:22 PM PDT 24	708649148 ps
T1029	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1407277173	Apr 18 01:51:08 PM PDT 24	Apr 18 01:51:13 PM PDT 24	131169712 ps
T1030	/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1162521828	Apr 18 01:51:23 PM PDT 24	Apr 18 01:51:51 PM PDT 24	7288375826 ps
T1031	/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2296338161	Apr 18 01:51:11 PM PDT 24	Apr 18 01:51:12 PM PDT 24	58516314 ps
T1032	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1924566693	Apr 18 01:51:10 PM PDT 24	Apr 18 01:51:13 PM PDT 24	27572727 ps

Test location	/workspace/coverage/default/48.sram_ctrl_lc_escalation.4028627339
Short name	T5
Test name
Test status
Simulation time	11114716932 ps
CPU time	76.27 seconds
Started	Apr 18 02:45:18 PM PDT 24
Finished	Apr 18 02:46:35 PM PDT 24
Peak memory	203096 kb
Host	smart-7bc6d49b-ec2c-485f-85b5-139e0f24ff6a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028627339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.4028627339
Directory	/workspace/48.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3938103564
Short name	T13
Test name
Test status
Simulation time	1380796434 ps
CPU time	42.01 seconds
Started	Apr 18 02:35:26 PM PDT 24
Finished	Apr 18 02:36:09 PM PDT 24
Peak memory	264480 kb
Host	smart-9dda99e9-9a25-4d56-b78f-b81598c13a0f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3938103564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3938103564
Directory	/workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all.3578744367
Short name	T7
Test name
Test status
Simulation time	126999890501 ps
CPU time	2621.18 seconds
Started	Apr 18 02:42:27 PM PDT 24
Finished	Apr 18 03:26:09 PM PDT 24
Peak memory	382124 kb
Host	smart-53580be1-7311-4d1b-9a36-1b2b1cff6abc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578744367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.3578744367
Directory	/workspace/41.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2642223567
Short name	T99
Test name
Test status
Simulation time	325740729 ps
CPU time	2.66 seconds
Started	Apr 18 01:51:08 PM PDT 24
Finished	Apr 18 01:51:12 PM PDT 24
Peak memory	202796 kb
Host	smart-df281385-8a59-43e7-9451-60f76fc6137d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642223567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.2642223567
Directory	/workspace/10.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/2.sram_ctrl_sec_cm.1873544145
Short name	T20
Test name
Test status
Simulation time	155512474 ps
CPU time	1.79 seconds
Started	Apr 18 02:30:52 PM PDT 24
Finished	Apr 18 02:30:55 PM PDT 24
Peak memory	222224 kb
Host	smart-d6e4fa5c-dfc4-4ec4-a4d6-2e3d08958859
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873544145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.1873544145
Directory	/workspace/2.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2474909215
Short name	T1
Test name
Test status
Simulation time	4559897608 ps
CPU time	144.68 seconds
Started	Apr 18 02:31:07 PM PDT 24
Finished	Apr 18 02:33:32 PM PDT 24
Peak memory	211396 kb
Host	smart-017c57c8-ee3a-4282-a228-8da499a94432
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474909215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.2474909215
Directory	/workspace/5.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_all.1438710192
Short name	T29
Test name
Test status
Simulation time	88711333696 ps
CPU time	6109.94 seconds
Started	Apr 18 02:39:07 PM PDT 24
Finished	Apr 18 04:20:58 PM PDT 24
Peak memory	382140 kb
Host	smart-df7adb2f-bc99-4afb-8620-eb0035f2618f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438710192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.1438710192
Directory	/workspace/32.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1941304314
Short name	T124
Test name
Test status
Simulation time	12174410342 ps
CPU time	282.41 seconds
Started	Apr 18 02:33:31 PM PDT 24
Finished	Apr 18 02:38:14 PM PDT 24
Peak memory	203140 kb
Host	smart-174c430a-23c6-4564-a1f5-105042cc9926
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941304314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.1941304314
Directory	/workspace/17.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3824785998
Short name	T61
Test name
Test status
Simulation time	16051796320 ps
CPU time	28.85 seconds
Started	Apr 18 01:51:09 PM PDT 24
Finished	Apr 18 01:51:39 PM PDT 24
Peak memory	202672 kb
Host	smart-eca03aa3-4364-4593-9ece-29e421682ea0
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824785998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3824785998
Directory	/workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1313024511
Short name	T9
Test name
Test status
Simulation time	59373849988 ps
CPU time	412.24 seconds
Started	Apr 18 02:31:56 PM PDT 24
Finished	Apr 18 02:38:48 PM PDT 24
Peak memory	203192 kb
Host	smart-329bb639-c9f6-4153-a8e2-5c87948ce3d8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313024511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.1313024511
Directory	/workspace/11.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/10.sram_ctrl_ram_cfg.875963455
Short name	T33
Test name
Test status
Simulation time	1343251282 ps
CPU time	3.72 seconds
Started	Apr 18 02:31:45 PM PDT 24
Finished	Apr 18 02:31:49 PM PDT 24
Peak memory	203072 kb
Host	smart-61148c9b-61a6-4370-9a07-f4f49275a1e2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875963455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.875963455
Directory	/workspace/10.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2914986624
Short name	T112
Test name
Test status
Simulation time	363834290 ps
CPU time	2.6 seconds
Started	Apr 18 01:51:28 PM PDT 24
Finished	Apr 18 01:51:32 PM PDT 24
Peak memory	202776 kb
Host	smart-b50e7534-3a5f-4162-a600-33bc2ea39948
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914986624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.2914986624
Directory	/workspace/18.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.973198837
Short name	T116
Test name
Test status
Simulation time	253153020 ps
CPU time	1.33 seconds
Started	Apr 18 01:51:10 PM PDT 24
Finished	Apr 18 01:51:13 PM PDT 24
Peak memory	202708 kb
Host	smart-27342a66-69bd-4b56-b487-d0ec0e7492ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973198837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.sram_ctrl_tl_intg_err.973198837
Directory	/workspace/9.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.sram_ctrl_alert_test.4110443778
Short name	T200
Test name
Test status
Simulation time	36634289 ps
CPU time	0.65 seconds
Started	Apr 18 02:30:38 PM PDT 24
Finished	Apr 18 02:30:40 PM PDT 24
Peak memory	202756 kb
Host	smart-cab6baa1-6ab6-4b8a-b313-8aa015795bc0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110443778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.4110443778
Directory	/workspace/0.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3065474461
Short name	T8
Test name
Test status
Simulation time	321822103 ps
CPU time	5.01 seconds
Started	Apr 18 02:32:23 PM PDT 24
Finished	Apr 18 02:32:29 PM PDT 24
Peak memory	211280 kb
Host	smart-8168e99c-85ed-4aa2-b682-da9a6898e432
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3065474461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3065474461
Directory	/workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.sram_ctrl_executable.1569776430
Short name	T122
Test name
Test status
Simulation time	7057334218 ps
CPU time	718.84 seconds
Started	Apr 18 02:43:46 PM PDT 24
Finished	Apr 18 02:55:45 PM PDT 24
Peak memory	374924 kb
Host	smart-69cf4bb5-2fc8-478f-b458-579996106635
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569776430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.1569776430
Directory	/workspace/44.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3926454906
Short name	T77
Test name
Test status
Simulation time	223751392202 ps
CPU time	1364.7 seconds
Started	Apr 18 02:30:34 PM PDT 24
Finished	Apr 18 02:53:19 PM PDT 24
Peak memory	380056 kb
Host	smart-27a59320-3512-41d2-b5b9-ff77e60e9f57
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926454906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.3926454906
Directory	/workspace/0.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2356050557
Short name	T72
Test name
Test status
Simulation time	14705347079 ps
CPU time	52.94 seconds
Started	Apr 18 01:51:12 PM PDT 24
Finished	Apr 18 01:52:06 PM PDT 24
Peak memory	202888 kb
Host	smart-919d8f16-9d0f-4b92-a6ea-6467e780aa24
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356050557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.2356050557
Directory	/workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1475593784
Short name	T56
Test name
Test status
Simulation time	31517400 ps
CPU time	0.73 seconds
Started	Apr 18 01:50:55 PM PDT 24
Finished	Apr 18 01:50:56 PM PDT 24
Peak memory	202512 kb
Host	smart-cd7261d6-0619-461b-9b4f-e232b3ef4ad5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475593784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.1475593784
Directory	/workspace/0.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2172671323
Short name	T947
Test name
Test status
Simulation time	508052927 ps
CPU time	2.44 seconds
Started	Apr 18 01:51:14 PM PDT 24
Finished	Apr 18 01:51:17 PM PDT 24
Peak memory	202596 kb
Host	smart-f94b1fd7-8c06-42e0-8dbe-ad15c8efc94d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172671323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.2172671323
Directory	/workspace/0.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.691118970
Short name	T998
Test name
Test status
Simulation time	40451417 ps
CPU time	0.64 seconds
Started	Apr 18 01:50:52 PM PDT 24
Finished	Apr 18 01:50:53 PM PDT 24
Peak memory	202480 kb
Host	smart-1406a91d-dcd6-4a53-9d61-c96c58c146f9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691118970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_reset.691118970
Directory	/workspace/0.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4232348455
Short name	T1012
Test name
Test status
Simulation time	6786768365 ps
CPU time	5.61 seconds
Started	Apr 18 01:50:56 PM PDT 24
Finished	Apr 18 01:51:03 PM PDT 24
Peak memory	210820 kb
Host	smart-1b446de9-f8fb-4f2f-8c97-96b3e9fca071
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232348455 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.4232348455
Directory	/workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2240786057
Short name	T1021
Test name
Test status
Simulation time	13509596 ps
CPU time	0.66 seconds
Started	Apr 18 01:50:56 PM PDT 24
Finished	Apr 18 01:50:58 PM PDT 24
Peak memory	202464 kb
Host	smart-85f95593-53ae-4a3b-8982-9879a5fbbdc1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240786057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.2240786057
Directory	/workspace/0.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3205777101
Short name	T1004
Test name
Test status
Simulation time	18197690 ps
CPU time	0.76 seconds
Started	Apr 18 01:51:25 PM PDT 24
Finished	Apr 18 01:51:27 PM PDT 24
Peak memory	202488 kb
Host	smart-b768979d-a113-42ed-b9f6-16007bff137a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205777101 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.3205777101
Directory	/workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1924566693
Short name	T1032
Test name
Test status
Simulation time	27572727 ps
CPU time	2.77 seconds
Started	Apr 18 01:51:10 PM PDT 24
Finished	Apr 18 01:51:13 PM PDT 24
Peak memory	202840 kb
Host	smart-a77e258b-71b1-4b9d-8c5b-aa5a7bf21475
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924566693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.1924566693
Directory	/workspace/0.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3402986797
Short name	T111
Test name
Test status
Simulation time	486905045 ps
CPU time	1.57 seconds
Started	Apr 18 01:50:58 PM PDT 24
Finished	Apr 18 01:51:01 PM PDT 24
Peak memory	202692 kb
Host	smart-a9533c47-26f6-46f3-98f8-84b478694803
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402986797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.3402986797
Directory	/workspace/0.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.224908304
Short name	T1026
Test name
Test status
Simulation time	33494334 ps
CPU time	0.71 seconds
Started	Apr 18 01:50:58 PM PDT 24
Finished	Apr 18 01:51:00 PM PDT 24
Peak memory	202428 kb
Host	smart-5a561314-45ac-4535-afa1-1cf8ad81885d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224908304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_aliasing.224908304
Directory	/workspace/1.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3348669198
Short name	T978
Test name
Test status
Simulation time	476796796 ps
CPU time	2.19 seconds
Started	Apr 18 01:50:56 PM PDT 24
Finished	Apr 18 01:51:00 PM PDT 24
Peak memory	202704 kb
Host	smart-d762d3ea-bd47-4686-9c14-26538654dcb7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348669198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.3348669198
Directory	/workspace/1.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2396925203
Short name	T1027
Test name
Test status
Simulation time	33349086 ps
CPU time	0.67 seconds
Started	Apr 18 01:51:14 PM PDT 24
Finished	Apr 18 01:51:16 PM PDT 24
Peak memory	202480 kb
Host	smart-f79c5341-77db-4463-8c8a-7d658d8c1303
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396925203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2396925203
Directory	/workspace/1.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.209755049
Short name	T1005
Test name
Test status
Simulation time	360168811 ps
CPU time	3.49 seconds
Started	Apr 18 01:51:14 PM PDT 24
Finished	Apr 18 01:51:19 PM PDT 24
Peak memory	210760 kb
Host	smart-cbb48a9f-1259-4a8a-9e5c-e6b51e00ab45
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209755049 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.209755049
Directory	/workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3495850907
Short name	T98
Test name
Test status
Simulation time	10646421 ps
CPU time	0.66 seconds
Started	Apr 18 01:51:11 PM PDT 24
Finished	Apr 18 01:51:13 PM PDT 24
Peak memory	202456 kb
Host	smart-f99badfb-63f4-499f-a002-7c7a26d69345
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495850907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.3495850907
Directory	/workspace/1.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1475853792
Short name	T999
Test name
Test status
Simulation time	9254702020 ps
CPU time	26.95 seconds
Started	Apr 18 01:51:03 PM PDT 24
Finished	Apr 18 01:51:30 PM PDT 24
Peak memory	202612 kb
Host	smart-683f5fa4-04e4-4a56-8694-b524b3317a36
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475853792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1475853792
Directory	/workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2160735699
Short name	T959
Test name
Test status
Simulation time	16051128 ps
CPU time	0.67 seconds
Started	Apr 18 01:50:54 PM PDT 24
Finished	Apr 18 01:50:55 PM PDT 24
Peak memory	202560 kb
Host	smart-7dc62bae-971a-4d75-ab58-b1af0d496803
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160735699 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.2160735699
Directory	/workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.377132683
Short name	T1010
Test name
Test status
Simulation time	43809184 ps
CPU time	3.76 seconds
Started	Apr 18 01:50:57 PM PDT 24
Finished	Apr 18 01:51:01 PM PDT 24
Peak memory	202824 kb
Host	smart-ef30ac27-f146-4915-99a1-d714527acbff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377132683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.377132683
Directory	/workspace/1.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4246026938
Short name	T120
Test name
Test status
Simulation time	170822000 ps
CPU time	2.23 seconds
Started	Apr 18 01:50:58 PM PDT 24
Finished	Apr 18 01:51:01 PM PDT 24
Peak memory	202744 kb
Host	smart-a1426b8c-b2db-4507-94ac-bec58e87f436
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246026938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.4246026938
Directory	/workspace/1.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.743673045
Short name	T962
Test name
Test status
Simulation time	719647842 ps
CPU time	3.57 seconds
Started	Apr 18 01:51:15 PM PDT 24
Finished	Apr 18 01:51:19 PM PDT 24
Peak memory	210788 kb
Host	smart-356e7c27-4b00-4613-8ffc-d0fbcb29be65
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743673045 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.743673045
Directory	/workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1168160475
Short name	T70
Test name
Test status
Simulation time	14380172 ps
CPU time	0.75 seconds
Started	Apr 18 01:51:19 PM PDT 24
Finished	Apr 18 01:51:21 PM PDT 24
Peak memory	202396 kb
Host	smart-ba5f7b24-defc-4db2-a124-e43c68afbd51
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168160475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.1168160475
Directory	/workspace/10.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3435614790
Short name	T984
Test name
Test status
Simulation time	7518183481 ps
CPU time	51.6 seconds
Started	Apr 18 01:51:10 PM PDT 24
Finished	Apr 18 01:52:03 PM PDT 24
Peak memory	202856 kb
Host	smart-0e2d79f3-8bdd-4d80-9634-4ea74d152211
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435614790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.3435614790
Directory	/workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3704517305
Short name	T967
Test name
Test status
Simulation time	24246643 ps
CPU time	0.79 seconds
Started	Apr 18 01:51:22 PM PDT 24
Finished	Apr 18 01:51:24 PM PDT 24
Peak memory	202524 kb
Host	smart-25c31c4e-8dac-47bf-86c8-953446698448
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704517305 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3704517305
Directory	/workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.287308885
Short name	T940
Test name
Test status
Simulation time	102402856 ps
CPU time	3.85 seconds
Started	Apr 18 01:51:25 PM PDT 24
Finished	Apr 18 01:51:30 PM PDT 24
Peak memory	202772 kb
Host	smart-2e39be22-565b-4378-8b07-87bbfa0eeff7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287308885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.287308885
Directory	/workspace/10.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3180696553
Short name	T1028
Test name
Test status
Simulation time	708649148 ps
CPU time	3.15 seconds
Started	Apr 18 01:51:18 PM PDT 24
Finished	Apr 18 01:51:22 PM PDT 24
Peak memory	202608 kb
Host	smart-ac6265da-81d7-4552-9be2-f457aa95a14f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180696553 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3180696553
Directory	/workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2739250690
Short name	T956
Test name
Test status
Simulation time	34225242 ps
CPU time	0.64 seconds
Started	Apr 18 01:51:22 PM PDT 24
Finished	Apr 18 01:51:23 PM PDT 24
Peak memory	202472 kb
Host	smart-084248dd-f6cb-4723-b8fd-ac152d98c20d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739250690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.2739250690
Directory	/workspace/11.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2929337470
Short name	T83
Test name
Test status
Simulation time	29306707384 ps
CPU time	50.19 seconds
Started	Apr 18 01:51:26 PM PDT 24
Finished	Apr 18 01:52:18 PM PDT 24
Peak memory	202860 kb
Host	smart-70e66517-9cb1-4ba9-b033-d6c7c1be8255
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929337470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.2929337470
Directory	/workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3387007841
Short name	T970
Test name
Test status
Simulation time	17130921 ps
CPU time	0.67 seconds
Started	Apr 18 01:52:06 PM PDT 24
Finished	Apr 18 01:52:07 PM PDT 24
Peak memory	202496 kb
Host	smart-68e898eb-7e79-4599-b021-e24c7f752f79
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387007841 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.3387007841
Directory	/workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2904256933
Short name	T975
Test name
Test status
Simulation time	574290266 ps
CPU time	4.46 seconds
Started	Apr 18 01:51:19 PM PDT 24
Finished	Apr 18 01:51:24 PM PDT 24
Peak memory	202788 kb
Host	smart-20b0aba9-f219-4a44-8967-4e9f92f266d6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904256933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.2904256933
Directory	/workspace/11.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2818888451
Short name	T1022
Test name
Test status
Simulation time	448432895 ps
CPU time	1.51 seconds
Started	Apr 18 01:51:27 PM PDT 24
Finished	Apr 18 01:51:30 PM PDT 24
Peak memory	202740 kb
Host	smart-dbe8af42-f895-4b80-9010-a5f1527683d2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818888451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.2818888451
Directory	/workspace/11.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3639202027
Short name	T996
Test name
Test status
Simulation time	349896556 ps
CPU time	3.77 seconds
Started	Apr 18 01:51:04 PM PDT 24
Finished	Apr 18 01:51:08 PM PDT 24
Peak memory	211008 kb
Host	smart-8ff1911a-c15e-4c75-8941-97ffebcbd9ed
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639202027 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3639202027
Directory	/workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3391237811
Short name	T995
Test name
Test status
Simulation time	13341771 ps
CPU time	0.67 seconds
Started	Apr 18 01:51:08 PM PDT 24
Finished	Apr 18 01:51:09 PM PDT 24
Peak memory	202460 kb
Host	smart-eddfac24-7d2e-437f-bba3-c39db5af89aa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391237811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.3391237811
Directory	/workspace/12.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2782934593
Short name	T86
Test name
Test status
Simulation time	3880278696 ps
CPU time	25.58 seconds
Started	Apr 18 01:51:09 PM PDT 24
Finished	Apr 18 01:51:35 PM PDT 24
Peak memory	202688 kb
Host	smart-2cc2dfc1-d9e1-461c-8b70-4b9f8102f95f
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782934593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2782934593
Directory	/workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.862315648
Short name	T980
Test name
Test status
Simulation time	25245486 ps
CPU time	0.73 seconds
Started	Apr 18 01:51:07 PM PDT 24
Finished	Apr 18 01:51:09 PM PDT 24
Peak memory	202568 kb
Host	smart-f98f03b2-bc73-4a8c-a886-10fa0bb41f1a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862315648 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.862315648
Directory	/workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1998700559
Short name	T969
Test name
Test status
Simulation time	123984372 ps
CPU time	4.17 seconds
Started	Apr 18 01:51:15 PM PDT 24
Finished	Apr 18 01:51:20 PM PDT 24
Peak memory	202824 kb
Host	smart-78450cbf-8890-4cdd-8922-aeaed347b476
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998700559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.1998700559
Directory	/workspace/12.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1647864594
Short name	T109
Test name
Test status
Simulation time	169286188 ps
CPU time	2.28 seconds
Started	Apr 18 01:51:09 PM PDT 24
Finished	Apr 18 01:51:11 PM PDT 24
Peak memory	202772 kb
Host	smart-b8ba5b12-8cf1-4b04-b2f0-011689fcc862
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647864594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.1647864594
Directory	/workspace/12.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1938319149
Short name	T982
Test name
Test status
Simulation time	476815794 ps
CPU time	4.11 seconds
Started	Apr 18 01:51:09 PM PDT 24
Finished	Apr 18 01:51:13 PM PDT 24
Peak memory	210940 kb
Host	smart-eacd81f0-d499-43f7-972b-2150d4855b43
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938319149 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1938319149
Directory	/workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2659714811
Short name	T68
Test name
Test status
Simulation time	93317309 ps
CPU time	0.66 seconds
Started	Apr 18 01:51:22 PM PDT 24
Finished	Apr 18 01:51:23 PM PDT 24
Peak memory	202332 kb
Host	smart-704b214a-6c4e-41db-947b-cf1c6ae7503e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659714811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.2659714811
Directory	/workspace/13.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1523586304
Short name	T81
Test name
Test status
Simulation time	14745863213 ps
CPU time	26.9 seconds
Started	Apr 18 01:51:06 PM PDT 24
Finished	Apr 18 01:51:34 PM PDT 24
Peak memory	202648 kb
Host	smart-82135895-209c-45a4-b596-5f617e12b09d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523586304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.1523586304
Directory	/workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2296338161
Short name	T1031
Test name
Test status
Simulation time	58516314 ps
CPU time	0.7 seconds
Started	Apr 18 01:51:11 PM PDT 24
Finished	Apr 18 01:51:12 PM PDT 24
Peak memory	202508 kb
Host	smart-613f4e24-e1c4-4fc2-ab87-202d603c2953
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296338161 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2296338161
Directory	/workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1863886295
Short name	T997
Test name
Test status
Simulation time	44507519 ps
CPU time	2.31 seconds
Started	Apr 18 01:51:11 PM PDT 24
Finished	Apr 18 01:51:14 PM PDT 24
Peak memory	202756 kb
Host	smart-9c1d4e30-a911-4eb5-b070-32d2dddbb454
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863886295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.1863886295
Directory	/workspace/13.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1054403372
Short name	T118
Test name
Test status
Simulation time	359295950 ps
CPU time	2.49 seconds
Started	Apr 18 01:51:25 PM PDT 24
Finished	Apr 18 01:51:29 PM PDT 24
Peak memory	202716 kb
Host	smart-2d88608b-3613-428e-8f3b-a98638a640ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054403372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.1054403372
Directory	/workspace/13.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.931556471
Short name	T957
Test name
Test status
Simulation time	1460240059 ps
CPU time	4.3 seconds
Started	Apr 18 01:51:08 PM PDT 24
Finished	Apr 18 01:51:13 PM PDT 24
Peak memory	211028 kb
Host	smart-7ddc3255-f001-4ac8-955b-a5973b7c609b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931556471 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.931556471
Directory	/workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4222473904
Short name	T951
Test name
Test status
Simulation time	28949518 ps
CPU time	0.63 seconds
Started	Apr 18 01:51:07 PM PDT 24
Finished	Apr 18 01:51:09 PM PDT 24
Peak memory	202476 kb
Host	smart-9769797d-37ff-486d-9ee7-b0d15e89916b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222473904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.4222473904
Directory	/workspace/14.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.884560199
Short name	T65
Test name
Test status
Simulation time	7152791787 ps
CPU time	49.89 seconds
Started	Apr 18 01:51:21 PM PDT 24
Finished	Apr 18 01:52:11 PM PDT 24
Peak memory	202844 kb
Host	smart-47e4d5a3-a1cb-4f56-bbb2-4e57fd306886
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884560199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.884560199
Directory	/workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.839392645
Short name	T60
Test name
Test status
Simulation time	36251519 ps
CPU time	0.69 seconds
Started	Apr 18 01:51:22 PM PDT 24
Finished	Apr 18 01:51:23 PM PDT 24
Peak memory	202352 kb
Host	smart-63689e3d-dcea-47d9-8044-1cde042ae705
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839392645 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.839392645
Directory	/workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2494294431
Short name	T939
Test name
Test status
Simulation time	457160711 ps
CPU time	3.79 seconds
Started	Apr 18 01:51:07 PM PDT 24
Finished	Apr 18 01:51:11 PM PDT 24
Peak memory	202752 kb
Host	smart-82bc88ba-70c6-45fd-aad1-f98273284a08
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494294431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.2494294431
Directory	/workspace/14.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2473071009
Short name	T119
Test name
Test status
Simulation time	130753283 ps
CPU time	1.6 seconds
Started	Apr 18 01:51:08 PM PDT 24
Finished	Apr 18 01:51:11 PM PDT 24
Peak memory	202784 kb
Host	smart-2688b5d7-68c5-4271-bd50-db1eb425fe45
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473071009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.2473071009
Directory	/workspace/14.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3497474644
Short name	T977
Test name
Test status
Simulation time	2307974903 ps
CPU time	3.66 seconds
Started	Apr 18 01:51:25 PM PDT 24
Finished	Apr 18 01:51:30 PM PDT 24
Peak memory	210844 kb
Host	smart-2b63e9c1-fc64-4cb2-8bba-7709270c45a9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497474644 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.3497474644
Directory	/workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2419831128
Short name	T986
Test name
Test status
Simulation time	14107832 ps
CPU time	0.65 seconds
Started	Apr 18 01:51:17 PM PDT 24
Finished	Apr 18 01:51:18 PM PDT 24
Peak memory	202424 kb
Host	smart-26bc5d07-a6fd-49f9-8aad-d39b1ecf0724
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419831128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.2419831128
Directory	/workspace/15.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.424492843
Short name	T1008
Test name
Test status
Simulation time	7397193211 ps
CPU time	51.41 seconds
Started	Apr 18 01:51:28 PM PDT 24
Finished	Apr 18 01:52:25 PM PDT 24
Peak memory	202844 kb
Host	smart-47f3f869-e675-4f01-91e0-8d80a190c907
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424492843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.424492843
Directory	/workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1204719234
Short name	T993
Test name
Test status
Simulation time	23673760 ps
CPU time	0.67 seconds
Started	Apr 18 01:51:20 PM PDT 24
Finished	Apr 18 01:51:21 PM PDT 24
Peak memory	202376 kb
Host	smart-f1e55889-3b3f-42ec-b8ce-a5dba93c2888
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204719234 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1204719234
Directory	/workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3661954804
Short name	T950
Test name
Test status
Simulation time	332835055 ps
CPU time	2.66 seconds
Started	Apr 18 01:51:12 PM PDT 24
Finished	Apr 18 01:51:15 PM PDT 24
Peak memory	202844 kb
Host	smart-421e96fa-3c00-4867-a2a4-a16aee24cce3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661954804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.3661954804
Directory	/workspace/15.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2889635887
Short name	T117
Test name
Test status
Simulation time	124596285 ps
CPU time	1.67 seconds
Started	Apr 18 01:51:19 PM PDT 24
Finished	Apr 18 01:51:21 PM PDT 24
Peak memory	202980 kb
Host	smart-1718f485-686d-474d-91bb-3cc22c1a2630
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889635887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.2889635887
Directory	/workspace/15.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4196605207
Short name	T1002
Test name
Test status
Simulation time	712194019 ps
CPU time	3.52 seconds
Started	Apr 18 01:51:10 PM PDT 24
Finished	Apr 18 01:51:14 PM PDT 24
Peak memory	211060 kb
Host	smart-f3818596-a300-44f7-94a8-20bcc28276bf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196605207 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.4196605207
Directory	/workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2318086747
Short name	T968
Test name
Test status
Simulation time	28136313 ps
CPU time	0.68 seconds
Started	Apr 18 01:51:17 PM PDT 24
Finished	Apr 18 01:51:19 PM PDT 24
Peak memory	202448 kb
Host	smart-65490a01-c25d-4b57-bd70-84cbf646fa14
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318086747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.2318086747
Directory	/workspace/16.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1364146668
Short name	T85
Test name
Test status
Simulation time	29365656406 ps
CPU time	50.49 seconds
Started	Apr 18 01:51:23 PM PDT 24
Finished	Apr 18 01:52:14 PM PDT 24
Peak memory	202764 kb
Host	smart-a5c5885d-0b0a-4227-974d-80be465f7be4
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364146668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1364146668
Directory	/workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1979536026
Short name	T90
Test name
Test status
Simulation time	27011872 ps
CPU time	0.69 seconds
Started	Apr 18 01:51:29 PM PDT 24
Finished	Apr 18 01:51:30 PM PDT 24
Peak memory	202432 kb
Host	smart-20c701a7-d856-4866-8218-d4bfc9a8f942
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979536026 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.1979536026
Directory	/workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1407277173
Short name	T1029
Test name
Test status
Simulation time	131169712 ps
CPU time	3.74 seconds
Started	Apr 18 01:51:08 PM PDT 24
Finished	Apr 18 01:51:13 PM PDT 24
Peak memory	211048 kb
Host	smart-f82a21fb-b3a7-4af9-9078-5702e5e72a33
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407277173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.1407277173
Directory	/workspace/16.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2129076614
Short name	T113
Test name
Test status
Simulation time	140422996 ps
CPU time	1.45 seconds
Started	Apr 18 01:51:20 PM PDT 24
Finished	Apr 18 01:51:22 PM PDT 24
Peak memory	202724 kb
Host	smart-61a19b7a-8c62-4e58-b977-6004169d2a00
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129076614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.2129076614
Directory	/workspace/16.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.677081466
Short name	T988
Test name
Test status
Simulation time	1446537653 ps
CPU time	5 seconds
Started	Apr 18 01:51:14 PM PDT 24
Finished	Apr 18 01:51:19 PM PDT 24
Peak memory	210972 kb
Host	smart-4ea5b08d-5c9f-4fe9-88c3-523c593f6e87
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677081466 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.677081466
Directory	/workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1900422207
Short name	T942
Test name
Test status
Simulation time	12735149 ps
CPU time	0.68 seconds
Started	Apr 18 01:51:09 PM PDT 24
Finished	Apr 18 01:51:11 PM PDT 24
Peak memory	202452 kb
Host	smart-d7e4ae96-cc61-4f12-9ae3-3f8682d2d6f4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900422207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.1900422207
Directory	/workspace/17.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2491867465
Short name	T989
Test name
Test status
Simulation time	14781724374 ps
CPU time	28.5 seconds
Started	Apr 18 01:51:21 PM PDT 24
Finished	Apr 18 01:51:50 PM PDT 24
Peak memory	202672 kb
Host	smart-392fa3fb-21b5-4496-9854-86421da544b2
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491867465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.2491867465
Directory	/workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1698128099
Short name	T949
Test name
Test status
Simulation time	37771794 ps
CPU time	0.8 seconds
Started	Apr 18 01:51:22 PM PDT 24
Finished	Apr 18 01:51:23 PM PDT 24
Peak memory	202512 kb
Host	smart-1a293b25-e8d1-449e-b407-c2ea07978af4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698128099 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1698128099
Directory	/workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.129030471
Short name	T987
Test name
Test status
Simulation time	134677022 ps
CPU time	4.95 seconds
Started	Apr 18 01:51:08 PM PDT 24
Finished	Apr 18 01:51:13 PM PDT 24
Peak memory	211064 kb
Host	smart-8c9e0cbf-f469-4a8c-bc8a-f8cfc54e1f4c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129030471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.129030471
Directory	/workspace/17.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1709291419
Short name	T115
Test name
Test status
Simulation time	630348091 ps
CPU time	2.61 seconds
Started	Apr 18 01:51:19 PM PDT 24
Finished	Apr 18 01:51:22 PM PDT 24
Peak memory	202712 kb
Host	smart-0a578cdc-b7b8-4253-8f95-bd4203742d06
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709291419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.1709291419
Directory	/workspace/17.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2170440899
Short name	T964
Test name
Test status
Simulation time	382271300 ps
CPU time	3.75 seconds
Started	Apr 18 01:51:10 PM PDT 24
Finished	Apr 18 01:51:15 PM PDT 24
Peak memory	211004 kb
Host	smart-3ecfc09e-7976-453b-9d82-453185aa86cc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170440899 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2170440899
Directory	/workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2306416721
Short name	T994
Test name
Test status
Simulation time	31687160 ps
CPU time	0.66 seconds
Started	Apr 18 01:51:24 PM PDT 24
Finished	Apr 18 01:51:25 PM PDT 24
Peak memory	202472 kb
Host	smart-cd13e0b9-0c84-4d57-8f69-737fa757bb08
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306416721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.2306416721
Directory	/workspace/18.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3249344808
Short name	T1003
Test name
Test status
Simulation time	4087949829 ps
CPU time	25.16 seconds
Started	Apr 18 01:51:09 PM PDT 24
Finished	Apr 18 01:51:35 PM PDT 24
Peak memory	202628 kb
Host	smart-2e2072ce-290f-47ce-b63e-466d217ca920
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249344808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3249344808
Directory	/workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1960977274
Short name	T57
Test name
Test status
Simulation time	88932057 ps
CPU time	0.78 seconds
Started	Apr 18 01:51:12 PM PDT 24
Finished	Apr 18 01:51:13 PM PDT 24
Peak memory	202580 kb
Host	smart-ca5a2a8a-2220-4052-8106-835d40958ca3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960977274 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1960977274
Directory	/workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3313904199
Short name	T952
Test name
Test status
Simulation time	567102553 ps
CPU time	5.19 seconds
Started	Apr 18 01:51:14 PM PDT 24
Finished	Apr 18 01:51:19 PM PDT 24
Peak memory	202796 kb
Host	smart-49aab21e-7120-4768-accb-83ba2427a24e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313904199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.3313904199
Directory	/workspace/18.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3250266093
Short name	T963
Test name
Test status
Simulation time	707084730 ps
CPU time	3.57 seconds
Started	Apr 18 01:51:12 PM PDT 24
Finished	Apr 18 01:51:16 PM PDT 24
Peak memory	211792 kb
Host	smart-36169d2f-d7d4-4745-9716-6d751378b930
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250266093 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3250266093
Directory	/workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1775446183
Short name	T1016
Test name
Test status
Simulation time	21870223 ps
CPU time	0.69 seconds
Started	Apr 18 01:51:23 PM PDT 24
Finished	Apr 18 01:51:25 PM PDT 24
Peak memory	202480 kb
Host	smart-65682b5a-c38b-4fbc-9255-194f1f2c9c33
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775446183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.1775446183
Directory	/workspace/19.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2743563359
Short name	T84
Test name
Test status
Simulation time	4562598328 ps
CPU time	26.33 seconds
Started	Apr 18 01:51:17 PM PDT 24
Finished	Apr 18 01:51:44 PM PDT 24
Peak memory	202656 kb
Host	smart-76377bec-a5de-4a0b-93a4-24c06d4ca2aa
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743563359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2743563359
Directory	/workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1096050825
Short name	T973
Test name
Test status
Simulation time	52482817 ps
CPU time	0.76 seconds
Started	Apr 18 01:51:10 PM PDT 24
Finished	Apr 18 01:51:12 PM PDT 24
Peak memory	202556 kb
Host	smart-b4210b17-95f8-457d-967b-84f3aed936e3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096050825 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1096050825
Directory	/workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2233504987
Short name	T981
Test name
Test status
Simulation time	69684164 ps
CPU time	2.48 seconds
Started	Apr 18 01:51:21 PM PDT 24
Finished	Apr 18 01:51:24 PM PDT 24
Peak memory	202856 kb
Host	smart-6f551cbd-08ed-44a3-8519-b24159dab7f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233504987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.2233504987
Directory	/workspace/19.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2080723888
Short name	T101
Test name
Test status
Simulation time	2203945217 ps
CPU time	2.45 seconds
Started	Apr 18 01:51:11 PM PDT 24
Finished	Apr 18 01:51:14 PM PDT 24
Peak memory	202812 kb
Host	smart-f6a86efa-7570-41c8-bfb2-f73dc9578dfa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080723888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.2080723888
Directory	/workspace/19.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1436105608
Short name	T979
Test name
Test status
Simulation time	20487981 ps
CPU time	0.81 seconds
Started	Apr 18 01:50:58 PM PDT 24
Finished	Apr 18 01:50:59 PM PDT 24
Peak memory	202492 kb
Host	smart-1109ec13-b0ab-4e78-b531-813dd8a45727
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436105608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.1436105608
Directory	/workspace/2.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2915745555
Short name	T82
Test name
Test status
Simulation time	645393366 ps
CPU time	2.38 seconds
Started	Apr 18 01:51:10 PM PDT 24
Finished	Apr 18 01:51:12 PM PDT 24
Peak memory	202556 kb
Host	smart-8e631934-7bb1-44d6-b128-877e076bfc14
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915745555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.2915745555
Directory	/workspace/2.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1579216738
Short name	T954
Test name
Test status
Simulation time	15225325 ps
CPU time	0.69 seconds
Started	Apr 18 01:50:55 PM PDT 24
Finished	Apr 18 01:50:56 PM PDT 24
Peak memory	202500 kb
Host	smart-6d0b46fe-3d90-47d6-87bb-370000add094
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579216738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.1579216738
Directory	/workspace/2.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3475236970
Short name	T958
Test name
Test status
Simulation time	397512524 ps
CPU time	3.46 seconds
Started	Apr 18 01:51:13 PM PDT 24
Finished	Apr 18 01:51:17 PM PDT 24
Peak memory	210804 kb
Host	smart-a1c66c19-a192-4c9e-8116-a3a94b9878dd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475236970 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.3475236970
Directory	/workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.384194617
Short name	T1006
Test name
Test status
Simulation time	16575906 ps
CPU time	0.66 seconds
Started	Apr 18 01:50:56 PM PDT 24
Finished	Apr 18 01:50:58 PM PDT 24
Peak memory	202456 kb
Host	smart-0cec09c6-8c2f-42a6-be88-e5b1a19c168a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384194617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_csr_rw.384194617
Directory	/workspace/2.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3794355404
Short name	T944
Test name
Test status
Simulation time	8027875260 ps
CPU time	30.41 seconds
Started	Apr 18 01:50:53 PM PDT 24
Finished	Apr 18 01:51:24 PM PDT 24
Peak memory	202676 kb
Host	smart-1ef04a41-bd79-4e81-a26d-96e814b079e5
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794355404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3794355404
Directory	/workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1848341517
Short name	T1013
Test name
Test status
Simulation time	16831634 ps
CPU time	0.75 seconds
Started	Apr 18 01:51:18 PM PDT 24
Finished	Apr 18 01:51:20 PM PDT 24
Peak memory	202528 kb
Host	smart-0b90674e-4773-42e7-ba90-b4c418f1a7d6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848341517 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1848341517
Directory	/workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2314753837
Short name	T1025
Test name
Test status
Simulation time	985691562 ps
CPU time	4.29 seconds
Started	Apr 18 01:51:04 PM PDT 24
Finished	Apr 18 01:51:08 PM PDT 24
Peak memory	202824 kb
Host	smart-5f52a818-104c-4dc7-8724-2cb8a6065c8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314753837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.2314753837
Directory	/workspace/2.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2198917120
Short name	T114
Test name
Test status
Simulation time	299186380 ps
CPU time	1.68 seconds
Started	Apr 18 01:50:56 PM PDT 24
Finished	Apr 18 01:50:58 PM PDT 24
Peak memory	202744 kb
Host	smart-ab60081e-d96b-4531-85dc-53981d559c30
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198917120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.2198917120
Directory	/workspace/2.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1111639375
Short name	T1007
Test name
Test status
Simulation time	22121660 ps
CPU time	0.79 seconds
Started	Apr 18 01:51:19 PM PDT 24
Finished	Apr 18 01:51:20 PM PDT 24
Peak memory	202420 kb
Host	smart-b75c881e-720e-4818-a723-d0851012d239
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111639375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.1111639375
Directory	/workspace/3.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3565731304
Short name	T974
Test name
Test status
Simulation time	265615079 ps
CPU time	1.53 seconds
Started	Apr 18 01:50:59 PM PDT 24
Finished	Apr 18 01:51:01 PM PDT 24
Peak memory	202684 kb
Host	smart-b8a6919c-ec1f-407c-b83e-92ecaa753cd4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565731304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.3565731304
Directory	/workspace/3.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.68351616
Short name	T943
Test name
Test status
Simulation time	44817521 ps
CPU time	0.65 seconds
Started	Apr 18 01:51:12 PM PDT 24
Finished	Apr 18 01:51:14 PM PDT 24
Peak memory	201976 kb
Host	smart-94d73a85-7a34-4624-9710-0b36a9a708e2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68351616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_reset.68351616
Directory	/workspace/3.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3800598409
Short name	T976
Test name
Test status
Simulation time	2334568989 ps
CPU time	3.8 seconds
Started	Apr 18 01:51:02 PM PDT 24
Finished	Apr 18 01:51:06 PM PDT 24
Peak memory	210876 kb
Host	smart-b70d6872-c324-4589-93c2-64affd9ec3d4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800598409 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3800598409
Directory	/workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1796629538
Short name	T71
Test name
Test status
Simulation time	18568167 ps
CPU time	0.65 seconds
Started	Apr 18 01:50:58 PM PDT 24
Finished	Apr 18 01:51:00 PM PDT 24
Peak memory	202468 kb
Host	smart-d384c6d4-a2d4-48e2-9e34-4fee839ca0e2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796629538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.1796629538
Directory	/workspace/3.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1162521828
Short name	T1030
Test name
Test status
Simulation time	7288375826 ps
CPU time	26.9 seconds
Started	Apr 18 01:51:23 PM PDT 24
Finished	Apr 18 01:51:51 PM PDT 24
Peak memory	202656 kb
Host	smart-394f46e2-6e0b-4dd0-80b2-a08624f4d06d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162521828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1162521828
Directory	/workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2300497207
Short name	T91
Test name
Test status
Simulation time	15345107 ps
CPU time	0.7 seconds
Started	Apr 18 01:51:01 PM PDT 24
Finished	Apr 18 01:51:02 PM PDT 24
Peak memory	202516 kb
Host	smart-d3b7a4fb-c030-40b4-964b-7ac9065b50bd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300497207 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.2300497207
Directory	/workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3845260556
Short name	T961
Test name
Test status
Simulation time	218750249 ps
CPU time	1.88 seconds
Started	Apr 18 01:50:59 PM PDT 24
Finished	Apr 18 01:51:02 PM PDT 24
Peak memory	202852 kb
Host	smart-16e406b0-4fcc-43a1-b91d-779caa097061
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845260556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.3845260556
Directory	/workspace/3.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.912190083
Short name	T972
Test name
Test status
Simulation time	304886398 ps
CPU time	1.51 seconds
Started	Apr 18 01:50:59 PM PDT 24
Finished	Apr 18 01:51:01 PM PDT 24
Peak memory	202708 kb
Host	smart-cd3f6cb0-8ac6-4103-ac7c-ea095306dcb5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912190083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.sram_ctrl_tl_intg_err.912190083
Directory	/workspace/3.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2494099426
Short name	T966
Test name
Test status
Simulation time	138877450 ps
CPU time	0.72 seconds
Started	Apr 18 01:50:59 PM PDT 24
Finished	Apr 18 01:51:00 PM PDT 24
Peak memory	202500 kb
Host	smart-8ed45a25-6a39-4c4d-ba03-1d150ed40f30
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494099426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.2494099426
Directory	/workspace/4.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3977122029
Short name	T990
Test name
Test status
Simulation time	322375401 ps
CPU time	2.34 seconds
Started	Apr 18 01:51:18 PM PDT 24
Finished	Apr 18 01:51:21 PM PDT 24
Peak memory	202636 kb
Host	smart-ed0c4716-a7db-41c5-9332-555ae5a2253f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977122029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.3977122029
Directory	/workspace/4.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1399838297
Short name	T1011
Test name
Test status
Simulation time	122498423 ps
CPU time	0.66 seconds
Started	Apr 18 01:51:20 PM PDT 24
Finished	Apr 18 01:51:22 PM PDT 24
Peak memory	202632 kb
Host	smart-aa4c9c3a-50f6-41a6-ad6e-bfd2f37f2331
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399838297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.1399838297
Directory	/workspace/4.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3933974482
Short name	T1015
Test name
Test status
Simulation time	360572930 ps
CPU time	4.15 seconds
Started	Apr 18 01:51:03 PM PDT 24
Finished	Apr 18 01:51:07 PM PDT 24
Peak memory	211976 kb
Host	smart-2a450b82-82a1-4cab-8547-0f6f5b1ce8c1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933974482 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3933974482
Directory	/workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2813960077
Short name	T1020
Test name
Test status
Simulation time	10721193 ps
CPU time	0.64 seconds
Started	Apr 18 01:51:03 PM PDT 24
Finished	Apr 18 01:51:04 PM PDT 24
Peak memory	202096 kb
Host	smart-971fc3ea-3040-45df-ac34-d50731973c48
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813960077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.2813960077
Directory	/workspace/4.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3561097979
Short name	T992
Test name
Test status
Simulation time	53318510 ps
CPU time	0.73 seconds
Started	Apr 18 01:51:17 PM PDT 24
Finished	Apr 18 01:51:18 PM PDT 24
Peak memory	202312 kb
Host	smart-097ba612-a47e-441b-995c-3116919a3fff
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561097979 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3561097979
Directory	/workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1999687439
Short name	T941
Test name
Test status
Simulation time	41212155 ps
CPU time	3.87 seconds
Started	Apr 18 01:51:21 PM PDT 24
Finished	Apr 18 01:51:26 PM PDT 24
Peak memory	202756 kb
Host	smart-b0dc593e-8bd3-44c2-abc7-373a96949ef1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999687439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.1999687439
Directory	/workspace/4.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3130658299
Short name	T985
Test name
Test status
Simulation time	495347443 ps
CPU time	1.58 seconds
Started	Apr 18 01:50:59 PM PDT 24
Finished	Apr 18 01:51:01 PM PDT 24
Peak memory	202792 kb
Host	smart-c921a022-b9e3-4cba-a584-042faa82941a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130658299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.3130658299
Directory	/workspace/4.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2046699994
Short name	T1023
Test name
Test status
Simulation time	348503883 ps
CPU time	3.44 seconds
Started	Apr 18 01:51:19 PM PDT 24
Finished	Apr 18 01:51:24 PM PDT 24
Peak memory	211012 kb
Host	smart-f1d665fb-6a65-4f23-b525-0db32de8de46
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046699994 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2046699994
Directory	/workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3314495792
Short name	T1024
Test name
Test status
Simulation time	21540715 ps
CPU time	0.68 seconds
Started	Apr 18 01:51:03 PM PDT 24
Finished	Apr 18 01:51:04 PM PDT 24
Peak memory	202496 kb
Host	smart-cdc56647-49c5-4157-ad3e-f3393878a424
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314495792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.3314495792
Directory	/workspace/5.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3766443864
Short name	T991
Test name
Test status
Simulation time	88064164655 ps
CPU time	57.4 seconds
Started	Apr 18 01:51:22 PM PDT 24
Finished	Apr 18 01:52:20 PM PDT 24
Peak memory	202800 kb
Host	smart-2902c4ce-9ad0-4416-a1b2-24c2df7583d7
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766443864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3766443864
Directory	/workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1298043743
Short name	T948
Test name
Test status
Simulation time	37760397 ps
CPU time	0.79 seconds
Started	Apr 18 01:51:13 PM PDT 24
Finished	Apr 18 01:51:14 PM PDT 24
Peak memory	202516 kb
Host	smart-318de0c5-af8b-4fca-91a4-8974148e919b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298043743 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1298043743
Directory	/workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1807642511
Short name	T945
Test name
Test status
Simulation time	91379283 ps
CPU time	2.99 seconds
Started	Apr 18 01:51:08 PM PDT 24
Finished	Apr 18 01:51:11 PM PDT 24
Peak memory	210980 kb
Host	smart-51860fb3-9d32-49b2-af5e-5952d112d30d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807642511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.1807642511
Directory	/workspace/5.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3489332129
Short name	T1014
Test name
Test status
Simulation time	358432809 ps
CPU time	1.57 seconds
Started	Apr 18 01:51:02 PM PDT 24
Finished	Apr 18 01:51:04 PM PDT 24
Peak memory	202736 kb
Host	smart-a1787ee4-bdc2-4031-b094-a608a29192cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489332129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.3489332129
Directory	/workspace/5.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2162146016
Short name	T1018
Test name
Test status
Simulation time	1370773466 ps
CPU time	3.71 seconds
Started	Apr 18 01:51:23 PM PDT 24
Finished	Apr 18 01:51:28 PM PDT 24
Peak memory	210752 kb
Host	smart-89f3d374-038a-4637-b524-b8d76ffe3e38
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162146016 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2162146016
Directory	/workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4075291918
Short name	T1017
Test name
Test status
Simulation time	27101186 ps
CPU time	0.69 seconds
Started	Apr 18 01:51:01 PM PDT 24
Finished	Apr 18 01:51:02 PM PDT 24
Peak memory	202468 kb
Host	smart-c05b1d23-8ad0-4278-b732-f0054e5a4345
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075291918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.4075291918
Directory	/workspace/6.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3938694405
Short name	T971
Test name
Test status
Simulation time	7427817466 ps
CPU time	26.72 seconds
Started	Apr 18 01:51:20 PM PDT 24
Finished	Apr 18 01:51:47 PM PDT 24
Peak memory	202660 kb
Host	smart-1bd6a614-ddad-4841-a358-d2baa42d2e4b
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938694405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3938694405
Directory	/workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.905703315
Short name	T63
Test name
Test status
Simulation time	29710688 ps
CPU time	0.8 seconds
Started	Apr 18 01:51:03 PM PDT 24
Finished	Apr 18 01:51:04 PM PDT 24
Peak memory	202532 kb
Host	smart-d61346c5-6593-4dd9-b609-76d6a3b710e1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905703315 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.905703315
Directory	/workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.894316814
Short name	T1009
Test name
Test status
Simulation time	1244438211 ps
CPU time	3.84 seconds
Started	Apr 18 01:51:02 PM PDT 24
Finished	Apr 18 01:51:06 PM PDT 24
Peak memory	202844 kb
Host	smart-63170b0d-57e0-4f9f-aa6c-527a5c74708c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894316814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.894316814
Directory	/workspace/6.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2912092871
Short name	T110
Test name
Test status
Simulation time	623062284 ps
CPU time	2.47 seconds
Started	Apr 18 01:51:20 PM PDT 24
Finished	Apr 18 01:51:23 PM PDT 24
Peak memory	202736 kb
Host	smart-4eff91ad-32aa-4496-aa18-2dce4be08fe4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912092871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.2912092871
Directory	/workspace/6.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3992857223
Short name	T965
Test name
Test status
Simulation time	1431249120 ps
CPU time	4.21 seconds
Started	Apr 18 01:51:35 PM PDT 24
Finished	Apr 18 01:51:40 PM PDT 24
Peak memory	210944 kb
Host	smart-b7d13062-31d4-4d71-b970-76123305a1bd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992857223 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3992857223
Directory	/workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1723748514
Short name	T946
Test name
Test status
Simulation time	18703529 ps
CPU time	0.65 seconds
Started	Apr 18 01:51:35 PM PDT 24
Finished	Apr 18 01:51:36 PM PDT 24
Peak memory	202500 kb
Host	smart-17edba1f-c8b7-4a88-ad4c-8f0a262b5cc4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723748514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.1723748514
Directory	/workspace/7.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.29096943
Short name	T69
Test name
Test status
Simulation time	14212210368 ps
CPU time	30.86 seconds
Started	Apr 18 01:51:03 PM PDT 24
Finished	Apr 18 01:51:34 PM PDT 24
Peak memory	202644 kb
Host	smart-c8579fb6-5013-4843-8ab9-7a7cea7dfd20
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29096943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base _test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.29096943
Directory	/workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3513739082
Short name	T62
Test name
Test status
Simulation time	70033980 ps
CPU time	0.74 seconds
Started	Apr 18 01:51:07 PM PDT 24
Finished	Apr 18 01:51:08 PM PDT 24
Peak memory	202532 kb
Host	smart-68028253-d5fe-43a1-8555-4d0cac069e44
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513739082 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3513739082
Directory	/workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1411450921
Short name	T960
Test name
Test status
Simulation time	179320928 ps
CPU time	2.96 seconds
Started	Apr 18 01:51:26 PM PDT 24
Finished	Apr 18 01:51:30 PM PDT 24
Peak memory	202776 kb
Host	smart-62b9eca0-e2f6-48bc-80c5-64b8bab7b6e1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411450921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.1411450921
Directory	/workspace/7.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2338243128
Short name	T1001
Test name
Test status
Simulation time	313986863 ps
CPU time	1.49 seconds
Started	Apr 18 01:51:07 PM PDT 24
Finished	Apr 18 01:51:09 PM PDT 24
Peak memory	202736 kb
Host	smart-c7d80eff-80aa-4d31-a321-19b579298419
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338243128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.2338243128
Directory	/workspace/7.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1828910266
Short name	T1019
Test name
Test status
Simulation time	740213395 ps
CPU time	4.58 seconds
Started	Apr 18 01:51:26 PM PDT 24
Finished	Apr 18 01:51:31 PM PDT 24
Peak memory	212072 kb
Host	smart-a8351a2a-4806-46ae-acfb-5a9225b721b3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828910266 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1828910266
Directory	/workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3061553071
Short name	T983
Test name
Test status
Simulation time	56142480 ps
CPU time	0.68 seconds
Started	Apr 18 01:51:22 PM PDT 24
Finished	Apr 18 01:51:23 PM PDT 24
Peak memory	202484 kb
Host	smart-32004d1f-1ce2-4d09-8fd3-fa0a79c3a2a7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061553071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.3061553071
Directory	/workspace/8.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2525787514
Short name	T58
Test name
Test status
Simulation time	36940315168 ps
CPU time	38.52 seconds
Started	Apr 18 01:51:17 PM PDT 24
Finished	Apr 18 01:51:56 PM PDT 24
Peak memory	202600 kb
Host	smart-54bcfee5-ce61-4bdd-bba6-b02998514725
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525787514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.2525787514
Directory	/workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3920290407
Short name	T64
Test name
Test status
Simulation time	23361719 ps
CPU time	0.78 seconds
Started	Apr 18 01:51:27 PM PDT 24
Finished	Apr 18 01:51:29 PM PDT 24
Peak memory	202556 kb
Host	smart-ac9136bb-94ab-4b85-ba11-be2dc5057a30
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920290407 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.3920290407
Directory	/workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1750158312
Short name	T955
Test name
Test status
Simulation time	328079287 ps
CPU time	2.39 seconds
Started	Apr 18 01:51:10 PM PDT 24
Finished	Apr 18 01:51:14 PM PDT 24
Peak memory	202864 kb
Host	smart-e6cf2301-13ca-4af7-b69f-1ef1b4d8cf9b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750158312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.1750158312
Directory	/workspace/8.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4216621909
Short name	T100
Test name
Test status
Simulation time	240782124 ps
CPU time	2.03 seconds
Started	Apr 18 01:51:24 PM PDT 24
Finished	Apr 18 01:51:27 PM PDT 24
Peak memory	202736 kb
Host	smart-53bf86bb-25a6-471e-8880-bf42aaee7f99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216621909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.4216621909
Directory	/workspace/8.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2834300231
Short name	T953
Test name
Test status
Simulation time	381445271 ps
CPU time	3.28 seconds
Started	Apr 18 01:51:08 PM PDT 24
Finished	Apr 18 01:51:11 PM PDT 24
Peak memory	210796 kb
Host	smart-733a30b3-36e9-43bc-a635-09ff8590c9db
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834300231 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.2834300231
Directory	/workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.419667169
Short name	T59
Test name
Test status
Simulation time	19616296 ps
CPU time	0.71 seconds
Started	Apr 18 01:51:26 PM PDT 24
Finished	Apr 18 01:51:28 PM PDT 24
Peak memory	202176 kb
Host	smart-12c91028-0e93-4316-8f4c-333cde65d37b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419667169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 9.sram_ctrl_csr_rw.419667169
Directory	/workspace/9.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3919143609
Short name	T1000
Test name
Test status
Simulation time	7063357638 ps
CPU time	48.72 seconds
Started	Apr 18 01:51:22 PM PDT 24
Finished	Apr 18 01:52:11 PM PDT 24
Peak memory	202716 kb
Host	smart-8f134897-3ee7-4ed8-9ab5-95f77d73c857
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919143609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3919143609
Directory	/workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2326538321
Short name	T89
Test name
Test status
Simulation time	50860384 ps
CPU time	0.76 seconds
Started	Apr 18 01:51:25 PM PDT 24
Finished	Apr 18 01:51:27 PM PDT 24
Peak memory	202536 kb
Host	smart-3cc2a54e-5e55-49f3-8611-d1b94986e1f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326538321 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2326538321
Directory	/workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2341928086
Short name	T938
Test name
Test status
Simulation time	772003183 ps
CPU time	2.7 seconds
Started	Apr 18 01:51:08 PM PDT 24
Finished	Apr 18 01:51:11 PM PDT 24
Peak memory	202856 kb
Host	smart-ff5fb998-da42-4e4e-bddc-2d46a618d5db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341928086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.2341928086
Directory	/workspace/9.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.sram_ctrl_bijection.834554371
Short name	T918
Test name
Test status
Simulation time	173250767753 ps
CPU time	838.21 seconds
Started	Apr 18 02:30:35 PM PDT 24
Finished	Apr 18 02:44:34 PM PDT 24
Peak memory	203740 kb
Host	smart-993c49e9-e0c0-4d1e-81ea-f772a4b9e5d0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834554371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.834554371
Directory	/workspace/0.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/0.sram_ctrl_executable.30734661
Short name	T30
Test name
Test status
Simulation time	13320373331 ps
CPU time	1352.63 seconds
Started	Apr 18 02:30:36 PM PDT 24
Finished	Apr 18 02:53:10 PM PDT 24
Peak memory	378008 kb
Host	smart-19b45918-cbfb-4408-9002-a8e887e26e8f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30734661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.30734661
Directory	/workspace/0.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/0.sram_ctrl_lc_escalation.3055477135
Short name	T783
Test name
Test status
Simulation time	1646928978 ps
CPU time	12.23 seconds
Started	Apr 18 02:30:35 PM PDT 24
Finished	Apr 18 02:30:48 PM PDT 24
Peak memory	202776 kb
Host	smart-8dcc81b8-0ccb-4a05-9afc-3f2595e168ac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055477135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.3055477135
Directory	/workspace/0.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/0.sram_ctrl_max_throughput.2274346077
Short name	T868
Test name
Test status
Simulation time	5634232154 ps
CPU time	45.93 seconds
Started	Apr 18 02:30:33 PM PDT 24
Finished	Apr 18 02:31:20 PM PDT 24
Peak memory	313484 kb
Host	smart-472a2e1c-874d-4e53-b144-a59c8a0b2075
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274346077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.2274346077
Directory	/workspace/0.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_partial_access.378919996
Short name	T434
Test name
Test status
Simulation time	2689835538 ps
CPU time	72.69 seconds
Started	Apr 18 02:31:23 PM PDT 24
Finished	Apr 18 02:32:36 PM PDT 24
Peak memory	211244 kb
Host	smart-31d4cf47-9168-4009-b08e-d3ad8b041c11
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378919996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_mem_partial_access.378919996
Directory	/workspace/0.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_walk.359463455
Short name	T426
Test name
Test status
Simulation time	6966794763 ps
CPU time	141.53 seconds
Started	Apr 18 02:30:34 PM PDT 24
Finished	Apr 18 02:32:56 PM PDT 24
Peak memory	203504 kb
Host	smart-a4e2cd10-6f6c-48cc-a178-49723a03c89c
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359463455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ mem_walk.359463455
Directory	/workspace/0.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/0.sram_ctrl_multiple_keys.904304276
Short name	T670
Test name
Test status
Simulation time	11246580993 ps
CPU time	1004.84 seconds
Started	Apr 18 02:30:28 PM PDT 24
Finished	Apr 18 02:47:13 PM PDT 24
Peak memory	374884 kb
Host	smart-17282706-cf73-45ee-bf22-f25562304c2b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904304276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multipl e_keys.904304276
Directory	/workspace/0.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access.2263463568
Short name	T493
Test name
Test status
Simulation time	1857656348 ps
CPU time	19.71 seconds
Started	Apr 18 02:30:36 PM PDT 24
Finished	Apr 18 02:30:56 PM PDT 24
Peak memory	257020 kb
Host	smart-52371ca8-a118-438d-ad7c-27cc31ba5da9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263463568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.2263463568
Directory	/workspace/0.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1074508105
Short name	T551
Test name
Test status
Simulation time	47462659758 ps
CPU time	163.37 seconds
Started	Apr 18 02:30:36 PM PDT 24
Finished	Apr 18 02:33:20 PM PDT 24
Peak memory	203380 kb
Host	smart-1dd3d4e8-f3b8-4f5e-be98-cb85d4989cd5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074508105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.1074508105
Directory	/workspace/0.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/0.sram_ctrl_ram_cfg.3318364441
Short name	T908
Test name
Test status
Simulation time	697341242 ps
CPU time	3.29 seconds
Started	Apr 18 02:30:32 PM PDT 24
Finished	Apr 18 02:30:36 PM PDT 24
Peak memory	203032 kb
Host	smart-65e789e1-d946-4c9c-8630-88f459cd4c52
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318364441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3318364441
Directory	/workspace/0.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/0.sram_ctrl_regwen.3876976981
Short name	T502
Test name
Test status
Simulation time	4782171525 ps
CPU time	801.02 seconds
Started	Apr 18 02:30:36 PM PDT 24
Finished	Apr 18 02:43:58 PM PDT 24
Peak memory	380124 kb
Host	smart-983de696-cfdb-4475-a332-fb7fbb5e4b3d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876976981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3876976981
Directory	/workspace/0.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/0.sram_ctrl_sec_cm.1663175523
Short name	T35
Test name
Test status
Simulation time	489402403 ps
CPU time	1.73 seconds
Started	Apr 18 02:30:37 PM PDT 24
Finished	Apr 18 02:30:39 PM PDT 24
Peak memory	222364 kb
Host	smart-d7543611-dd7d-4895-ae50-0337e6c6731e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663175523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1663175523
Directory	/workspace/0.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.sram_ctrl_smoke.2278076538
Short name	T639
Test name
Test status
Simulation time	2014430748 ps
CPU time	16 seconds
Started	Apr 18 02:30:28 PM PDT 24
Finished	Apr 18 02:30:44 PM PDT 24
Peak memory	202952 kb
Host	smart-f5da863b-8e40-4442-a4f1-5372ca925f30
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278076538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2278076538
Directory	/workspace/0.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all.210812029
Short name	T917
Test name
Test status
Simulation time	94128044228 ps
CPU time	9116.95 seconds
Started	Apr 18 02:30:36 PM PDT 24
Finished	Apr 18 05:02:34 PM PDT 24
Peak memory	387228 kb
Host	smart-319e99f4-b599-48d2-8ce0-38f3fda34c23
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210812029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_stress_all.210812029
Directory	/workspace/0.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.426105350
Short name	T930
Test name
Test status
Simulation time	1489412658 ps
CPU time	39.72 seconds
Started	Apr 18 02:30:33 PM PDT 24
Finished	Apr 18 02:31:14 PM PDT 24
Peak memory	211308 kb
Host	smart-04ee96ad-f51e-468d-8733-94523bb0bec8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=426105350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.426105350
Directory	/workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_pipeline.826232779
Short name	T461
Test name
Test status
Simulation time	4053920209 ps
CPU time	312.6 seconds
Started	Apr 18 02:30:37 PM PDT 24
Finished	Apr 18 02:35:50 PM PDT 24
Peak memory	203048 kb
Host	smart-a96897ab-3796-4ed8-a6fb-74bde92feb8d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826232779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_stress_pipeline.826232779
Directory	/workspace/0.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3553846789
Short name	T785
Test name
Test status
Simulation time	731005661 ps
CPU time	22.59 seconds
Started	Apr 18 02:30:33 PM PDT 24
Finished	Apr 18 02:30:56 PM PDT 24
Peak memory	268444 kb
Host	smart-7808541e-cbde-49b2-9f3f-1495eaa2631b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553846789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3553846789
Directory	/workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.876576652
Short name	T613
Test name
Test status
Simulation time	8974757544 ps
CPU time	519.93 seconds
Started	Apr 18 02:30:40 PM PDT 24
Finished	Apr 18 02:39:21 PM PDT 24
Peak memory	379004 kb
Host	smart-fbb3f366-1458-4178-8323-9280cfe40d66
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876576652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.sram_ctrl_access_during_key_req.876576652
Directory	/workspace/1.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/1.sram_ctrl_alert_test.2061019338
Short name	T416
Test name
Test status
Simulation time	47893311 ps
CPU time	0.67 seconds
Started	Apr 18 02:30:44 PM PDT 24
Finished	Apr 18 02:30:45 PM PDT 24
Peak memory	202732 kb
Host	smart-31a0e7e9-83c5-4e2d-b42e-db15f5b8144a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061019338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2061019338
Directory	/workspace/1.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.sram_ctrl_bijection.3688042061
Short name	T850
Test name
Test status
Simulation time	579827364549 ps
CPU time	2337.55 seconds
Started	Apr 18 02:30:38 PM PDT 24
Finished	Apr 18 03:09:36 PM PDT 24
Peak memory	203284 kb
Host	smart-06d5a590-6f6d-409b-886d-334febe0559c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688042061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 3688042061
Directory	/workspace/1.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/1.sram_ctrl_lc_escalation.165808488
Short name	T322
Test name
Test status
Simulation time	13669386335 ps
CPU time	48.47 seconds
Started	Apr 18 02:30:40 PM PDT 24
Finished	Apr 18 02:31:29 PM PDT 24
Peak memory	203028 kb
Host	smart-eaf38a2a-84a4-424f-b2ed-84c363da1abe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165808488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esca lation.165808488
Directory	/workspace/1.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/1.sram_ctrl_max_throughput.3671224615
Short name	T865
Test name
Test status
Simulation time	3959046686 ps
CPU time	28.55 seconds
Started	Apr 18 02:30:38 PM PDT 24
Finished	Apr 18 02:31:07 PM PDT 24
Peak memory	284800 kb
Host	smart-8dd990b7-9227-405d-b441-455e9297907b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671224615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.3671224615
Directory	/workspace/1.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3699177509
Short name	T848
Test name
Test status
Simulation time	30943292367 ps
CPU time	121.21 seconds
Started	Apr 18 02:30:39 PM PDT 24
Finished	Apr 18 02:32:41 PM PDT 24
Peak memory	219536 kb
Host	smart-0c685093-910a-4dc0-8772-974685f3bda5
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699177509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.3699177509
Directory	/workspace/1.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_walk.2457773155
Short name	T377
Test name
Test status
Simulation time	13775254944 ps
CPU time	137.8 seconds
Started	Apr 18 02:30:39 PM PDT 24
Finished	Apr 18 02:32:58 PM PDT 24
Peak memory	203180 kb
Host	smart-f1ccd6a4-7966-491e-a710-39b841efc8a9
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457773155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.2457773155
Directory	/workspace/1.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/1.sram_ctrl_multiple_keys.3394056367
Short name	T925
Test name
Test status
Simulation time	29866661775 ps
CPU time	571.73 seconds
Started	Apr 18 02:30:41 PM PDT 24
Finished	Apr 18 02:40:13 PM PDT 24
Peak memory	371828 kb
Host	smart-b33055d0-5ccd-4b1d-af20-f9d22a7855bf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394056367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.3394056367
Directory	/workspace/1.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access.3097475375
Short name	T602
Test name
Test status
Simulation time	1798237656 ps
CPU time	25.41 seconds
Started	Apr 18 02:30:40 PM PDT 24
Finished	Apr 18 02:31:06 PM PDT 24
Peak memory	203012 kb
Host	smart-00c32cb2-d61d-44f8-b6d6-0a6dbadd4d46
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097475375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.3097475375
Directory	/workspace/1.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2044576081
Short name	T182
Test name
Test status
Simulation time	132780399006 ps
CPU time	185.63 seconds
Started	Apr 18 02:30:38 PM PDT 24
Finished	Apr 18 02:33:45 PM PDT 24
Peak memory	203148 kb
Host	smart-199922ab-d10a-4fff-9c5a-c85767ff7c6f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044576081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.2044576081
Directory	/workspace/1.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/1.sram_ctrl_ram_cfg.2336630892
Short name	T766
Test name
Test status
Simulation time	350792358 ps
CPU time	3.04 seconds
Started	Apr 18 02:30:38 PM PDT 24
Finished	Apr 18 02:30:43 PM PDT 24
Peak memory	203028 kb
Host	smart-49407a99-ff58-40c5-984f-819956c46b2a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336630892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2336630892
Directory	/workspace/1.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/1.sram_ctrl_regwen.343131579
Short name	T596
Test name
Test status
Simulation time	19344509996 ps
CPU time	628.33 seconds
Started	Apr 18 02:30:39 PM PDT 24
Finished	Apr 18 02:41:08 PM PDT 24
Peak memory	376880 kb
Host	smart-f60bd1d5-5e30-4bf5-9c83-341dab01e58c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343131579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.343131579
Directory	/workspace/1.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/1.sram_ctrl_sec_cm.721300019
Short name	T22
Test name
Test status
Simulation time	477625463 ps
CPU time	3.68 seconds
Started	Apr 18 02:30:41 PM PDT 24
Finished	Apr 18 02:30:45 PM PDT 24
Peak memory	222104 kb
Host	smart-834383a8-8ea9-4e4f-a845-28e03a704dec
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721300019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_sec_cm.721300019
Directory	/workspace/1.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.sram_ctrl_smoke.2477239278
Short name	T163
Test name
Test status
Simulation time	4281872989 ps
CPU time	16.58 seconds
Started	Apr 18 02:30:39 PM PDT 24
Finished	Apr 18 02:30:56 PM PDT 24
Peak memory	203016 kb
Host	smart-9d9aea8d-b31b-4bf4-9632-fd51276b0a7d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477239278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2477239278
Directory	/workspace/1.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all.241260008
Short name	T539
Test name
Test status
Simulation time	235953629099 ps
CPU time	4468.75 seconds
Started	Apr 18 02:30:37 PM PDT 24
Finished	Apr 18 03:45:07 PM PDT 24
Peak memory	375992 kb
Host	smart-dc6e760d-5b7a-469f-a088-0fa90aa346f8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241260008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_stress_all.241260008
Directory	/workspace/1.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.416377557
Short name	T880
Test name
Test status
Simulation time	4852429934 ps
CPU time	31.22 seconds
Started	Apr 18 02:30:39 PM PDT 24
Finished	Apr 18 02:31:11 PM PDT 24
Peak memory	212432 kb
Host	smart-78bfd889-fe48-4b7f-a676-9d8d8ac89a17
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=416377557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.416377557
Directory	/workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2637978032
Short name	T516
Test name
Test status
Simulation time	18066935441 ps
CPU time	202.01 seconds
Started	Apr 18 02:30:40 PM PDT 24
Finished	Apr 18 02:34:03 PM PDT 24
Peak memory	203148 kb
Host	smart-b44375bd-7d87-4d93-aa94-4e7eb6db8900
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637978032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.2637978032
Directory	/workspace/1.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1208312807
Short name	T887
Test name
Test status
Simulation time	1618668851 ps
CPU time	127.94 seconds
Started	Apr 18 02:30:58 PM PDT 24
Finished	Apr 18 02:33:06 PM PDT 24
Peak memory	364556 kb
Host	smart-9bba6df7-1521-4b0d-8c55-2dc5213f6859
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208312807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.1208312807
Directory	/workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3959863035
Short name	T677
Test name
Test status
Simulation time	84382370045 ps
CPU time	464.69 seconds
Started	Apr 18 02:31:47 PM PDT 24
Finished	Apr 18 02:39:32 PM PDT 24
Peak memory	377460 kb
Host	smart-88362b80-6758-48d3-a378-49a479141a79
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959863035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.3959863035
Directory	/workspace/10.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/10.sram_ctrl_alert_test.543506738
Short name	T209
Test name
Test status
Simulation time	40791769 ps
CPU time	0.65 seconds
Started	Apr 18 02:31:52 PM PDT 24
Finished	Apr 18 02:31:53 PM PDT 24
Peak memory	202840 kb
Host	smart-391a7af9-86f7-4326-b41e-77cea708000c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543506738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.543506738
Directory	/workspace/10.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.sram_ctrl_bijection.2416202683
Short name	T229
Test name
Test status
Simulation time	330736222251 ps
CPU time	2734.38 seconds
Started	Apr 18 02:31:39 PM PDT 24
Finished	Apr 18 03:17:15 PM PDT 24
Peak memory	203472 kb
Host	smart-15716e03-8a09-40ad-a130-79f420bad906
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416202683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .2416202683
Directory	/workspace/10.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/10.sram_ctrl_executable.3421567747
Short name	T636
Test name
Test status
Simulation time	5116911490 ps
CPU time	516.44 seconds
Started	Apr 18 02:31:44 PM PDT 24
Finished	Apr 18 02:40:21 PM PDT 24
Peak memory	375924 kb
Host	smart-525b2b9f-cf9a-4c9e-8b59-841c8d7ea5b7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421567747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.3421567747
Directory	/workspace/10.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/10.sram_ctrl_lc_escalation.3692994759
Short name	T196
Test name
Test status
Simulation time	4358031817 ps
CPU time	14.69 seconds
Started	Apr 18 02:32:47 PM PDT 24
Finished	Apr 18 02:33:02 PM PDT 24
Peak memory	203068 kb
Host	smart-04b89e5b-3f23-4cd1-8c7c-5e3514919a52
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692994759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.3692994759
Directory	/workspace/10.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/10.sram_ctrl_max_throughput.2120716071
Short name	T733
Test name
Test status
Simulation time	1575254294 ps
CPU time	92.29 seconds
Started	Apr 18 02:31:47 PM PDT 24
Finished	Apr 18 02:33:19 PM PDT 24
Peak memory	358360 kb
Host	smart-6760c300-27cb-4c86-98fe-e502f3f26b9b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120716071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.2120716071
Directory	/workspace/10.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.421890797
Short name	T787
Test name
Test status
Simulation time	3801743522 ps
CPU time	61.16 seconds
Started	Apr 18 02:31:48 PM PDT 24
Finished	Apr 18 02:32:49 PM PDT 24
Peak memory	211296 kb
Host	smart-f113d0fc-e971-4e6f-b04b-c4e5a079a23d
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421890797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_mem_partial_access.421890797
Directory	/workspace/10.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_walk.3830195455
Short name	T462
Test name
Test status
Simulation time	71636727717 ps
CPU time	317.9 seconds
Started	Apr 18 02:31:48 PM PDT 24
Finished	Apr 18 02:37:06 PM PDT 24
Peak memory	203736 kb
Host	smart-7430d9d3-3090-40f3-aafd-aa1306c2b6f5
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830195455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.3830195455
Directory	/workspace/10.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/10.sram_ctrl_multiple_keys.2616084756
Short name	T793
Test name
Test status
Simulation time	14317490612 ps
CPU time	547.64 seconds
Started	Apr 18 02:31:46 PM PDT 24
Finished	Apr 18 02:40:54 PM PDT 24
Peak memory	353420 kb
Host	smart-c31116dc-5cb5-4732-91e1-418e7a1497d5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616084756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.2616084756
Directory	/workspace/10.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access.324246027
Short name	T542
Test name
Test status
Simulation time	3698808487 ps
CPU time	34.54 seconds
Started	Apr 18 02:31:40 PM PDT 24
Finished	Apr 18 02:32:15 PM PDT 24
Peak memory	286828 kb
Host	smart-293cc5ef-1a58-48dc-b34d-145639397d05
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324246027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.s ram_ctrl_partial_access.324246027
Directory	/workspace/10.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3620881301
Short name	T364
Test name
Test status
Simulation time	36465720944 ps
CPU time	455.55 seconds
Started	Apr 18 02:31:44 PM PDT 24
Finished	Apr 18 02:39:20 PM PDT 24
Peak memory	203196 kb
Host	smart-d09ee07c-c3b1-4e4d-a55e-a624b94b27ff
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620881301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.3620881301
Directory	/workspace/10.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/10.sram_ctrl_regwen.3635865826
Short name	T436
Test name
Test status
Simulation time	15287219647 ps
CPU time	572.95 seconds
Started	Apr 18 02:31:47 PM PDT 24
Finished	Apr 18 02:41:21 PM PDT 24
Peak memory	373188 kb
Host	smart-495bee8c-b29c-48bc-bdcd-1725d22aee76
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635865826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3635865826
Directory	/workspace/10.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/10.sram_ctrl_smoke.592311662
Short name	T232
Test name
Test status
Simulation time	702314904 ps
CPU time	6.85 seconds
Started	Apr 18 02:31:40 PM PDT 24
Finished	Apr 18 02:31:47 PM PDT 24
Peak memory	203012 kb
Host	smart-e2c167d5-5dc8-4419-9bf4-76971edede51
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592311662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.592311662
Directory	/workspace/10.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all.1030835357
Short name	T285
Test name
Test status
Simulation time	208504870772 ps
CPU time	6388.37 seconds
Started	Apr 18 02:31:52 PM PDT 24
Finished	Apr 18 04:18:22 PM PDT 24
Peak memory	383332 kb
Host	smart-386882b5-fce5-4185-8f93-4a6fd91085eb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030835357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.1030835357
Directory	/workspace/10.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3944807469
Short name	T645
Test name
Test status
Simulation time	189107181 ps
CPU time	5.61 seconds
Started	Apr 18 02:31:51 PM PDT 24
Finished	Apr 18 02:31:57 PM PDT 24
Peak memory	211268 kb
Host	smart-204438b8-40f9-4202-928d-23fd6580e729
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3944807469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3944807469
Directory	/workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_pipeline.4033359792
Short name	T627
Test name
Test status
Simulation time	11211418219 ps
CPU time	187.72 seconds
Started	Apr 18 02:31:40 PM PDT 24
Finished	Apr 18 02:34:48 PM PDT 24
Peak memory	203164 kb
Host	smart-d6671fd0-96b2-4271-b9e3-c049c9d7faf1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033359792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.4033359792
Directory	/workspace/10.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2865898854
Short name	T814
Test name
Test status
Simulation time	3270284039 ps
CPU time	125.6 seconds
Started	Apr 18 02:31:46 PM PDT 24
Finished	Apr 18 02:33:52 PM PDT 24
Peak memory	371720 kb
Host	smart-442ec075-80c8-4342-a895-b3f91c19910b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865898854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2865898854
Directory	/workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3649896391
Short name	T777
Test name
Test status
Simulation time	1146036147 ps
CPU time	126.18 seconds
Started	Apr 18 02:32:02 PM PDT 24
Finished	Apr 18 02:34:09 PM PDT 24
Peak memory	373740 kb
Host	smart-7824e68a-33b3-45b9-9319-dca7f481f004
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649896391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.3649896391
Directory	/workspace/11.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/11.sram_ctrl_alert_test.2074545100
Short name	T497
Test name
Test status
Simulation time	15424358 ps
CPU time	0.65 seconds
Started	Apr 18 02:32:07 PM PDT 24
Finished	Apr 18 02:32:08 PM PDT 24
Peak memory	202844 kb
Host	smart-7d6154b2-6bc4-4baa-ad06-33dd37ef79ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074545100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.2074545100
Directory	/workspace/11.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.sram_ctrl_bijection.1856221329
Short name	T648
Test name
Test status
Simulation time	55431523039 ps
CPU time	1263 seconds
Started	Apr 18 02:31:58 PM PDT 24
Finished	Apr 18 02:53:01 PM PDT 24
Peak memory	203024 kb
Host	smart-fb824b33-a8d6-4efb-9ef9-f53f7712f70f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856221329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .1856221329
Directory	/workspace/11.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/11.sram_ctrl_executable.566304892
Short name	T327
Test name
Test status
Simulation time	46652939078 ps
CPU time	1002.58 seconds
Started	Apr 18 02:32:07 PM PDT 24
Finished	Apr 18 02:48:50 PM PDT 24
Peak memory	373816 kb
Host	smart-6dfc0da5-426b-41cc-abb1-6e7f36bb7c60
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566304892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executabl e.566304892
Directory	/workspace/11.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/11.sram_ctrl_lc_escalation.2561251415
Short name	T174
Test name
Test status
Simulation time	17087799864 ps
CPU time	29.84 seconds
Started	Apr 18 02:32:05 PM PDT 24
Finished	Apr 18 02:32:35 PM PDT 24
Peak memory	211192 kb
Host	smart-03851ac8-2253-40a4-aec2-05a34f952d6e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561251415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.2561251415
Directory	/workspace/11.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/11.sram_ctrl_max_throughput.2791411019
Short name	T349
Test name
Test status
Simulation time	1557012551 ps
CPU time	16.63 seconds
Started	Apr 18 02:31:57 PM PDT 24
Finished	Apr 18 02:32:14 PM PDT 24
Peak memory	252100 kb
Host	smart-30dd909e-c02e-44cb-bb93-93eecb6c7a8b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791411019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.2791411019
Directory	/workspace/11.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.477865875
Short name	T584
Test name
Test status
Simulation time	19541104773 ps
CPU time	147.85 seconds
Started	Apr 18 02:32:10 PM PDT 24
Finished	Apr 18 02:34:38 PM PDT 24
Peak memory	211328 kb
Host	smart-b823fce6-55e8-496b-9271-04a8b24c6f81
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477865875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .sram_ctrl_mem_partial_access.477865875
Directory	/workspace/11.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_walk.2407534023
Short name	T564
Test name
Test status
Simulation time	4025839006 ps
CPU time	238.81 seconds
Started	Apr 18 02:32:01 PM PDT 24
Finished	Apr 18 02:36:01 PM PDT 24
Peak memory	203220 kb
Host	smart-0885273c-5817-492e-b991-25774e52e798
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407534023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.2407534023
Directory	/workspace/11.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/11.sram_ctrl_multiple_keys.4058182215
Short name	T219
Test name
Test status
Simulation time	1725208603 ps
CPU time	29.69 seconds
Started	Apr 18 02:31:51 PM PDT 24
Finished	Apr 18 02:32:22 PM PDT 24
Peak memory	202964 kb
Host	smart-79274921-8a74-440c-b070-0e54bfe451b0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058182215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.4058182215
Directory	/workspace/11.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access.1406300861
Short name	T414
Test name
Test status
Simulation time	636171220 ps
CPU time	20.07 seconds
Started	Apr 18 02:31:55 PM PDT 24
Finished	Apr 18 02:32:16 PM PDT 24
Peak memory	203064 kb
Host	smart-68510245-5675-4671-8700-2ce1a49366ae
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406300861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.1406300861
Directory	/workspace/11.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_ram_cfg.13541860
Short name	T846
Test name
Test status
Simulation time	710531326 ps
CPU time	3.16 seconds
Started	Apr 18 02:32:03 PM PDT 24
Finished	Apr 18 02:32:06 PM PDT 24
Peak memory	203020 kb
Host	smart-017ea829-ae71-4e4b-a03c-36e6a6f3ae05
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13541860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.13541860
Directory	/workspace/11.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/11.sram_ctrl_regwen.1424038591
Short name	T194
Test name
Test status
Simulation time	5241410079 ps
CPU time	363.98 seconds
Started	Apr 18 02:32:03 PM PDT 24
Finished	Apr 18 02:38:08 PM PDT 24
Peak memory	372216 kb
Host	smart-6c3876ab-e7db-46e9-a6b4-f7f23eb6df5d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424038591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1424038591
Directory	/workspace/11.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/11.sram_ctrl_smoke.3751309013
Short name	T393
Test name
Test status
Simulation time	801560116 ps
CPU time	50.18 seconds
Started	Apr 18 02:31:52 PM PDT 24
Finished	Apr 18 02:32:43 PM PDT 24
Peak memory	297916 kb
Host	smart-28d3a665-92a9-4532-a1ea-475e2124acd4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751309013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3751309013
Directory	/workspace/11.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_all.2448098950
Short name	T647
Test name
Test status
Simulation time	48460631051 ps
CPU time	2347.2 seconds
Started	Apr 18 02:32:10 PM PDT 24
Finished	Apr 18 03:11:18 PM PDT 24
Peak memory	295384 kb
Host	smart-7a01c96b-c9e7-4c9b-84a1-53845ecf04b7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448098950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.2448098950
Directory	/workspace/11.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3776107400
Short name	T838
Test name
Test status
Simulation time	1148856872 ps
CPU time	16.26 seconds
Started	Apr 18 02:32:09 PM PDT 24
Finished	Apr 18 02:32:25 PM PDT 24
Peak memory	211260 kb
Host	smart-bff08cab-d2ae-4058-9b4f-85334b630919
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3776107400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3776107400
Directory	/workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1291365123
Short name	T910
Test name
Test status
Simulation time	7657923279 ps
CPU time	206.19 seconds
Started	Apr 18 02:31:57 PM PDT 24
Finished	Apr 18 02:35:23 PM PDT 24
Peak memory	203144 kb
Host	smart-e53b0534-0ab1-4ff5-ae87-64c79235032b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291365123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.1291365123
Directory	/workspace/11.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3509579277
Short name	T160
Test name
Test status
Simulation time	4090566227 ps
CPU time	44.3 seconds
Started	Apr 18 02:32:03 PM PDT 24
Finished	Apr 18 02:32:47 PM PDT 24
Peak memory	301108 kb
Host	smart-250d0f97-3517-4eae-a3df-6b1847e0593c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509579277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3509579277
Directory	/workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.4143294636
Short name	T507
Test name
Test status
Simulation time	49263094135 ps
CPU time	1035.43 seconds
Started	Apr 18 02:32:21 PM PDT 24
Finished	Apr 18 02:49:37 PM PDT 24
Peak memory	376948 kb
Host	smart-29d44fe7-bc0b-4903-80ad-a0579d025f56
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143294636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.4143294636
Directory	/workspace/12.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/12.sram_ctrl_alert_test.1435167016
Short name	T449
Test name
Test status
Simulation time	32784053 ps
CPU time	0.63 seconds
Started	Apr 18 02:32:22 PM PDT 24
Finished	Apr 18 02:32:24 PM PDT 24
Peak memory	202660 kb
Host	smart-4a82d7eb-c331-4a07-bfce-d7a67e28f158
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435167016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.1435167016
Directory	/workspace/12.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.sram_ctrl_bijection.2659138437
Short name	T666
Test name
Test status
Simulation time	140737688501 ps
CPU time	2271.69 seconds
Started	Apr 18 02:32:14 PM PDT 24
Finished	Apr 18 03:10:06 PM PDT 24
Peak memory	203432 kb
Host	smart-1fe53add-6b13-4f6b-b9ff-2733fe03289f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659138437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .2659138437
Directory	/workspace/12.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/12.sram_ctrl_executable.2659088641
Short name	T514
Test name
Test status
Simulation time	13738902627 ps
CPU time	535.57 seconds
Started	Apr 18 02:32:19 PM PDT 24
Finished	Apr 18 02:41:15 PM PDT 24
Peak memory	378008 kb
Host	smart-8cfd5f9d-8993-4357-a76a-ef5fec2813f3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659088641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.2659088641
Directory	/workspace/12.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/12.sram_ctrl_lc_escalation.3594963003
Short name	T350
Test name
Test status
Simulation time	9375541704 ps
CPU time	54.48 seconds
Started	Apr 18 02:32:18 PM PDT 24
Finished	Apr 18 02:33:13 PM PDT 24
Peak memory	211300 kb
Host	smart-8de9c771-12c6-4b1e-926b-66c05c605254
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594963003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.3594963003
Directory	/workspace/12.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/12.sram_ctrl_max_throughput.187067921
Short name	T621
Test name
Test status
Simulation time	757929603 ps
CPU time	40.68 seconds
Started	Apr 18 02:32:19 PM PDT 24
Finished	Apr 18 02:33:01 PM PDT 24
Peak memory	293968 kb
Host	smart-5060b4d5-0683-4b07-a22b-2621855d350e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187067921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.sram_ctrl_max_throughput.187067921
Directory	/workspace/12.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.413515306
Short name	T891
Test name
Test status
Simulation time	11819819128 ps
CPU time	148.92 seconds
Started	Apr 18 02:32:23 PM PDT 24
Finished	Apr 18 02:34:52 PM PDT 24
Peak memory	211308 kb
Host	smart-99c0adf1-8bbc-41f3-88f9-c740f66031b6
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413515306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_mem_partial_access.413515306
Directory	/workspace/12.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_walk.1204532444
Short name	T920
Test name
Test status
Simulation time	7341349378 ps
CPU time	143.9 seconds
Started	Apr 18 02:32:23 PM PDT 24
Finished	Apr 18 02:34:48 PM PDT 24
Peak memory	203556 kb
Host	smart-c39a1c13-2d34-4f7c-9bc6-f10055967104
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204532444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.1204532444
Directory	/workspace/12.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/12.sram_ctrl_multiple_keys.3216256121
Short name	T126
Test name
Test status
Simulation time	173424578558 ps
CPU time	1278.99 seconds
Started	Apr 18 02:32:10 PM PDT 24
Finished	Apr 18 02:53:29 PM PDT 24
Peak memory	380056 kb
Host	smart-e807dc5a-4bc2-465f-9ade-30545af2006a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216256121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.3216256121
Directory	/workspace/12.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access.2949390451
Short name	T858
Test name
Test status
Simulation time	2834831136 ps
CPU time	6.94 seconds
Started	Apr 18 02:32:13 PM PDT 24
Finished	Apr 18 02:32:20 PM PDT 24
Peak memory	202864 kb
Host	smart-7c23b7bb-1f53-4019-872e-e474d570c02e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949390451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.2949390451
Directory	/workspace/12.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3894543651
Short name	T810
Test name
Test status
Simulation time	6550091930 ps
CPU time	152.03 seconds
Started	Apr 18 02:32:17 PM PDT 24
Finished	Apr 18 02:34:50 PM PDT 24
Peak memory	203164 kb
Host	smart-f94c8c6d-10df-45e4-9bdd-9e26c0cc046c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894543651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.3894543651
Directory	/workspace/12.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/12.sram_ctrl_ram_cfg.4269802176
Short name	T871
Test name
Test status
Simulation time	346026362 ps
CPU time	3.2 seconds
Started	Apr 18 02:32:25 PM PDT 24
Finished	Apr 18 02:32:28 PM PDT 24
Peak memory	203068 kb
Host	smart-e040d725-28d6-474c-8f0c-f6aadca1773b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269802176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.4269802176
Directory	/workspace/12.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/12.sram_ctrl_regwen.3505593083
Short name	T529
Test name
Test status
Simulation time	19091423118 ps
CPU time	188.8 seconds
Started	Apr 18 02:32:23 PM PDT 24
Finished	Apr 18 02:35:32 PM PDT 24
Peak memory	371292 kb
Host	smart-7c4d59b2-a99b-41cd-8009-d0c532b186e7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505593083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3505593083
Directory	/workspace/12.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/12.sram_ctrl_smoke.1318018166
Short name	T473
Test name
Test status
Simulation time	2870973310 ps
CPU time	20.87 seconds
Started	Apr 18 02:32:08 PM PDT 24
Finished	Apr 18 02:32:29 PM PDT 24
Peak memory	203008 kb
Host	smart-755c9e46-09cd-4e57-9240-e078c69adc7e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318018166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1318018166
Directory	/workspace/12.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all.616021924
Short name	T129
Test name
Test status
Simulation time	67914271902 ps
CPU time	1294.77 seconds
Started	Apr 18 02:32:24 PM PDT 24
Finished	Apr 18 02:53:59 PM PDT 24
Peak memory	379024 kb
Host	smart-b772722f-1322-45a8-99b4-78c896c61e81
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616021924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_stress_all.616021924
Directory	/workspace/12.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3382520851
Short name	T459
Test name
Test status
Simulation time	30935274880 ps
CPU time	184.38 seconds
Started	Apr 18 02:32:12 PM PDT 24
Finished	Apr 18 02:35:17 PM PDT 24
Peak memory	203148 kb
Host	smart-923ab923-6654-4c1d-97e7-e1391866f1e9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382520851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.3382520851
Directory	/workspace/12.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4264316685
Short name	T612
Test name
Test status
Simulation time	1144056230 ps
CPU time	10.51 seconds
Started	Apr 18 02:32:17 PM PDT 24
Finished	Apr 18 02:32:28 PM PDT 24
Peak memory	227940 kb
Host	smart-5e69d2cc-a5f4-4718-902c-1b8b387e1636
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264316685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.4264316685
Directory	/workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1021902357
Short name	T45
Test name
Test status
Simulation time	1063314570 ps
CPU time	13.27 seconds
Started	Apr 18 02:32:36 PM PDT 24
Finished	Apr 18 02:32:49 PM PDT 24
Peak memory	203024 kb
Host	smart-405b2ce6-dfa9-4f7f-be64-728fa6e21d39
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021902357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.1021902357
Directory	/workspace/13.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/13.sram_ctrl_alert_test.3246284890
Short name	T216
Test name
Test status
Simulation time	41718479 ps
CPU time	0.64 seconds
Started	Apr 18 02:32:41 PM PDT 24
Finished	Apr 18 02:32:42 PM PDT 24
Peak memory	202772 kb
Host	smart-25686bb9-645c-4fa5-b3e2-9f8c87619acb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246284890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3246284890
Directory	/workspace/13.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.sram_ctrl_bijection.1083653440
Short name	T415
Test name
Test status
Simulation time	520016454282 ps
CPU time	1078.04 seconds
Started	Apr 18 02:32:30 PM PDT 24
Finished	Apr 18 02:50:29 PM PDT 24
Peak memory	203384 kb
Host	smart-a9eaa0fa-cb32-4952-9581-774947acc958
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083653440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .1083653440
Directory	/workspace/13.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/13.sram_ctrl_executable.2311357268
Short name	T179
Test name
Test status
Simulation time	133623188317 ps
CPU time	1162.02 seconds
Started	Apr 18 02:32:34 PM PDT 24
Finished	Apr 18 02:51:56 PM PDT 24
Peak memory	361628 kb
Host	smart-9f81889e-aa06-46d1-b7d2-17f096e65a13
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311357268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.2311357268
Directory	/workspace/13.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/13.sram_ctrl_lc_escalation.2386713772
Short name	T247
Test name
Test status
Simulation time	57287123809 ps
CPU time	106.79 seconds
Started	Apr 18 02:32:33 PM PDT 24
Finished	Apr 18 02:34:20 PM PDT 24
Peak memory	203120 kb
Host	smart-48d764ac-7f3a-4b65-8b66-d3264587cfbb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386713772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.2386713772
Directory	/workspace/13.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/13.sram_ctrl_max_throughput.3263689803
Short name	T245
Test name
Test status
Simulation time	3062263124 ps
CPU time	110.99 seconds
Started	Apr 18 02:33:21 PM PDT 24
Finished	Apr 18 02:35:12 PM PDT 24
Peak memory	370672 kb
Host	smart-6865aa11-7cb2-48d1-9d4d-aee69a37c636
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263689803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.3263689803
Directory	/workspace/13.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.656655515
Short name	T705
Test name
Test status
Simulation time	1926934788 ps
CPU time	61.59 seconds
Started	Apr 18 02:32:39 PM PDT 24
Finished	Apr 18 02:33:41 PM PDT 24
Peak memory	211224 kb
Host	smart-11f1d3a6-d77c-47c3-b76d-365d7d5de3fc
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656655515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13 .sram_ctrl_mem_partial_access.656655515
Directory	/workspace/13.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_walk.330295070
Short name	T368
Test name
Test status
Simulation time	4106475294 ps
CPU time	240.95 seconds
Started	Apr 18 02:32:41 PM PDT 24
Finished	Apr 18 02:36:43 PM PDT 24
Peak memory	203628 kb
Host	smart-4eeb51b4-e5b8-42fb-88b1-d3c2f677f169
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330295070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _mem_walk.330295070
Directory	/workspace/13.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/13.sram_ctrl_multiple_keys.844362977
Short name	T351
Test name
Test status
Simulation time	17451531038 ps
CPU time	1205.54 seconds
Started	Apr 18 02:32:29 PM PDT 24
Finished	Apr 18 02:52:35 PM PDT 24
Peak memory	380208 kb
Host	smart-59d2f5bf-c970-42b3-9bf8-b093042f5db0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844362977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip le_keys.844362977
Directory	/workspace/13.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access.84009230
Short name	T694
Test name
Test status
Simulation time	362254397 ps
CPU time	4.49 seconds
Started	Apr 18 02:32:28 PM PDT 24
Finished	Apr 18 02:32:33 PM PDT 24
Peak memory	206176 kb
Host	smart-46884295-8bd9-4aa6-91c3-50875f4dd933
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84009230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sr am_ctrl_partial_access.84009230
Directory	/workspace/13.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1622364431
Short name	T299
Test name
Test status
Simulation time	19939820643 ps
CPU time	250.13 seconds
Started	Apr 18 02:32:29 PM PDT 24
Finished	Apr 18 02:36:40 PM PDT 24
Peak memory	203184 kb
Host	smart-4ba5c257-4b10-4bd7-a1e0-ad137669f972
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622364431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.1622364431
Directory	/workspace/13.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/13.sram_ctrl_ram_cfg.659114549
Short name	T142
Test name
Test status
Simulation time	1158953056 ps
CPU time	3.39 seconds
Started	Apr 18 02:32:40 PM PDT 24
Finished	Apr 18 02:32:43 PM PDT 24
Peak memory	203032 kb
Host	smart-ea173d50-1fe0-4be1-94dd-c389b061f774
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659114549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.659114549
Directory	/workspace/13.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/13.sram_ctrl_smoke.93721529
Short name	T376
Test name
Test status
Simulation time	937778567 ps
CPU time	9.56 seconds
Started	Apr 18 02:32:24 PM PDT 24
Finished	Apr 18 02:32:34 PM PDT 24
Peak memory	203004 kb
Host	smart-6f17ed1d-a9c0-49d5-93d3-ea908aa3707d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93721529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.93721529
Directory	/workspace/13.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_all.3616866911
Short name	T590
Test name
Test status
Simulation time	482191530281 ps
CPU time	4445.99 seconds
Started	Apr 18 02:32:42 PM PDT 24
Finished	Apr 18 03:46:49 PM PDT 24
Peak memory	378796 kb
Host	smart-d7d1cf7f-663f-498a-be6b-6a836dc14f15
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616866911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.3616866911
Directory	/workspace/13.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.183361662
Short name	T50
Test name
Test status
Simulation time	619219390 ps
CPU time	9.88 seconds
Started	Apr 18 02:32:40 PM PDT 24
Finished	Apr 18 02:32:51 PM PDT 24
Peak memory	211280 kb
Host	smart-d30ddf7b-8422-4cac-8de6-6781f346da01
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=183361662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.183361662
Directory	/workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2724681329
Short name	T335
Test name
Test status
Simulation time	4958050442 ps
CPU time	242.11 seconds
Started	Apr 18 02:32:27 PM PDT 24
Finished	Apr 18 02:36:30 PM PDT 24
Peak memory	203156 kb
Host	smart-b0c8fef6-c8ec-40ee-9735-b2272f6c4f5a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724681329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.2724681329
Directory	/workspace/13.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1752408044
Short name	T271
Test name
Test status
Simulation time	6641269759 ps
CPU time	6.13 seconds
Started	Apr 18 02:32:40 PM PDT 24
Finished	Apr 18 02:32:47 PM PDT 24
Peak memory	202884 kb
Host	smart-13a0f753-a4f3-4565-b2a5-b42290d65db0
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752408044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1752408044
Directory	/workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.4081899518
Short name	T75
Test name
Test status
Simulation time	46243942058 ps
CPU time	891.93 seconds
Started	Apr 18 02:32:50 PM PDT 24
Finished	Apr 18 02:47:42 PM PDT 24
Peak memory	380096 kb
Host	smart-8b030f1f-2504-444e-9bd9-a70cb7836caf
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081899518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.4081899518
Directory	/workspace/14.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/14.sram_ctrl_alert_test.975633973
Short name	T225
Test name
Test status
Simulation time	15060539 ps
CPU time	0.64 seconds
Started	Apr 18 02:32:56 PM PDT 24
Finished	Apr 18 02:32:57 PM PDT 24
Peak memory	202224 kb
Host	smart-447a3402-65f5-493c-878d-5570428c6082
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975633973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.975633973
Directory	/workspace/14.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.sram_ctrl_bijection.2294139515
Short name	T695
Test name
Test status
Simulation time	167338859378 ps
CPU time	2206.36 seconds
Started	Apr 18 02:32:44 PM PDT 24
Finished	Apr 18 03:09:31 PM PDT 24
Peak memory	203104 kb
Host	smart-4b9095a1-3929-460d-a044-4d10a4811bf5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294139515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .2294139515
Directory	/workspace/14.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/14.sram_ctrl_executable.250862743
Short name	T631
Test name
Test status
Simulation time	30424907127 ps
CPU time	992.95 seconds
Started	Apr 18 02:32:51 PM PDT 24
Finished	Apr 18 02:49:24 PM PDT 24
Peak memory	374856 kb
Host	smart-24b294d3-6527-403f-a2fc-14966758504d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250862743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executabl e.250862743
Directory	/workspace/14.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/14.sram_ctrl_lc_escalation.2060808084
Short name	T521
Test name
Test status
Simulation time	44265992946 ps
CPU time	31.41 seconds
Started	Apr 18 02:32:50 PM PDT 24
Finished	Apr 18 02:33:21 PM PDT 24
Peak memory	215712 kb
Host	smart-8fb1fa94-8df1-4968-8ec6-0cb4a191a786
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060808084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.2060808084
Directory	/workspace/14.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/14.sram_ctrl_max_throughput.689294989
Short name	T135
Test name
Test status
Simulation time	3099615465 ps
CPU time	9.88 seconds
Started	Apr 18 02:32:50 PM PDT 24
Finished	Apr 18 02:33:01 PM PDT 24
Peak memory	227464 kb
Host	smart-b71f7a74-963b-4bcd-b76f-61596ddfa1db
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689294989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.sram_ctrl_max_throughput.689294989
Directory	/workspace/14.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.272233125
Short name	T689
Test name
Test status
Simulation time	11057036962 ps
CPU time	124.97 seconds
Started	Apr 18 02:32:55 PM PDT 24
Finished	Apr 18 02:35:01 PM PDT 24
Peak memory	211388 kb
Host	smart-7e9458ec-2c03-4777-904b-d7b3398c6aa1
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272233125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14 .sram_ctrl_mem_partial_access.272233125
Directory	/workspace/14.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_walk.68823672
Short name	T511
Test name
Test status
Simulation time	14034104248 ps
CPU time	149.29 seconds
Started	Apr 18 02:32:49 PM PDT 24
Finished	Apr 18 02:35:19 PM PDT 24
Peak memory	203608 kb
Host	smart-b532bbde-9d40-4607-82c0-ce7ef06c966e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68823672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ mem_walk.68823672
Directory	/workspace/14.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/14.sram_ctrl_multiple_keys.3771747569
Short name	T396
Test name
Test status
Simulation time	5504700848 ps
CPU time	375.83 seconds
Started	Apr 18 02:32:43 PM PDT 24
Finished	Apr 18 02:39:00 PM PDT 24
Peak memory	344196 kb
Host	smart-8e4e5ff3-b6c7-44cf-b4fd-0699c18e47f6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771747569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.3771747569
Directory	/workspace/14.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access.3367520189
Short name	T491
Test name
Test status
Simulation time	2025859081 ps
CPU time	111.11 seconds
Started	Apr 18 02:32:44 PM PDT 24
Finished	Apr 18 02:34:36 PM PDT 24
Peak memory	367580 kb
Host	smart-62e4b0ca-5c23-4485-8e27-32566496a917
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367520189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.3367520189
Directory	/workspace/14.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.972854470
Short name	T328
Test name
Test status
Simulation time	7591668077 ps
CPU time	172.09 seconds
Started	Apr 18 02:32:44 PM PDT 24
Finished	Apr 18 02:35:36 PM PDT 24
Peak memory	203196 kb
Host	smart-5340eb43-bf17-4ae6-8d2a-e06b28b25773
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972854470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.sram_ctrl_partial_access_b2b.972854470
Directory	/workspace/14.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/14.sram_ctrl_ram_cfg.3451774017
Short name	T19
Test name
Test status
Simulation time	359562036 ps
CPU time	3.46 seconds
Started	Apr 18 02:32:51 PM PDT 24
Finished	Apr 18 02:32:55 PM PDT 24
Peak memory	202996 kb
Host	smart-a9422750-0940-47d6-b56a-08c2fdc42f29
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451774017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.3451774017
Directory	/workspace/14.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/14.sram_ctrl_regwen.2275275431
Short name	T227
Test name
Test status
Simulation time	2564385527 ps
CPU time	714.8 seconds
Started	Apr 18 02:32:49 PM PDT 24
Finished	Apr 18 02:44:45 PM PDT 24
Peak memory	377900 kb
Host	smart-871ee51a-9a42-4244-84d0-2798a4876fb2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275275431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2275275431
Directory	/workspace/14.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/14.sram_ctrl_smoke.177503141
Short name	T690
Test name
Test status
Simulation time	923590359 ps
CPU time	13.41 seconds
Started	Apr 18 02:32:45 PM PDT 24
Finished	Apr 18 02:32:59 PM PDT 24
Peak memory	202956 kb
Host	smart-c675096c-5cdb-4962-baf0-36d3d3af1c4e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177503141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.177503141
Directory	/workspace/14.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_all.929272087
Short name	T125
Test name
Test status
Simulation time	220720747479 ps
CPU time	5068.39 seconds
Started	Apr 18 02:32:55 PM PDT 24
Finished	Apr 18 03:57:24 PM PDT 24
Peak memory	380104 kb
Host	smart-812a6b47-7fc9-4b67-a7a4-b95fa201ff16
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929272087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_stress_all.929272087
Directory	/workspace/14.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1777809955
Short name	T251
Test name
Test status
Simulation time	2355094146 ps
CPU time	297.38 seconds
Started	Apr 18 02:32:54 PM PDT 24
Finished	Apr 18 02:37:53 PM PDT 24
Peak memory	376180 kb
Host	smart-afecd99a-2dd8-41d9-91e5-e5c08889b59d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1777809955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1777809955
Directory	/workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_pipeline.3434116169
Short name	T433
Test name
Test status
Simulation time	7449642326 ps
CPU time	185.42 seconds
Started	Apr 18 02:32:46 PM PDT 24
Finished	Apr 18 02:35:52 PM PDT 24
Peak memory	203112 kb
Host	smart-98594962-620a-4ef5-934a-b27d9247c65f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434116169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.3434116169
Directory	/workspace/14.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3545643591
Short name	T238
Test name
Test status
Simulation time	2763677323 ps
CPU time	25.04 seconds
Started	Apr 18 02:32:51 PM PDT 24
Finished	Apr 18 02:33:16 PM PDT 24
Peak memory	278704 kb
Host	smart-7f09f7f8-505d-43b2-a00b-5f23f1e413be
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545643591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3545643591
Directory	/workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.157910164
Short name	T593
Test name
Test status
Simulation time	10713696676 ps
CPU time	811.42 seconds
Started	Apr 18 02:33:00 PM PDT 24
Finished	Apr 18 02:46:31 PM PDT 24
Peak memory	376960 kb
Host	smart-7c838acf-f839-4fcf-bb64-a91d7dbe6973
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157910164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_access_during_key_req.157910164
Directory	/workspace/15.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/15.sram_ctrl_alert_test.807128071
Short name	T157
Test name
Test status
Simulation time	24089593 ps
CPU time	0.65 seconds
Started	Apr 18 02:33:11 PM PDT 24
Finished	Apr 18 02:33:12 PM PDT 24
Peak memory	202780 kb
Host	smart-c04ad843-1633-4384-b40b-74ce02fba4e0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807128071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.807128071
Directory	/workspace/15.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.sram_ctrl_executable.2574515150
Short name	T407
Test name
Test status
Simulation time	48878424917 ps
CPU time	697.69 seconds
Started	Apr 18 02:33:06 PM PDT 24
Finished	Apr 18 02:44:44 PM PDT 24
Peak memory	375860 kb
Host	smart-78736705-7ef3-4aef-9d8f-448c22bb8d22
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574515150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.2574515150
Directory	/workspace/15.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/15.sram_ctrl_lc_escalation.58771273
Short name	T338
Test name
Test status
Simulation time	2621410872 ps
CPU time	14.71 seconds
Started	Apr 18 02:33:01 PM PDT 24
Finished	Apr 18 02:33:16 PM PDT 24
Peak memory	203040 kb
Host	smart-b69a94f9-65db-438b-ad55-f5d16e905e12
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58771273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_esca lation.58771273
Directory	/workspace/15.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/15.sram_ctrl_max_throughput.2176059733
Short name	T764
Test name
Test status
Simulation time	753358388 ps
CPU time	80.67 seconds
Started	Apr 18 02:32:59 PM PDT 24
Finished	Apr 18 02:34:20 PM PDT 24
Peak memory	345100 kb
Host	smart-73b726bd-53db-4663-82ff-6902083aef09
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176059733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.2176059733
Directory	/workspace/15.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_partial_access.286817000
Short name	T382
Test name
Test status
Simulation time	1855982080 ps
CPU time	63.36 seconds
Started	Apr 18 02:33:08 PM PDT 24
Finished	Apr 18 02:34:12 PM PDT 24
Peak memory	211224 kb
Host	smart-96c732bf-e11c-424f-b305-f603e6a9db72
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286817000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .sram_ctrl_mem_partial_access.286817000
Directory	/workspace/15.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_walk.3750251327
Short name	T188
Test name
Test status
Simulation time	2061146407 ps
CPU time	123.83 seconds
Started	Apr 18 02:33:08 PM PDT 24
Finished	Apr 18 02:35:12 PM PDT 24
Peak memory	203176 kb
Host	smart-2df4294c-1998-4499-8b81-63b9825a7525
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750251327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.3750251327
Directory	/workspace/15.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/15.sram_ctrl_multiple_keys.2494091325
Short name	T770
Test name
Test status
Simulation time	30497322288 ps
CPU time	798.61 seconds
Started	Apr 18 02:32:55 PM PDT 24
Finished	Apr 18 02:46:14 PM PDT 24
Peak memory	379948 kb
Host	smart-f0a01ca5-f141-4afa-855c-e503d933d7d8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494091325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.2494091325
Directory	/workspace/15.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access.52497305
Short name	T523
Test name
Test status
Simulation time	5061649814 ps
CPU time	119.87 seconds
Started	Apr 18 02:33:00 PM PDT 24
Finished	Apr 18 02:35:01 PM PDT 24
Peak memory	350392 kb
Host	smart-557542df-f940-495b-8a9d-5d2b5cab2713
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52497305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sr am_ctrl_partial_access.52497305
Directory	/workspace/15.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2600919853
Short name	T185
Test name
Test status
Simulation time	17331487887 ps
CPU time	354.42 seconds
Started	Apr 18 02:33:00 PM PDT 24
Finished	Apr 18 02:38:54 PM PDT 24
Peak memory	203036 kb
Host	smart-8d409d20-a2b1-498f-83ae-e6b8bdefe0b0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600919853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.2600919853
Directory	/workspace/15.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/15.sram_ctrl_ram_cfg.1771767258
Short name	T290
Test name
Test status
Simulation time	353268288 ps
CPU time	3 seconds
Started	Apr 18 02:33:05 PM PDT 24
Finished	Apr 18 02:33:08 PM PDT 24
Peak memory	202980 kb
Host	smart-4cf9f0a4-d29c-4622-b480-b470ffc1de9c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771767258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1771767258
Directory	/workspace/15.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/15.sram_ctrl_regwen.3236364214
Short name	T381
Test name
Test status
Simulation time	57745447578 ps
CPU time	1400.65 seconds
Started	Apr 18 02:33:05 PM PDT 24
Finished	Apr 18 02:56:26 PM PDT 24
Peak memory	380052 kb
Host	smart-ec059958-e229-48cc-9431-508b3224f658
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236364214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3236364214
Directory	/workspace/15.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/15.sram_ctrl_smoke.2785849958
Short name	T341
Test name
Test status
Simulation time	1676961312 ps
CPU time	8.89 seconds
Started	Apr 18 02:32:54 PM PDT 24
Finished	Apr 18 02:33:03 PM PDT 24
Peak memory	203028 kb
Host	smart-8ee46201-d52c-4f42-9328-0958e8f5fc39
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785849958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2785849958
Directory	/workspace/15.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all.1674616248
Short name	T211
Test name
Test status
Simulation time	181520929970 ps
CPU time	3941.43 seconds
Started	Apr 18 02:33:07 PM PDT 24
Finished	Apr 18 03:38:49 PM PDT 24
Peak memory	381128 kb
Host	smart-1986469d-d0db-46cc-b0f0-73347ed50f2e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674616248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.1674616248
Directory	/workspace/15.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3206834469
Short name	T102
Test name
Test status
Simulation time	2878199773 ps
CPU time	38.5 seconds
Started	Apr 18 02:33:05 PM PDT 24
Finished	Apr 18 02:33:44 PM PDT 24
Peak memory	211300 kb
Host	smart-0462831e-56be-45e4-a6b1-622c70df9b1f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3206834469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3206834469
Directory	/workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.4111005245
Short name	T724
Test name
Test status
Simulation time	10459595120 ps
CPU time	308.26 seconds
Started	Apr 18 02:33:01 PM PDT 24
Finished	Apr 18 02:38:10 PM PDT 24
Peak memory	203116 kb
Host	smart-42788278-bed6-49be-b426-1255e4a51e75
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111005245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.4111005245
Directory	/workspace/15.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1610557107
Short name	T555
Test name
Test status
Simulation time	3078811001 ps
CPU time	8.05 seconds
Started	Apr 18 02:33:01 PM PDT 24
Finished	Apr 18 02:33:09 PM PDT 24
Peak memory	219284 kb
Host	smart-98de22c5-e1e6-4c23-816b-e80be06b67c7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610557107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.1610557107
Directory	/workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3070883178
Short name	T17
Test name
Test status
Simulation time	45281793892 ps
CPU time	738.01 seconds
Started	Apr 18 02:33:16 PM PDT 24
Finished	Apr 18 02:45:34 PM PDT 24
Peak memory	378008 kb
Host	smart-efb6bfdf-2d92-4e1d-abe8-619e8eb54e59
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070883178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.3070883178
Directory	/workspace/16.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/16.sram_ctrl_alert_test.1287637284
Short name	T898
Test name
Test status
Simulation time	16530257 ps
CPU time	0.65 seconds
Started	Apr 18 02:33:26 PM PDT 24
Finished	Apr 18 02:33:26 PM PDT 24
Peak memory	202784 kb
Host	smart-f9826880-1981-4c95-a094-ed9e767e4fd7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287637284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.1287637284
Directory	/workspace/16.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.sram_ctrl_bijection.985217682
Short name	T172
Test name
Test status
Simulation time	690279771225 ps
CPU time	2331.62 seconds
Started	Apr 18 02:33:10 PM PDT 24
Finished	Apr 18 03:12:02 PM PDT 24
Peak memory	203404 kb
Host	smart-f6d18b95-d5af-46f0-99aa-e2c1ddfe8841
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985217682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection. 985217682
Directory	/workspace/16.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/16.sram_ctrl_executable.2037218829
Short name	T739
Test name
Test status
Simulation time	117005252080 ps
CPU time	1262.65 seconds
Started	Apr 18 02:33:21 PM PDT 24
Finished	Apr 18 02:54:25 PM PDT 24
Peak memory	374900 kb
Host	smart-d7e845be-b8f0-49ea-9fe5-c2f6f5d1e828
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037218829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.2037218829
Directory	/workspace/16.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/16.sram_ctrl_lc_escalation.2220696046
Short name	T665
Test name
Test status
Simulation time	3199121495 ps
CPU time	7.48 seconds
Started	Apr 18 02:33:17 PM PDT 24
Finished	Apr 18 02:33:25 PM PDT 24
Peak memory	211044 kb
Host	smart-903ad1f4-352d-4b64-ac5e-98c0af8474b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220696046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.2220696046
Directory	/workspace/16.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/16.sram_ctrl_max_throughput.2830080580
Short name	T641
Test name
Test status
Simulation time	760969690 ps
CPU time	82.19 seconds
Started	Apr 18 02:33:15 PM PDT 24
Finished	Apr 18 02:34:38 PM PDT 24
Peak memory	323612 kb
Host	smart-ca5c08bb-effd-49ed-ba58-4908543dc36e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830080580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.2830080580
Directory	/workspace/16.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.697308908
Short name	T774
Test name
Test status
Simulation time	6498338389 ps
CPU time	123.99 seconds
Started	Apr 18 02:33:26 PM PDT 24
Finished	Apr 18 02:35:30 PM PDT 24
Peak memory	211288 kb
Host	smart-ffe08032-58b7-4e44-b166-939a12adcd91
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697308908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_mem_partial_access.697308908
Directory	/workspace/16.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_walk.4008618086
Short name	T782
Test name
Test status
Simulation time	37271237671 ps
CPU time	147.56 seconds
Started	Apr 18 02:33:21 PM PDT 24
Finished	Apr 18 02:35:49 PM PDT 24
Peak memory	203592 kb
Host	smart-d866cef5-9c08-4e8f-8b5c-086eaefe2562
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008618086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.4008618086
Directory	/workspace/16.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/16.sram_ctrl_multiple_keys.2914805143
Short name	T600
Test name
Test status
Simulation time	22609441784 ps
CPU time	333.37 seconds
Started	Apr 18 02:33:11 PM PDT 24
Finished	Apr 18 02:38:44 PM PDT 24
Peak memory	344548 kb
Host	smart-8265e63c-9eda-493e-80b5-fb0e653686fc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914805143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.2914805143
Directory	/workspace/16.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access.196772752
Short name	T404
Test name
Test status
Simulation time	890648704 ps
CPU time	92.98 seconds
Started	Apr 18 02:33:10 PM PDT 24
Finished	Apr 18 02:34:43 PM PDT 24
Peak memory	355536 kb
Host	smart-cc2f59ca-b7db-41e8-a745-0807c0a03cdd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196772752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s ram_ctrl_partial_access.196772752
Directory	/workspace/16.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3804644132
Short name	T815
Test name
Test status
Simulation time	49740462805 ps
CPU time	242.58 seconds
Started	Apr 18 02:33:15 PM PDT 24
Finished	Apr 18 02:37:18 PM PDT 24
Peak memory	203196 kb
Host	smart-f9d1a668-2433-436b-9778-43b062dbe780
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804644132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.3804644132
Directory	/workspace/16.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/16.sram_ctrl_ram_cfg.3426370372
Short name	T237
Test name
Test status
Simulation time	347144952 ps
CPU time	3.27 seconds
Started	Apr 18 02:33:21 PM PDT 24
Finished	Apr 18 02:33:25 PM PDT 24
Peak memory	203072 kb
Host	smart-5af5dc9e-4f75-4531-bd1a-09854cc478e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426370372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3426370372
Directory	/workspace/16.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/16.sram_ctrl_regwen.2030650667
Short name	T743
Test name
Test status
Simulation time	38540413904 ps
CPU time	821.45 seconds
Started	Apr 18 02:33:21 PM PDT 24
Finished	Apr 18 02:47:03 PM PDT 24
Peak memory	377884 kb
Host	smart-adf7d1de-cb41-4f3c-af7d-1331a56cf0c0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030650667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2030650667
Directory	/workspace/16.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/16.sram_ctrl_smoke.624277586
Short name	T241
Test name
Test status
Simulation time	3166557174 ps
CPU time	13.48 seconds
Started	Apr 18 02:33:10 PM PDT 24
Finished	Apr 18 02:33:24 PM PDT 24
Peak memory	202932 kb
Host	smart-ae4fce8a-00f6-47d3-90e0-f6d726c8a04c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624277586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.624277586
Directory	/workspace/16.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_all.502115589
Short name	T130
Test name
Test status
Simulation time	80256577990 ps
CPU time	2383.45 seconds
Started	Apr 18 02:33:26 PM PDT 24
Finished	Apr 18 03:13:10 PM PDT 24
Peak memory	380060 kb
Host	smart-5a1e250c-6e59-4412-8512-1dbe3892aed2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502115589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_stress_all.502115589
Directory	/workspace/16.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1440366733
Short name	T853
Test name
Test status
Simulation time	2477143433 ps
CPU time	125.64 seconds
Started	Apr 18 02:33:26 PM PDT 24
Finished	Apr 18 02:35:32 PM PDT 24
Peak memory	344304 kb
Host	smart-441c0e51-916e-4b19-8a2f-008aab5b5b17
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1440366733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1440366733
Directory	/workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.6480932
Short name	T242
Test name
Test status
Simulation time	8748465960 ps
CPU time	146.74 seconds
Started	Apr 18 02:33:09 PM PDT 24
Finished	Apr 18 02:35:36 PM PDT 24
Peak memory	203200 kb
Host	smart-bd70d48d-df15-4f61-84ae-9cd239107ab5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6480932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s ram_ctrl_stress_pipeline.6480932
Directory	/workspace/16.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.959663311
Short name	T143
Test name
Test status
Simulation time	3042746724 ps
CPU time	74.07 seconds
Started	Apr 18 02:33:15 PM PDT 24
Finished	Apr 18 02:34:30 PM PDT 24
Peak memory	339932 kb
Host	smart-9c55d3f5-92cb-4712-a153-d07718eeb707
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959663311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_throughput_w_partial_write.959663311
Directory	/workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.15909856
Short name	T388
Test name
Test status
Simulation time	81772750602 ps
CPU time	1793.54 seconds
Started	Apr 18 02:33:36 PM PDT 24
Finished	Apr 18 03:03:30 PM PDT 24
Peak memory	377956 kb
Host	smart-aa07a0d3-8b48-492a-87ad-c762646d9c5d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15909856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.sram_ctrl_access_during_key_req.15909856
Directory	/workspace/17.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/17.sram_ctrl_alert_test.3141392791
Short name	T403
Test name
Test status
Simulation time	34758426 ps
CPU time	0.6 seconds
Started	Apr 18 02:33:41 PM PDT 24
Finished	Apr 18 02:33:42 PM PDT 24
Peak memory	202644 kb
Host	smart-6f3fdfe5-dca0-419a-a58e-e454bebfec09
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141392791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.3141392791
Directory	/workspace/17.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.sram_ctrl_bijection.1614606380
Short name	T279
Test name
Test status
Simulation time	374028239733 ps
CPU time	1703.9 seconds
Started	Apr 18 02:33:31 PM PDT 24
Finished	Apr 18 03:01:55 PM PDT 24
Peak memory	203364 kb
Host	smart-f4fe83f0-5239-4541-9eb1-9eeec25fa5f3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614606380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .1614606380
Directory	/workspace/17.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/17.sram_ctrl_executable.3003341779
Short name	T744
Test name
Test status
Simulation time	49944057438 ps
CPU time	1009.74 seconds
Started	Apr 18 02:33:37 PM PDT 24
Finished	Apr 18 02:50:27 PM PDT 24
Peak memory	379580 kb
Host	smart-549227ad-2d93-4c94-b716-3acdb81479cf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003341779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.3003341779
Directory	/workspace/17.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/17.sram_ctrl_lc_escalation.2225018920
Short name	T866
Test name
Test status
Simulation time	19983865977 ps
CPU time	68.61 seconds
Started	Apr 18 02:33:30 PM PDT 24
Finished	Apr 18 02:34:39 PM PDT 24
Peak memory	211272 kb
Host	smart-aeebd69c-0322-4179-93c0-8a24d5a8f25b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225018920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.2225018920
Directory	/workspace/17.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/17.sram_ctrl_max_throughput.3428765097
Short name	T781
Test name
Test status
Simulation time	1486397913 ps
CPU time	126.7 seconds
Started	Apr 18 02:33:31 PM PDT 24
Finished	Apr 18 02:35:38 PM PDT 24
Peak memory	358456 kb
Host	smart-67339675-3ae6-44bd-82e8-266b25360aa8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428765097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.3428765097
Directory	/workspace/17.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3546030699
Short name	T43
Test name
Test status
Simulation time	2630509041 ps
CPU time	73.67 seconds
Started	Apr 18 02:33:36 PM PDT 24
Finished	Apr 18 02:34:50 PM PDT 24
Peak memory	211336 kb
Host	smart-48d03fcb-e7ac-4414-8bf6-63149c90f2e2
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546030699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.3546030699
Directory	/workspace/17.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_walk.1908853936
Short name	T195
Test name
Test status
Simulation time	4106812352 ps
CPU time	240.76 seconds
Started	Apr 18 02:33:37 PM PDT 24
Finished	Apr 18 02:37:38 PM PDT 24
Peak memory	203108 kb
Host	smart-19290ef5-cf63-4c16-8e84-36fbbbfc026a
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908853936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.1908853936
Directory	/workspace/17.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/17.sram_ctrl_multiple_keys.1178088919
Short name	T286
Test name
Test status
Simulation time	46830184714 ps
CPU time	710.67 seconds
Started	Apr 18 02:33:32 PM PDT 24
Finished	Apr 18 02:45:23 PM PDT 24
Peak memory	378200 kb
Host	smart-c64d5c86-2b80-4956-a06b-ad6dafb78b6a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178088919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.1178088919
Directory	/workspace/17.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access.1929235928
Short name	T37
Test name
Test status
Simulation time	3181165635 ps
CPU time	7.06 seconds
Started	Apr 18 02:33:31 PM PDT 24
Finished	Apr 18 02:33:38 PM PDT 24
Peak memory	202904 kb
Host	smart-3ccecc5c-34f5-4c1b-9202-513aec198cd0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929235928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.1929235928
Directory	/workspace/17.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_ram_cfg.1185057749
Short name	T817
Test name
Test status
Simulation time	351502178 ps
CPU time	3.37 seconds
Started	Apr 18 02:33:36 PM PDT 24
Finished	Apr 18 02:33:40 PM PDT 24
Peak memory	203060 kb
Host	smart-1a92b6c0-8d49-4fc8-a345-303c71805122
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185057749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1185057749
Directory	/workspace/17.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/17.sram_ctrl_regwen.1902071439
Short name	T538
Test name
Test status
Simulation time	23304813100 ps
CPU time	592.38 seconds
Started	Apr 18 02:33:35 PM PDT 24
Finished	Apr 18 02:43:28 PM PDT 24
Peak memory	379988 kb
Host	smart-eacb237a-f25e-41cc-b7fc-91ea8525e5c1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902071439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1902071439
Directory	/workspace/17.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/17.sram_ctrl_smoke.2437096213
Short name	T607
Test name
Test status
Simulation time	836047591 ps
CPU time	72.6 seconds
Started	Apr 18 02:33:25 PM PDT 24
Finished	Apr 18 02:34:38 PM PDT 24
Peak memory	326784 kb
Host	smart-0154567d-4079-4a25-a76f-ecb550f160df
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437096213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2437096213
Directory	/workspace/17.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all.1292835281
Short name	T609
Test name
Test status
Simulation time	468786512689 ps
CPU time	1854.4 seconds
Started	Apr 18 02:33:42 PM PDT 24
Finished	Apr 18 03:04:37 PM PDT 24
Peak memory	373908 kb
Host	smart-7f9d5509-b234-451a-b3b4-ea0a3fd8a682
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292835281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.1292835281
Directory	/workspace/17.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2754867535
Short name	T800
Test name
Test status
Simulation time	5241023473 ps
CPU time	51.31 seconds
Started	Apr 18 02:33:39 PM PDT 24
Finished	Apr 18 02:34:31 PM PDT 24
Peak memory	211348 kb
Host	smart-0f406a2e-eab6-41e5-8006-9f31afa8917a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2754867535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2754867535
Directory	/workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3938215888
Short name	T534
Test name
Test status
Simulation time	15937298385 ps
CPU time	262.58 seconds
Started	Apr 18 02:33:31 PM PDT 24
Finished	Apr 18 02:37:54 PM PDT 24
Peak memory	203172 kb
Host	smart-2a061f71-0fe8-4259-864f-d2f097b42820
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938215888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.3938215888
Directory	/workspace/17.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3692905890
Short name	T455
Test name
Test status
Simulation time	962487015 ps
CPU time	62.28 seconds
Started	Apr 18 02:33:31 PM PDT 24
Finished	Apr 18 02:34:33 PM PDT 24
Peak memory	348084 kb
Host	smart-56cdb393-87ae-4d82-8bb6-2c0b0a21d0ac
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692905890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.3692905890
Directory	/workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1482864001
Short name	T419
Test name
Test status
Simulation time	4219247277 ps
CPU time	179.51 seconds
Started	Apr 18 02:33:51 PM PDT 24
Finished	Apr 18 02:36:51 PM PDT 24
Peak memory	333148 kb
Host	smart-1d4139c1-9af6-4487-9424-84666ceec136
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482864001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.1482864001
Directory	/workspace/18.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/18.sram_ctrl_alert_test.3035568628
Short name	T344
Test name
Test status
Simulation time	16036027 ps
CPU time	0.64 seconds
Started	Apr 18 02:33:57 PM PDT 24
Finished	Apr 18 02:33:58 PM PDT 24
Peak memory	202824 kb
Host	smart-b9339372-b322-4644-b4f6-e4d58ef47e01
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035568628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3035568628
Directory	/workspace/18.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.sram_ctrl_bijection.1104492743
Short name	T489
Test name
Test status
Simulation time	48037142813 ps
CPU time	872.6 seconds
Started	Apr 18 02:33:41 PM PDT 24
Finished	Apr 18 02:48:14 PM PDT 24
Peak memory	203132 kb
Host	smart-e7b5e2df-a7a8-409e-b4ed-c863e0815239
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104492743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .1104492743
Directory	/workspace/18.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/18.sram_ctrl_executable.2491164811
Short name	T683
Test name
Test status
Simulation time	31497964188 ps
CPU time	436.23 seconds
Started	Apr 18 02:33:50 PM PDT 24
Finished	Apr 18 02:41:07 PM PDT 24
Peak memory	371784 kb
Host	smart-86522f56-3d1b-48bc-a527-e17a10ad8b83
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491164811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.2491164811
Directory	/workspace/18.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/18.sram_ctrl_lc_escalation.2259348864
Short name	T53
Test name
Test status
Simulation time	9308496816 ps
CPU time	52.22 seconds
Started	Apr 18 02:33:51 PM PDT 24
Finished	Apr 18 02:34:44 PM PDT 24
Peak memory	203168 kb
Host	smart-f6246db9-ea7c-4981-b7ed-2b4d29deeb0a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259348864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.2259348864
Directory	/workspace/18.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/18.sram_ctrl_max_throughput.2477589613
Short name	T490
Test name
Test status
Simulation time	723512481 ps
CPU time	27.93 seconds
Started	Apr 18 02:33:47 PM PDT 24
Finished	Apr 18 02:34:15 PM PDT 24
Peak memory	285132 kb
Host	smart-cdb4d248-46ca-4d7b-b102-47fc2d972a69
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477589613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.2477589613
Directory	/workspace/18.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2733497616
Short name	T87
Test name
Test status
Simulation time	5190458435 ps
CPU time	152.26 seconds
Started	Apr 18 02:33:56 PM PDT 24
Finished	Apr 18 02:36:29 PM PDT 24
Peak memory	211588 kb
Host	smart-42332a52-ef0b-460f-a0b3-e628db422a1d
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733497616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.2733497616
Directory	/workspace/18.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_walk.1359227518
Short name	T2
Test name
Test status
Simulation time	21518669857 ps
CPU time	162.29 seconds
Started	Apr 18 02:33:56 PM PDT 24
Finished	Apr 18 02:36:39 PM PDT 24
Peak memory	203552 kb
Host	smart-1ccfa512-3070-494f-97f9-56bbbe6e0b26
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359227518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.1359227518
Directory	/workspace/18.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/18.sram_ctrl_multiple_keys.1468198067
Short name	T446
Test name
Test status
Simulation time	34867367828 ps
CPU time	687.12 seconds
Started	Apr 18 02:33:42 PM PDT 24
Finished	Apr 18 02:45:10 PM PDT 24
Peak memory	377916 kb
Host	smart-4423c52c-d4fd-42d8-982f-c8a1da046197
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468198067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.1468198067
Directory	/workspace/18.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access.1015867903
Short name	T843
Test name
Test status
Simulation time	5803743112 ps
CPU time	22.01 seconds
Started	Apr 18 02:33:47 PM PDT 24
Finished	Apr 18 02:34:09 PM PDT 24
Peak memory	203392 kb
Host	smart-102b19b1-6ee1-4882-8f02-ca9ac79f5491
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015867903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.1015867903
Directory	/workspace/18.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.348529234
Short name	T754
Test name
Test status
Simulation time	6315260696 ps
CPU time	346.1 seconds
Started	Apr 18 02:33:46 PM PDT 24
Finished	Apr 18 02:39:32 PM PDT 24
Peak memory	203152 kb
Host	smart-de9f1abb-af14-4304-b3d4-b3fa7dc4387c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348529234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.sram_ctrl_partial_access_b2b.348529234
Directory	/workspace/18.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/18.sram_ctrl_ram_cfg.307725210
Short name	T572
Test name
Test status
Simulation time	1410955920 ps
CPU time	3.66 seconds
Started	Apr 18 02:33:55 PM PDT 24
Finished	Apr 18 02:33:59 PM PDT 24
Peak memory	203140 kb
Host	smart-482a606e-e976-4979-be5f-6b5bb7d38817
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307725210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.307725210
Directory	/workspace/18.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/18.sram_ctrl_regwen.1966303999
Short name	T391
Test name
Test status
Simulation time	30437229235 ps
CPU time	661.92 seconds
Started	Apr 18 02:33:58 PM PDT 24
Finished	Apr 18 02:45:00 PM PDT 24
Peak memory	375840 kb
Host	smart-230e0d57-fc11-41ac-9a3e-7ae2e5fe5077
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966303999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1966303999
Directory	/workspace/18.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/18.sram_ctrl_smoke.4188782317
Short name	T218
Test name
Test status
Simulation time	1649969390 ps
CPU time	46.29 seconds
Started	Apr 18 02:33:39 PM PDT 24
Finished	Apr 18 02:34:26 PM PDT 24
Peak memory	306764 kb
Host	smart-bae1ef16-4800-421b-b20d-c315f737f835
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188782317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.4188782317
Directory	/workspace/18.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all.2296381142
Short name	T169
Test name
Test status
Simulation time	37288994227 ps
CPU time	3934.6 seconds
Started	Apr 18 02:33:57 PM PDT 24
Finished	Apr 18 03:39:33 PM PDT 24
Peak memory	383072 kb
Host	smart-38cfaddf-3f36-49e3-a371-ee297baa50b8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296381142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.2296381142
Directory	/workspace/18.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2653106196
Short name	T47
Test name
Test status
Simulation time	647666879 ps
CPU time	6.96 seconds
Started	Apr 18 02:33:57 PM PDT 24
Finished	Apr 18 02:34:04 PM PDT 24
Peak memory	211304 kb
Host	smart-97b644d4-8b9f-4833-8f62-740037df08c7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2653106196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2653106196
Directory	/workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.2485743178
Short name	T12
Test name
Test status
Simulation time	17956026080 ps
CPU time	252.01 seconds
Started	Apr 18 02:33:47 PM PDT 24
Finished	Apr 18 02:37:59 PM PDT 24
Peak memory	203132 kb
Host	smart-4eafe8f1-8a5b-4eba-9df8-78511ae29bfe
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485743178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.2485743178
Directory	/workspace/18.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.459890245
Short name	T11
Test name
Test status
Simulation time	1509754111 ps
CPU time	29.98 seconds
Started	Apr 18 02:33:53 PM PDT 24
Finished	Apr 18 02:34:24 PM PDT 24
Peak memory	276860 kb
Host	smart-00303a5a-4285-4e0b-b987-3b3edfdb3082
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459890245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.459890245
Directory	/workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.1310977754
Short name	T270
Test name
Test status
Simulation time	11622804062 ps
CPU time	785.16 seconds
Started	Apr 18 02:34:15 PM PDT 24
Finished	Apr 18 02:47:21 PM PDT 24
Peak memory	375952 kb
Host	smart-abbcf65a-4695-48e3-82a0-6b9350b7b16d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310977754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.1310977754
Directory	/workspace/19.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/19.sram_ctrl_alert_test.3527527299
Short name	T457
Test name
Test status
Simulation time	18741555 ps
CPU time	0.63 seconds
Started	Apr 18 02:34:21 PM PDT 24
Finished	Apr 18 02:34:22 PM PDT 24
Peak memory	202788 kb
Host	smart-a48f5b93-cbc6-4728-9f5a-89ceeafdd7c8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527527299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3527527299
Directory	/workspace/19.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.sram_ctrl_bijection.2695485383
Short name	T472
Test name
Test status
Simulation time	574028791695 ps
CPU time	2601.88 seconds
Started	Apr 18 02:34:06 PM PDT 24
Finished	Apr 18 03:17:28 PM PDT 24
Peak memory	203556 kb
Host	smart-eedc5bdc-2973-49fc-b68b-92f0a911f379
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695485383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .2695485383
Directory	/workspace/19.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/19.sram_ctrl_lc_escalation.1271879106
Short name	T410
Test name
Test status
Simulation time	26762503012 ps
CPU time	42.3 seconds
Started	Apr 18 02:34:11 PM PDT 24
Finished	Apr 18 02:34:53 PM PDT 24
Peak memory	211276 kb
Host	smart-f3421ce9-3ad0-47e9-8c41-da11a4644b50
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271879106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.1271879106
Directory	/workspace/19.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/19.sram_ctrl_max_throughput.615629226
Short name	T834
Test name
Test status
Simulation time	780062251 ps
CPU time	54.67 seconds
Started	Apr 18 02:34:09 PM PDT 24
Finished	Apr 18 02:35:05 PM PDT 24
Peak memory	319508 kb
Host	smart-da27fc07-ace7-4e00-8cf5-c4828d4d242c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615629226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.sram_ctrl_max_throughput.615629226
Directory	/workspace/19.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2854536050
Short name	T438
Test name
Test status
Simulation time	29010438353 ps
CPU time	143.34 seconds
Started	Apr 18 02:34:15 PM PDT 24
Finished	Apr 18 02:36:39 PM PDT 24
Peak memory	211352 kb
Host	smart-59d8612d-1ffd-4b51-aa13-e92f28ac67f3
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854536050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.2854536050
Directory	/workspace/19.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_walk.2250468988
Short name	T712
Test name
Test status
Simulation time	28716968395 ps
CPU time	285.04 seconds
Started	Apr 18 02:34:14 PM PDT 24
Finished	Apr 18 02:39:00 PM PDT 24
Peak memory	204156 kb
Host	smart-36128288-7a0d-41fc-9a38-ebff48d722fe
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250468988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.2250468988
Directory	/workspace/19.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/19.sram_ctrl_multiple_keys.2196612471
Short name	T67
Test name
Test status
Simulation time	53525958028 ps
CPU time	1535.32 seconds
Started	Apr 18 02:34:04 PM PDT 24
Finished	Apr 18 02:59:40 PM PDT 24
Peak memory	372848 kb
Host	smart-99e09db4-ce0c-47ee-a786-079fce09d0bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196612471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.2196612471
Directory	/workspace/19.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access.1711863563
Short name	T792
Test name
Test status
Simulation time	5637531394 ps
CPU time	174.83 seconds
Started	Apr 18 02:34:03 PM PDT 24
Finished	Apr 18 02:36:58 PM PDT 24
Peak memory	367700 kb
Host	smart-32559082-19df-4fb2-9fd1-ec695d3149a3
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711863563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.1711863563
Directory	/workspace/19.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.348054805
Short name	T301
Test name
Test status
Simulation time	8801346765 ps
CPU time	197.67 seconds
Started	Apr 18 02:34:02 PM PDT 24
Finished	Apr 18 02:37:20 PM PDT 24
Peak memory	203196 kb
Host	smart-a67b1284-3573-4760-9035-c5c8cfae989b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348054805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.sram_ctrl_partial_access_b2b.348054805
Directory	/workspace/19.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/19.sram_ctrl_ram_cfg.3952015218
Short name	T308
Test name
Test status
Simulation time	1410633744 ps
CPU time	3.43 seconds
Started	Apr 18 02:34:16 PM PDT 24
Finished	Apr 18 02:34:20 PM PDT 24
Peak memory	203016 kb
Host	smart-c6f8aac6-c543-424a-a0c2-5b053319dabd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952015218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3952015218
Directory	/workspace/19.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/19.sram_ctrl_regwen.3273493405
Short name	T563
Test name
Test status
Simulation time	35754323421 ps
CPU time	1157.66 seconds
Started	Apr 18 02:34:15 PM PDT 24
Finished	Apr 18 02:53:33 PM PDT 24
Peak memory	375884 kb
Host	smart-1374e795-367f-49a0-a315-5ec1cf65595c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273493405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3273493405
Directory	/workspace/19.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/19.sram_ctrl_smoke.886310265
Short name	T718
Test name
Test status
Simulation time	1887022949 ps
CPU time	102.13 seconds
Started	Apr 18 02:33:55 PM PDT 24
Finished	Apr 18 02:35:38 PM PDT 24
Peak memory	352200 kb
Host	smart-186305aa-3f03-4f5a-b8d6-78b5c5c79ac7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886310265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.886310265
Directory	/workspace/19.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all.660168783
Short name	T495
Test name
Test status
Simulation time	93616857166 ps
CPU time	6418.88 seconds
Started	Apr 18 02:34:20 PM PDT 24
Finished	Apr 18 04:21:19 PM PDT 24
Peak memory	380020 kb
Host	smart-f8c9b0eb-b999-4443-8312-391d35ce68f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660168783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_stress_all.660168783
Directory	/workspace/19.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3629878624
Short name	T723
Test name
Test status
Simulation time	967437704 ps
CPU time	27.06 seconds
Started	Apr 18 02:34:23 PM PDT 24
Finished	Apr 18 02:34:50 PM PDT 24
Peak memory	212516 kb
Host	smart-b3f9af24-770f-49c4-bce4-969ed6689166
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3629878624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3629878624
Directory	/workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1517321878
Short name	T637
Test name
Test status
Simulation time	7985176700 ps
CPU time	235.35 seconds
Started	Apr 18 02:34:03 PM PDT 24
Finished	Apr 18 02:37:58 PM PDT 24
Peak memory	203140 kb
Host	smart-2b8731f2-f4fc-478c-8cbe-47e1d487d3b3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517321878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.1517321878
Directory	/workspace/19.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.607093763
Short name	T442
Test name
Test status
Simulation time	819837979 ps
CPU time	105.98 seconds
Started	Apr 18 02:34:11 PM PDT 24
Finished	Apr 18 02:35:58 PM PDT 24
Peak memory	369604 kb
Host	smart-79c06099-b8ec-4239-9e87-1b8abc0b4a06
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607093763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.607093763
Directory	/workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/2.sram_ctrl_access_during_key_req.3275897273
Short name	T635
Test name
Test status
Simulation time	4629004276 ps
CPU time	127.89 seconds
Started	Apr 18 02:30:41 PM PDT 24
Finished	Apr 18 02:32:50 PM PDT 24
Peak memory	318672 kb
Host	smart-bfa1cef7-8690-4253-b690-50023302ef1d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275897273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.3275897273
Directory	/workspace/2.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/2.sram_ctrl_alert_test.3619184097
Short name	T801
Test name
Test status
Simulation time	13145392 ps
CPU time	0.62 seconds
Started	Apr 18 02:30:51 PM PDT 24
Finished	Apr 18 02:30:52 PM PDT 24
Peak memory	202616 kb
Host	smart-7ee1555b-ddcb-4914-9687-1004419593c5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619184097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3619184097
Directory	/workspace/2.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.sram_ctrl_bijection.2017705195
Short name	T220
Test name
Test status
Simulation time	90489460283 ps
CPU time	1589.04 seconds
Started	Apr 18 02:30:42 PM PDT 24
Finished	Apr 18 02:57:12 PM PDT 24
Peak memory	203352 kb
Host	smart-17ac95db-6380-49ac-93b1-70d3ca9da5cc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017705195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 2017705195
Directory	/workspace/2.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/2.sram_ctrl_executable.4009121538
Short name	T264
Test name
Test status
Simulation time	61248117186 ps
CPU time	555.93 seconds
Started	Apr 18 02:30:51 PM PDT 24
Finished	Apr 18 02:40:07 PM PDT 24
Peak memory	379004 kb
Host	smart-c044a843-589c-43f7-8181-3ac9da397e31
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009121538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.4009121538
Directory	/workspace/2.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/2.sram_ctrl_lc_escalation.3743049791
Short name	T725
Test name
Test status
Simulation time	5561992342 ps
CPU time	8.85 seconds
Started	Apr 18 02:30:42 PM PDT 24
Finished	Apr 18 02:30:51 PM PDT 24
Peak memory	211280 kb
Host	smart-c48cb4b8-6636-44ab-b7ed-3039e419dcca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743049791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.3743049791
Directory	/workspace/2.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/2.sram_ctrl_max_throughput.2426157716
Short name	T476
Test name
Test status
Simulation time	2863594584 ps
CPU time	26.72 seconds
Started	Apr 18 02:30:42 PM PDT 24
Finished	Apr 18 02:31:09 PM PDT 24
Peak memory	279516 kb
Host	smart-8a562cfd-338b-4e2e-ac93-47474c2af0d9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426157716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.2426157716
Directory	/workspace/2.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2798726665
Short name	T385
Test name
Test status
Simulation time	4788511771 ps
CPU time	74.08 seconds
Started	Apr 18 02:30:51 PM PDT 24
Finished	Apr 18 02:32:05 PM PDT 24
Peak memory	211352 kb
Host	smart-1375f255-404e-48f8-8d2d-5a7190ae5f23
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798726665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.2798726665
Directory	/workspace/2.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_walk.366267599
Short name	T337
Test name
Test status
Simulation time	6957911487 ps
CPU time	149.24 seconds
Started	Apr 18 02:30:52 PM PDT 24
Finished	Apr 18 02:33:22 PM PDT 24
Peak memory	203652 kb
Host	smart-1a641767-ac17-471e-bc55-6a0fdb43f437
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366267599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ mem_walk.366267599
Directory	/workspace/2.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/2.sram_ctrl_multiple_keys.4129358088
Short name	T913
Test name
Test status
Simulation time	36784690824 ps
CPU time	1018.26 seconds
Started	Apr 18 02:30:41 PM PDT 24
Finished	Apr 18 02:47:40 PM PDT 24
Peak memory	376724 kb
Host	smart-5536f478-72cd-4602-a502-173b03821c06
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129358088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.4129358088
Directory	/workspace/2.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access.2215407660
Short name	T704
Test name
Test status
Simulation time	484548598 ps
CPU time	5.5 seconds
Started	Apr 18 02:30:41 PM PDT 24
Finished	Apr 18 02:30:48 PM PDT 24
Peak memory	203072 kb
Host	smart-0ee51721-430e-41e7-92c8-213b75f0f584
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215407660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.2215407660
Directory	/workspace/2.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3537210307
Short name	T899
Test name
Test status
Simulation time	34382879593 ps
CPU time	393.43 seconds
Started	Apr 18 02:30:50 PM PDT 24
Finished	Apr 18 02:37:23 PM PDT 24
Peak memory	203132 kb
Host	smart-a2a9f0f9-981d-4076-850e-7c06e25c2485
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537210307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.3537210307
Directory	/workspace/2.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/2.sram_ctrl_ram_cfg.1813369372
Short name	T167
Test name
Test status
Simulation time	1604622643 ps
CPU time	3.5 seconds
Started	Apr 18 02:30:51 PM PDT 24
Finished	Apr 18 02:30:55 PM PDT 24
Peak memory	203096 kb
Host	smart-fccc14fc-880f-41ec-abec-b0e1b7b7af5a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813369372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1813369372
Directory	/workspace/2.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/2.sram_ctrl_regwen.1441456168
Short name	T857
Test name
Test status
Simulation time	7806007434 ps
CPU time	437.42 seconds
Started	Apr 18 02:30:53 PM PDT 24
Finished	Apr 18 02:38:11 PM PDT 24
Peak memory	376756 kb
Host	smart-9b2d63ef-e79a-4b3c-abbc-ea9bdf91ee59
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441456168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1441456168
Directory	/workspace/2.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/2.sram_ctrl_smoke.450060357
Short name	T803
Test name
Test status
Simulation time	1855927832 ps
CPU time	115.47 seconds
Started	Apr 18 02:30:41 PM PDT 24
Finished	Apr 18 02:32:37 PM PDT 24
Peak memory	360908 kb
Host	smart-0f5357ba-3abe-48d3-9440-cd094ef3f664
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450060357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.450060357
Directory	/workspace/2.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all.157914757
Short name	T456
Test name
Test status
Simulation time	796372347809 ps
CPU time	5170.76 seconds
Started	Apr 18 02:30:53 PM PDT 24
Finished	Apr 18 03:57:05 PM PDT 24
Peak memory	380108 kb
Host	smart-84c7418c-1eb4-4349-857b-4d1d4767aed4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157914757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_stress_all.157914757
Directory	/workspace/2.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2435456179
Short name	T52
Test name
Test status
Simulation time	5628325096 ps
CPU time	46.47 seconds
Started	Apr 18 02:30:50 PM PDT 24
Finished	Apr 18 02:31:37 PM PDT 24
Peak memory	211380 kb
Host	smart-f83c59a2-06be-4ca9-9af7-3f75d6fb6012
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2435456179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2435456179
Directory	/workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_pipeline.4173929976
Short name	T463
Test name
Test status
Simulation time	4725763529 ps
CPU time	278.79 seconds
Started	Apr 18 02:30:40 PM PDT 24
Finished	Apr 18 02:35:20 PM PDT 24
Peak memory	203092 kb
Host	smart-cc1a65c3-a4c7-4872-9f04-831439949df3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173929976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.4173929976
Directory	/workspace/2.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.515151614
Short name	T306
Test name
Test status
Simulation time	1137264846 ps
CPU time	31.31 seconds
Started	Apr 18 02:30:41 PM PDT 24
Finished	Apr 18 02:31:13 PM PDT 24
Peak memory	288912 kb
Host	smart-5af516e7-75ea-4eb2-a524-7cd406adc430
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515151614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.515151614
Directory	/workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2577150972
Short name	T525
Test name
Test status
Simulation time	44409649919 ps
CPU time	862.96 seconds
Started	Apr 18 02:34:35 PM PDT 24
Finished	Apr 18 02:48:59 PM PDT 24
Peak memory	375916 kb
Host	smart-0a1d2c4e-e885-4ce1-8088-056a0882b286
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577150972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.2577150972
Directory	/workspace/20.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/20.sram_ctrl_alert_test.631839461
Short name	T829
Test name
Test status
Simulation time	15119642 ps
CPU time	0.63 seconds
Started	Apr 18 02:34:46 PM PDT 24
Finished	Apr 18 02:34:47 PM PDT 24
Peak memory	202288 kb
Host	smart-e8d4f2b7-83ba-45b0-a104-50fa6f6fa22e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631839461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.631839461
Directory	/workspace/20.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.sram_ctrl_bijection.1030464520
Short name	T175
Test name
Test status
Simulation time	987952295825 ps
CPU time	1181.61 seconds
Started	Apr 18 02:34:19 PM PDT 24
Finished	Apr 18 02:54:01 PM PDT 24
Peak memory	203304 kb
Host	smart-0e2c7d50-5e22-4ef1-9cdf-f9f87f0ab05c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030464520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .1030464520
Directory	/workspace/20.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/20.sram_ctrl_executable.3432598719
Short name	T379
Test name
Test status
Simulation time	5975813830 ps
CPU time	37.92 seconds
Started	Apr 18 02:34:35 PM PDT 24
Finished	Apr 18 02:35:14 PM PDT 24
Peak memory	203156 kb
Host	smart-af3a5e30-19dd-4470-acb7-fea7814cb8e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432598719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.3432598719
Directory	/workspace/20.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/20.sram_ctrl_lc_escalation.1234417549
Short name	T730
Test name
Test status
Simulation time	17917537030 ps
CPU time	27.42 seconds
Started	Apr 18 02:34:31 PM PDT 24
Finished	Apr 18 02:34:59 PM PDT 24
Peak memory	203136 kb
Host	smart-a857d8a9-ab89-4a85-af4e-27d7aa03f837
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234417549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.1234417549
Directory	/workspace/20.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/20.sram_ctrl_max_throughput.2622382034
Short name	T808
Test name
Test status
Simulation time	2989457640 ps
CPU time	40.35 seconds
Started	Apr 18 02:34:32 PM PDT 24
Finished	Apr 18 02:35:13 PM PDT 24
Peak memory	285792 kb
Host	smart-9f708c7b-f83f-4ee4-9775-94ca9e711c7b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622382034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.2622382034
Directory	/workspace/20.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2749196027
Short name	T901
Test name
Test status
Simulation time	32625164576 ps
CPU time	85.78 seconds
Started	Apr 18 02:34:45 PM PDT 24
Finished	Apr 18 02:36:11 PM PDT 24
Peak memory	211292 kb
Host	smart-02c27364-2479-4fcc-bc9c-7d08bc2ce083
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749196027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.2749196027
Directory	/workspace/20.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_walk.1218880163
Short name	T854
Test name
Test status
Simulation time	43776896117 ps
CPU time	264.24 seconds
Started	Apr 18 02:34:45 PM PDT 24
Finished	Apr 18 02:39:10 PM PDT 24
Peak memory	203176 kb
Host	smart-b54557b4-c5f6-40fa-80f0-a0a62a85a729
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218880163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.1218880163
Directory	/workspace/20.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/20.sram_ctrl_multiple_keys.1154229665
Short name	T429
Test name
Test status
Simulation time	15298147947 ps
CPU time	656 seconds
Started	Apr 18 02:34:18 PM PDT 24
Finished	Apr 18 02:45:15 PM PDT 24
Peak memory	378164 kb
Host	smart-81c8ea31-b6fd-4e01-bb69-016b7024e826
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154229665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.1154229665
Directory	/workspace/20.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access.1685208417
Short name	T919
Test name
Test status
Simulation time	1934253384 ps
CPU time	23.49 seconds
Started	Apr 18 02:34:24 PM PDT 24
Finished	Apr 18 02:34:48 PM PDT 24
Peak memory	203044 kb
Host	smart-c902c44a-c322-4311-af20-dc1bc45d78d5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685208417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.1685208417
Directory	/workspace/20.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3381408031
Short name	T500
Test name
Test status
Simulation time	7052205730 ps
CPU time	262 seconds
Started	Apr 18 02:34:33 PM PDT 24
Finished	Apr 18 02:38:55 PM PDT 24
Peak memory	203200 kb
Host	smart-eb186c5b-acc8-47ef-a17d-e18de65e49fa
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381408031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.3381408031
Directory	/workspace/20.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/20.sram_ctrl_ram_cfg.3003253962
Short name	T34
Test name
Test status
Simulation time	1539931289 ps
CPU time	3.24 seconds
Started	Apr 18 02:34:39 PM PDT 24
Finished	Apr 18 02:34:43 PM PDT 24
Peak memory	203064 kb
Host	smart-3481ff5c-c29b-4fa9-a299-0413d4c21385
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003253962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3003253962
Directory	/workspace/20.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/20.sram_ctrl_regwen.2302077832
Short name	T934
Test name
Test status
Simulation time	7849382417 ps
CPU time	703.56 seconds
Started	Apr 18 02:34:35 PM PDT 24
Finished	Apr 18 02:46:20 PM PDT 24
Peak memory	377952 kb
Host	smart-32603d12-1bbb-47fd-b7e7-fc3c6fd2ca48
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302077832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2302077832
Directory	/workspace/20.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/20.sram_ctrl_smoke.3170658473
Short name	T540
Test name
Test status
Simulation time	1159113034 ps
CPU time	16.53 seconds
Started	Apr 18 02:34:19 PM PDT 24
Finished	Apr 18 02:34:35 PM PDT 24
Peak memory	202984 kb
Host	smart-586eb268-ed7d-4837-9650-9e5f572946d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170658473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3170658473
Directory	/workspace/20.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all.3626820506
Short name	T915
Test name
Test status
Simulation time	40190826075 ps
CPU time	3039.16 seconds
Started	Apr 18 02:34:47 PM PDT 24
Finished	Apr 18 03:25:27 PM PDT 24
Peak memory	377112 kb
Host	smart-c3d15e58-211b-43c3-947c-8279debeb0d9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626820506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.3626820506
Directory	/workspace/20.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3203286948
Short name	T32
Test name
Test status
Simulation time	4213748682 ps
CPU time	83.13 seconds
Started	Apr 18 02:34:48 PM PDT 24
Finished	Apr 18 02:36:11 PM PDT 24
Peak memory	311436 kb
Host	smart-06269626-e2bc-4c72-8729-8e98a30f3f2c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3203286948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3203286948
Directory	/workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_pipeline.4282979296
Short name	T92
Test name
Test status
Simulation time	4728185131 ps
CPU time	287.59 seconds
Started	Apr 18 02:34:26 PM PDT 24
Finished	Apr 18 02:39:14 PM PDT 24
Peak memory	203180 kb
Host	smart-e0327545-670f-490c-8a6f-6b3efcd1689a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282979296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.4282979296
Directory	/workspace/20.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2652324359
Short name	T144
Test name
Test status
Simulation time	1573623796 ps
CPU time	76.16 seconds
Started	Apr 18 02:34:28 PM PDT 24
Finished	Apr 18 02:35:45 PM PDT 24
Peak memory	329684 kb
Host	smart-47e71408-29f0-4432-b141-cab61a6f570e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652324359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.2652324359
Directory	/workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/21.sram_ctrl_access_during_key_req.558844174
Short name	T703
Test name
Test status
Simulation time	6208808884 ps
CPU time	150.44 seconds
Started	Apr 18 02:34:57 PM PDT 24
Finished	Apr 18 02:37:28 PM PDT 24
Peak memory	361748 kb
Host	smart-90b9b61e-09e1-4794-8724-32d799c6fcec
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558844174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 21.sram_ctrl_access_during_key_req.558844174
Directory	/workspace/21.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/21.sram_ctrl_alert_test.2613691466
Short name	T302
Test name
Test status
Simulation time	72936219 ps
CPU time	0.59 seconds
Started	Apr 18 02:35:14 PM PDT 24
Finished	Apr 18 02:35:15 PM PDT 24
Peak memory	202704 kb
Host	smart-fc3e5634-41d8-40be-afac-76f353c57b36
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613691466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2613691466
Directory	/workspace/21.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.sram_ctrl_bijection.2521086153
Short name	T131
Test name
Test status
Simulation time	61927365987 ps
CPU time	2018.73 seconds
Started	Apr 18 02:34:55 PM PDT 24
Finished	Apr 18 03:08:35 PM PDT 24
Peak memory	203400 kb
Host	smart-800a6dc8-d72c-4050-89b2-0fdf5f43a052
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521086153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .2521086153
Directory	/workspace/21.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/21.sram_ctrl_executable.841398815
Short name	T634
Test name
Test status
Simulation time	227046598586 ps
CPU time	1288.24 seconds
Started	Apr 18 02:35:01 PM PDT 24
Finished	Apr 18 02:56:30 PM PDT 24
Peak memory	377952 kb
Host	smart-01145208-4d41-4d23-b1ed-fe343d13d125
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841398815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executabl e.841398815
Directory	/workspace/21.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/21.sram_ctrl_lc_escalation.228293299
Short name	T155
Test name
Test status
Simulation time	28570591433 ps
CPU time	53.73 seconds
Started	Apr 18 02:34:56 PM PDT 24
Finished	Apr 18 02:35:50 PM PDT 24
Peak memory	203116 kb
Host	smart-40f65aca-d505-4618-a559-fcd42f98e78e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228293299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esc alation.228293299
Directory	/workspace/21.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/21.sram_ctrl_max_throughput.2577096541
Short name	T633
Test name
Test status
Simulation time	1491614026 ps
CPU time	104.52 seconds
Started	Apr 18 02:34:57 PM PDT 24
Finished	Apr 18 02:36:42 PM PDT 24
Peak memory	366568 kb
Host	smart-2dd1b224-8427-405e-ba62-0f717abbb929
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577096541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.2577096541
Directory	/workspace/21.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.3849546395
Short name	T750
Test name
Test status
Simulation time	5204365449 ps
CPU time	156.83 seconds
Started	Apr 18 02:35:06 PM PDT 24
Finished	Apr 18 02:37:43 PM PDT 24
Peak memory	211308 kb
Host	smart-5f148189-e2a8-4986-80d3-3e3f7ff4699d
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849546395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.3849546395
Directory	/workspace/21.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_walk.3463086868
Short name	T15
Test name
Test status
Simulation time	89792195997 ps
CPU time	306.62 seconds
Started	Apr 18 02:35:06 PM PDT 24
Finished	Apr 18 02:40:12 PM PDT 24
Peak memory	203252 kb
Host	smart-ea00dca0-e27d-462e-8073-3640a158922c
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463086868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.3463086868
Directory	/workspace/21.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/21.sram_ctrl_multiple_keys.1078648592
Short name	T481
Test name
Test status
Simulation time	9770498693 ps
CPU time	142.58 seconds
Started	Apr 18 02:34:52 PM PDT 24
Finished	Apr 18 02:37:15 PM PDT 24
Peak memory	377624 kb
Host	smart-cb8049b1-3c52-4276-b8d6-6cd570eb5e95
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078648592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.1078648592
Directory	/workspace/21.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access.846186257
Short name	T751
Test name
Test status
Simulation time	4225407307 ps
CPU time	34.55 seconds
Started	Apr 18 02:34:55 PM PDT 24
Finished	Apr 18 02:35:30 PM PDT 24
Peak memory	286600 kb
Host	smart-4f5d9a39-ac58-4ae3-9b50-0f57b7b53fc0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846186257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.s ram_ctrl_partial_access.846186257
Directory	/workspace/21.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3241227373
Short name	T682
Test name
Test status
Simulation time	4082112892 ps
CPU time	243.17 seconds
Started	Apr 18 02:34:55 PM PDT 24
Finished	Apr 18 02:38:59 PM PDT 24
Peak memory	203132 kb
Host	smart-45a380f7-a2d2-4c0c-898d-c27d595270d0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241227373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.3241227373
Directory	/workspace/21.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/21.sram_ctrl_ram_cfg.3708428694
Short name	T752
Test name
Test status
Simulation time	347000615 ps
CPU time	3.39 seconds
Started	Apr 18 02:35:07 PM PDT 24
Finished	Apr 18 02:35:11 PM PDT 24
Peak memory	203044 kb
Host	smart-ee97906f-d326-4a3c-a801-d808b799cd11
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708428694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3708428694
Directory	/workspace/21.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/21.sram_ctrl_regwen.3161899794
Short name	T674
Test name
Test status
Simulation time	5681146716 ps
CPU time	201.08 seconds
Started	Apr 18 02:35:05 PM PDT 24
Finished	Apr 18 02:38:26 PM PDT 24
Peak memory	374844 kb
Host	smart-e8d6d69e-1400-42f4-a52a-325efe875b11
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161899794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3161899794
Directory	/workspace/21.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/21.sram_ctrl_smoke.1281919721
Short name	T543
Test name
Test status
Simulation time	1130814082 ps
CPU time	65.05 seconds
Started	Apr 18 02:34:51 PM PDT 24
Finished	Apr 18 02:35:56 PM PDT 24
Peak memory	322636 kb
Host	smart-f2e67cac-4e19-4e91-a053-17e835631a2d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281919721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1281919721
Directory	/workspace/21.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all.4054342598
Short name	T715
Test name
Test status
Simulation time	317418480752 ps
CPU time	5260.43 seconds
Started	Apr 18 02:35:10 PM PDT 24
Finished	Apr 18 04:02:52 PM PDT 24
Peak memory	380052 kb
Host	smart-a44ad92d-6b7f-4fb3-a767-c21aef165532
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054342598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.4054342598
Directory	/workspace/21.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.412941620
Short name	T731
Test name
Test status
Simulation time	4701874396 ps
CPU time	66.06 seconds
Started	Apr 18 02:35:13 PM PDT 24
Finished	Apr 18 02:36:20 PM PDT 24
Peak memory	211404 kb
Host	smart-1116f176-e3fa-461d-966b-dad217b9f700
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=412941620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.412941620
Directory	/workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1600600667
Short name	T895
Test name
Test status
Simulation time	14289443258 ps
CPU time	220.5 seconds
Started	Apr 18 02:34:56 PM PDT 24
Finished	Apr 18 02:38:37 PM PDT 24
Peak memory	203152 kb
Host	smart-b1e81420-e0f1-4ffd-8a51-fb9538dfc902
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600600667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.1600600667
Directory	/workspace/21.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1181237678
Short name	T146
Test name
Test status
Simulation time	3117102313 ps
CPU time	53.9 seconds
Started	Apr 18 02:34:57 PM PDT 24
Finished	Apr 18 02:35:51 PM PDT 24
Peak memory	317496 kb
Host	smart-11a19b01-328d-40aa-b4e0-cb1b82cd0347
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181237678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.1181237678
Directory	/workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/22.sram_ctrl_access_during_key_req.3452290867
Short name	T691
Test name
Test status
Simulation time	10633337260 ps
CPU time	830.04 seconds
Started	Apr 18 02:35:16 PM PDT 24
Finished	Apr 18 02:49:07 PM PDT 24
Peak memory	378936 kb
Host	smart-4f6a2381-b486-44f1-aba7-ba8b76976285
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452290867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.3452290867
Directory	/workspace/22.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/22.sram_ctrl_alert_test.843727645
Short name	T329
Test name
Test status
Simulation time	23639114 ps
CPU time	0.65 seconds
Started	Apr 18 02:35:28 PM PDT 24
Finished	Apr 18 02:35:29 PM PDT 24
Peak memory	202796 kb
Host	smart-df931ab0-ce88-4312-ba79-f8a011997e53
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843727645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.843727645
Directory	/workspace/22.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.sram_ctrl_bijection.615535518
Short name	T721
Test name
Test status
Simulation time	15069313597 ps
CPU time	991.44 seconds
Started	Apr 18 02:35:11 PM PDT 24
Finished	Apr 18 02:51:43 PM PDT 24
Peak memory	203120 kb
Host	smart-494b5395-6884-48aa-a0f6-2f340bb5853d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615535518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection. 615535518
Directory	/workspace/22.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/22.sram_ctrl_executable.3502616368
Short name	T421
Test name
Test status
Simulation time	33716596505 ps
CPU time	812.85 seconds
Started	Apr 18 02:35:19 PM PDT 24
Finished	Apr 18 02:48:52 PM PDT 24
Peak memory	378952 kb
Host	smart-b7f146be-3236-473a-a740-87e2bdb1048e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502616368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.3502616368
Directory	/workspace/22.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/22.sram_ctrl_lc_escalation.3400871323
Short name	T661
Test name
Test status
Simulation time	12667319407 ps
CPU time	64.37 seconds
Started	Apr 18 02:35:16 PM PDT 24
Finished	Apr 18 02:36:20 PM PDT 24
Peak memory	203108 kb
Host	smart-0227e988-7fe0-4f66-b4da-a5554e9c3d10
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400871323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.3400871323
Directory	/workspace/22.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/22.sram_ctrl_max_throughput.3358103408
Short name	T571
Test name
Test status
Simulation time	770552472 ps
CPU time	151.95 seconds
Started	Apr 18 02:35:15 PM PDT 24
Finished	Apr 18 02:37:48 PM PDT 24
Peak memory	369816 kb
Host	smart-53bda6a3-df07-425e-9841-946e000dada2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358103408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.3358103408
Directory	/workspace/22.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3257019637
Short name	T533
Test name
Test status
Simulation time	1620609802 ps
CPU time	118.05 seconds
Started	Apr 18 02:35:25 PM PDT 24
Finished	Apr 18 02:37:23 PM PDT 24
Peak memory	211216 kb
Host	smart-f91e742e-7742-461a-9a96-8344f01528c6
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257019637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.3257019637
Directory	/workspace/22.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_walk.172267951
Short name	T313
Test name
Test status
Simulation time	18660763112 ps
CPU time	320.25 seconds
Started	Apr 18 02:35:20 PM PDT 24
Finished	Apr 18 02:40:40 PM PDT 24
Peak memory	203760 kb
Host	smart-6fa88421-5c1d-4599-9345-d007e6517b17
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172267951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl _mem_walk.172267951
Directory	/workspace/22.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/22.sram_ctrl_multiple_keys.3023723164
Short name	T807
Test name
Test status
Simulation time	16711649414 ps
CPU time	948.79 seconds
Started	Apr 18 02:35:10 PM PDT 24
Finished	Apr 18 02:50:59 PM PDT 24
Peak memory	380052 kb
Host	smart-c4ec766e-dde5-430a-9ddb-a49947cd342f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023723164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.3023723164
Directory	/workspace/22.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access.406509601
Short name	T332
Test name
Test status
Simulation time	994650252 ps
CPU time	14.48 seconds
Started	Apr 18 02:35:16 PM PDT 24
Finished	Apr 18 02:35:31 PM PDT 24
Peak memory	202972 kb
Host	smart-e81ecff5-92f0-45ed-9917-be6507a6b7ec
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406509601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.s ram_ctrl_partial_access.406509601
Directory	/workspace/22.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2800708949
Short name	T638
Test name
Test status
Simulation time	14790433232 ps
CPU time	384.71 seconds
Started	Apr 18 02:35:18 PM PDT 24
Finished	Apr 18 02:41:43 PM PDT 24
Peak memory	203224 kb
Host	smart-1ca67ff0-98f8-499f-8b08-922a5d7430af
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800708949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.2800708949
Directory	/workspace/22.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/22.sram_ctrl_ram_cfg.1372299252
Short name	T669
Test name
Test status
Simulation time	413736454 ps
CPU time	3.39 seconds
Started	Apr 18 02:35:20 PM PDT 24
Finished	Apr 18 02:35:24 PM PDT 24
Peak memory	203060 kb
Host	smart-d2a96f45-59e2-4b5e-a6e7-18cca4a107d9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372299252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1372299252
Directory	/workspace/22.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/22.sram_ctrl_regwen.2350852166
Short name	T780
Test name
Test status
Simulation time	52615701787 ps
CPU time	833.43 seconds
Started	Apr 18 02:35:22 PM PDT 24
Finished	Apr 18 02:49:15 PM PDT 24
Peak memory	380992 kb
Host	smart-c0a66407-221b-44f8-847f-4d98e2da6245
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350852166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2350852166
Directory	/workspace/22.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/22.sram_ctrl_smoke.2918885980
Short name	T450
Test name
Test status
Simulation time	1495854933 ps
CPU time	7.47 seconds
Started	Apr 18 02:35:13 PM PDT 24
Finished	Apr 18 02:35:21 PM PDT 24
Peak memory	206116 kb
Host	smart-b9387314-cd9e-49cc-9630-a48ade967931
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918885980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2918885980
Directory	/workspace/22.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_all.1214149729
Short name	T268
Test name
Test status
Simulation time	82190952372 ps
CPU time	1097.55 seconds
Started	Apr 18 02:35:26 PM PDT 24
Finished	Apr 18 02:53:44 PM PDT 24
Peak memory	375096 kb
Host	smart-b55744b1-8f8c-4f8f-adfe-0635079663de
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214149729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.1214149729
Directory	/workspace/22.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.1545028836
Short name	T547
Test name
Test status
Simulation time	5225923477 ps
CPU time	197.07 seconds
Started	Apr 18 02:35:13 PM PDT 24
Finished	Apr 18 02:38:30 PM PDT 24
Peak memory	203148 kb
Host	smart-a0dd49de-2e95-4a23-8908-c8a9ac5057e7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545028836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.1545028836
Directory	/workspace/22.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3476357880
Short name	T151
Test name
Test status
Simulation time	8817196446 ps
CPU time	23.82 seconds
Started	Apr 18 02:35:17 PM PDT 24
Finished	Apr 18 02:35:41 PM PDT 24
Peak memory	256300 kb
Host	smart-cd9bd900-0b93-4edf-8b5f-e028e94c58c2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476357880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.3476357880
Directory	/workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1686360529
Short name	T707
Test name
Test status
Simulation time	58569829029 ps
CPU time	741.02 seconds
Started	Apr 18 02:35:45 PM PDT 24
Finished	Apr 18 02:48:07 PM PDT 24
Peak memory	373884 kb
Host	smart-4470903a-ecba-4457-a7fb-b86e1f1cb84d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686360529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.1686360529
Directory	/workspace/23.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/23.sram_ctrl_alert_test.3801199006
Short name	T375
Test name
Test status
Simulation time	14379393 ps
CPU time	0.66 seconds
Started	Apr 18 02:35:51 PM PDT 24
Finished	Apr 18 02:35:52 PM PDT 24
Peak memory	202844 kb
Host	smart-113d206f-13be-428c-95f3-b978b571691c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801199006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3801199006
Directory	/workspace/23.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.sram_ctrl_bijection.3995107135
Short name	T799
Test name
Test status
Simulation time	37065516906 ps
CPU time	557.14 seconds
Started	Apr 18 02:35:31 PM PDT 24
Finished	Apr 18 02:44:48 PM PDT 24
Peak memory	203264 kb
Host	smart-4b06be6e-52bf-4a94-ae46-5bd617822221
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995107135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .3995107135
Directory	/workspace/23.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/23.sram_ctrl_executable.408560520
Short name	T41
Test name
Test status
Simulation time	17549839841 ps
CPU time	1248.2 seconds
Started	Apr 18 02:35:46 PM PDT 24
Finished	Apr 18 02:56:34 PM PDT 24
Peak memory	374904 kb
Host	smart-57e982be-a8a7-4e73-8586-d34f9df385cb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408560520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executabl e.408560520
Directory	/workspace/23.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/23.sram_ctrl_lc_escalation.972679304
Short name	T356
Test name
Test status
Simulation time	9583340052 ps
CPU time	60.23 seconds
Started	Apr 18 02:35:45 PM PDT 24
Finished	Apr 18 02:36:46 PM PDT 24
Peak memory	203088 kb
Host	smart-5287fc19-8cf6-4eef-9698-d20ee760c6c6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972679304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_esc alation.972679304
Directory	/workspace/23.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/23.sram_ctrl_max_throughput.4049314012
Short name	T161
Test name
Test status
Simulation time	797395639 ps
CPU time	113.3 seconds
Started	Apr 18 02:35:36 PM PDT 24
Finished	Apr 18 02:37:30 PM PDT 24
Peak memory	363520 kb
Host	smart-e09cca10-025d-4932-9bae-b6d56b2d5f5d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049314012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.4049314012
Directory	/workspace/23.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2195729967
Short name	T753
Test name
Test status
Simulation time	1628233258 ps
CPU time	117.1 seconds
Started	Apr 18 02:35:45 PM PDT 24
Finished	Apr 18 02:37:42 PM PDT 24
Peak memory	211240 kb
Host	smart-09345074-fef4-4c67-989e-bb56c690a6d0
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195729967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.2195729967
Directory	/workspace/23.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_walk.911957114
Short name	T307
Test name
Test status
Simulation time	4125714975 ps
CPU time	117.21 seconds
Started	Apr 18 02:35:46 PM PDT 24
Finished	Apr 18 02:37:44 PM PDT 24
Peak memory	203296 kb
Host	smart-adcb8b25-1976-4c25-bf7d-295e977ea215
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911957114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl _mem_walk.911957114
Directory	/workspace/23.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/23.sram_ctrl_multiple_keys.1440905229
Short name	T841
Test name
Test status
Simulation time	52725437979 ps
CPU time	870.91 seconds
Started	Apr 18 02:35:25 PM PDT 24
Finished	Apr 18 02:49:56 PM PDT 24
Peak memory	370568 kb
Host	smart-21081f72-65fc-48e8-955e-a76219efc089
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440905229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.1440905229
Directory	/workspace/23.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access.740971411
Short name	T818
Test name
Test status
Simulation time	2087519619 ps
CPU time	19.35 seconds
Started	Apr 18 02:35:32 PM PDT 24
Finished	Apr 18 02:35:51 PM PDT 24
Peak memory	202996 kb
Host	smart-70c14765-c3f6-4200-9efe-ef6dcb7eb50c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740971411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s ram_ctrl_partial_access.740971411
Directory	/workspace/23.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1540257434
Short name	T903
Test name
Test status
Simulation time	18225134618 ps
CPU time	426.93 seconds
Started	Apr 18 02:35:38 PM PDT 24
Finished	Apr 18 02:42:45 PM PDT 24
Peak memory	203176 kb
Host	smart-2fc4630f-553b-4019-aed1-cf48495d2222
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540257434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.1540257434
Directory	/workspace/23.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/23.sram_ctrl_ram_cfg.2651603823
Short name	T719
Test name
Test status
Simulation time	609677353 ps
CPU time	3.55 seconds
Started	Apr 18 02:35:48 PM PDT 24
Finished	Apr 18 02:35:52 PM PDT 24
Peak memory	203056 kb
Host	smart-271fd627-3f77-4829-9e38-6d687d22f953
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651603823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2651603823
Directory	/workspace/23.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/23.sram_ctrl_regwen.1517663122
Short name	T931
Test name
Test status
Simulation time	2800304438 ps
CPU time	1356.99 seconds
Started	Apr 18 02:35:46 PM PDT 24
Finished	Apr 18 02:58:23 PM PDT 24
Peak memory	377940 kb
Host	smart-36c43bc9-11b9-45ff-9924-80c0cae6c5be
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517663122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1517663122
Directory	/workspace/23.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/23.sram_ctrl_smoke.3323936774
Short name	T361
Test name
Test status
Simulation time	21899377764 ps
CPU time	22.25 seconds
Started	Apr 18 02:35:25 PM PDT 24
Finished	Apr 18 02:35:48 PM PDT 24
Peak memory	203104 kb
Host	smart-a089d64e-0a41-4c8d-90e7-70ae7db8d4bf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323936774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3323936774
Directory	/workspace/23.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all.2363567587
Short name	T54
Test name
Test status
Simulation time	245513836902 ps
CPU time	6146.65 seconds
Started	Apr 18 02:35:54 PM PDT 24
Finished	Apr 18 04:18:21 PM PDT 24
Peak memory	379000 kb
Host	smart-a9053a85-497a-466f-89fe-657f55565bd9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363567587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.2363567587
Directory	/workspace/23.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2184893339
Short name	T51
Test name
Test status
Simulation time	3126679000 ps
CPU time	7.61 seconds
Started	Apr 18 02:35:45 PM PDT 24
Finished	Apr 18 02:35:54 PM PDT 24
Peak memory	211316 kb
Host	smart-586d7dcf-b29a-45e2-aaae-90e2a1ae6f3b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2184893339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2184893339
Directory	/workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3528080407
Short name	T795
Test name
Test status
Simulation time	4939094518 ps
CPU time	261.47 seconds
Started	Apr 18 02:35:31 PM PDT 24
Finished	Apr 18 02:39:53 PM PDT 24
Peak memory	203108 kb
Host	smart-ec1de54a-100f-4caa-8712-6a296d2d8b1a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528080407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3528080407
Directory	/workspace/23.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.233696726
Short name	T139
Test name
Test status
Simulation time	3897613974 ps
CPU time	53.2 seconds
Started	Apr 18 02:35:37 PM PDT 24
Finished	Apr 18 02:36:30 PM PDT 24
Peak memory	303168 kb
Host	smart-d1ae7049-d1a0-4b31-94e7-fca602d8071e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233696726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.233696726
Directory	/workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/24.sram_ctrl_access_during_key_req.936320668
Short name	T486
Test name
Test status
Simulation time	41179216600 ps
CPU time	1324.7 seconds
Started	Apr 18 02:36:07 PM PDT 24
Finished	Apr 18 02:58:12 PM PDT 24
Peak memory	374888 kb
Host	smart-ada8a311-40f9-40cf-905d-f26a033a1c3c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936320668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 24.sram_ctrl_access_during_key_req.936320668
Directory	/workspace/24.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/24.sram_ctrl_alert_test.2027975664
Short name	T662
Test name
Test status
Simulation time	13582912 ps
CPU time	0.63 seconds
Started	Apr 18 02:36:10 PM PDT 24
Finished	Apr 18 02:36:11 PM PDT 24
Peak memory	202648 kb
Host	smart-36b97e9f-8470-4ba0-82a9-c75d458c5781
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027975664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2027975664
Directory	/workspace/24.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.sram_ctrl_bijection.486415782
Short name	T447
Test name
Test status
Simulation time	21321239322 ps
CPU time	1506.06 seconds
Started	Apr 18 02:35:57 PM PDT 24
Finished	Apr 18 03:01:03 PM PDT 24
Peak memory	203316 kb
Host	smart-6a34862e-afb3-4a4a-8266-ff0148d71c99
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486415782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection. 486415782
Directory	/workspace/24.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/24.sram_ctrl_executable.2931724535
Short name	T465
Test name
Test status
Simulation time	11030058109 ps
CPU time	742.29 seconds
Started	Apr 18 02:36:06 PM PDT 24
Finished	Apr 18 02:48:28 PM PDT 24
Peak memory	378956 kb
Host	smart-8b361e0f-4e20-4ee3-81ca-768930d4aac1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931724535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.2931724535
Directory	/workspace/24.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/24.sram_ctrl_lc_escalation.2489913747
Short name	T359
Test name
Test status
Simulation time	152977929849 ps
CPU time	107.5 seconds
Started	Apr 18 02:36:05 PM PDT 24
Finished	Apr 18 02:37:53 PM PDT 24
Peak memory	203060 kb
Host	smart-511236cf-401e-4858-b79a-5a10717b88e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489913747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.2489913747
Directory	/workspace/24.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/24.sram_ctrl_max_throughput.2319483519
Short name	T926
Test name
Test status
Simulation time	1501916435 ps
CPU time	160.05 seconds
Started	Apr 18 02:36:02 PM PDT 24
Finished	Apr 18 02:38:42 PM PDT 24
Peak memory	370644 kb
Host	smart-99594d9a-f032-4fef-93dd-71f6e9e239fc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319483519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.2319483519
Directory	/workspace/24.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1172632748
Short name	T812
Test name
Test status
Simulation time	1623276747 ps
CPU time	117.44 seconds
Started	Apr 18 02:36:07 PM PDT 24
Finished	Apr 18 02:38:04 PM PDT 24
Peak memory	211168 kb
Host	smart-427d1f61-e1a6-4701-91f3-f0eeb9a8b145
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172632748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1172632748
Directory	/workspace/24.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_walk.1791286178
Short name	T581
Test name
Test status
Simulation time	2066349936 ps
CPU time	118.85 seconds
Started	Apr 18 02:36:05 PM PDT 24
Finished	Apr 18 02:38:05 PM PDT 24
Peak memory	203160 kb
Host	smart-c2199323-1dac-48da-a003-bffa25aec99f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791286178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.1791286178
Directory	/workspace/24.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/24.sram_ctrl_multiple_keys.3477938392
Short name	T373
Test name
Test status
Simulation time	42584262818 ps
CPU time	334.63 seconds
Started	Apr 18 02:35:56 PM PDT 24
Finished	Apr 18 02:41:32 PM PDT 24
Peak memory	370716 kb
Host	smart-83a7ea28-771f-4b43-8b35-8d861cb24ffd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477938392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.3477938392
Directory	/workspace/24.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access.429227915
Short name	T821
Test name
Test status
Simulation time	433512359 ps
CPU time	5.96 seconds
Started	Apr 18 02:35:57 PM PDT 24
Finished	Apr 18 02:36:03 PM PDT 24
Peak memory	211908 kb
Host	smart-14825d8d-4eff-4bc1-bf92-e2bd8e9ea279
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429227915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s ram_ctrl_partial_access.429227915
Directory	/workspace/24.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2138006851
Short name	T714
Test name
Test status
Simulation time	5172028229 ps
CPU time	287.25 seconds
Started	Apr 18 02:36:03 PM PDT 24
Finished	Apr 18 02:40:51 PM PDT 24
Peak memory	203176 kb
Host	smart-246ea428-198d-4e87-8cdd-efd54ddab504
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138006851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.2138006851
Directory	/workspace/24.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/24.sram_ctrl_ram_cfg.2202128340
Short name	T675
Test name
Test status
Simulation time	1462635821 ps
CPU time	3.59 seconds
Started	Apr 18 02:36:06 PM PDT 24
Finished	Apr 18 02:36:10 PM PDT 24
Peak memory	203048 kb
Host	smart-4b5cf513-de1f-40de-8000-cdae6bc531f7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202128340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2202128340
Directory	/workspace/24.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/24.sram_ctrl_regwen.3882983983
Short name	T484
Test name
Test status
Simulation time	13812696897 ps
CPU time	526.68 seconds
Started	Apr 18 02:36:07 PM PDT 24
Finished	Apr 18 02:44:54 PM PDT 24
Peak memory	360812 kb
Host	smart-1f96dbf7-0813-46a5-9d6c-ec6d093c4fb1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882983983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3882983983
Directory	/workspace/24.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/24.sram_ctrl_smoke.3759288581
Short name	T136
Test name
Test status
Simulation time	3292798401 ps
CPU time	21.75 seconds
Started	Apr 18 02:35:51 PM PDT 24
Finished	Apr 18 02:36:13 PM PDT 24
Peak memory	260084 kb
Host	smart-e55c8ec6-63a3-4525-91e0-2b1e1cbc04e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759288581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3759288581
Directory	/workspace/24.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all.1859018775
Short name	T300
Test name
Test status
Simulation time	306783435208 ps
CPU time	6174.04 seconds
Started	Apr 18 02:36:12 PM PDT 24
Finished	Apr 18 04:19:07 PM PDT 24
Peak memory	380048 kb
Host	smart-9c51edfc-07a0-47de-9837-e4bf545a3517
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859018775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.1859018775
Directory	/workspace/24.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1386777433
Short name	T709
Test name
Test status
Simulation time	11561291258 ps
CPU time	59.75 seconds
Started	Apr 18 02:36:07 PM PDT 24
Finished	Apr 18 02:37:07 PM PDT 24
Peak memory	212948 kb
Host	smart-5c8cf02a-022d-45b1-9894-aa4a324c2a50
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1386777433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.1386777433
Directory	/workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.417585177
Short name	T536
Test name
Test status
Simulation time	20680688823 ps
CPU time	320.21 seconds
Started	Apr 18 02:35:55 PM PDT 24
Finished	Apr 18 02:41:16 PM PDT 24
Peak memory	203128 kb
Host	smart-6f0d5d51-236e-4340-9076-45691950e156
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417585177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .sram_ctrl_stress_pipeline.417585177
Directory	/workspace/24.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.680017233
Short name	T568
Test name
Test status
Simulation time	2540877804 ps
CPU time	61.48 seconds
Started	Apr 18 02:36:04 PM PDT 24
Finished	Apr 18 02:37:06 PM PDT 24
Peak memory	301196 kb
Host	smart-c123f32c-7115-40f1-90bb-fa4298956c49
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680017233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_throughput_w_partial_write.680017233
Directory	/workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2946262224
Short name	T830
Test name
Test status
Simulation time	17910244220 ps
CPU time	1171.63 seconds
Started	Apr 18 02:36:23 PM PDT 24
Finished	Apr 18 02:55:55 PM PDT 24
Peak memory	374944 kb
Host	smart-99163415-e8e7-4b7b-9666-6c1ce5e037b3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946262224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2946262224
Directory	/workspace/25.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/25.sram_ctrl_alert_test.2311505690
Short name	T214
Test name
Test status
Simulation time	55995227 ps
CPU time	0.65 seconds
Started	Apr 18 02:36:28 PM PDT 24
Finished	Apr 18 02:36:29 PM PDT 24
Peak memory	202756 kb
Host	smart-0418b156-d74f-4620-8db6-576c34a5bf18
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311505690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2311505690
Directory	/workspace/25.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.sram_ctrl_bijection.2809246447
Short name	T326
Test name
Test status
Simulation time	135189674778 ps
CPU time	734.89 seconds
Started	Apr 18 02:36:10 PM PDT 24
Finished	Apr 18 02:48:26 PM PDT 24
Peak memory	203348 kb
Host	smart-767a7232-1044-4e9e-bd75-15a4ad80f075
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809246447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .2809246447
Directory	/workspace/25.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/25.sram_ctrl_executable.1073327444
Short name	T474
Test name
Test status
Simulation time	18772268024 ps
CPU time	1193.64 seconds
Started	Apr 18 02:36:23 PM PDT 24
Finished	Apr 18 02:56:17 PM PDT 24
Peak memory	379024 kb
Host	smart-24f68fa6-83eb-4319-a67b-29bdf1b07dcc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073327444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.1073327444
Directory	/workspace/25.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/25.sram_ctrl_lc_escalation.2592138076
Short name	T566
Test name
Test status
Simulation time	7525462283 ps
CPU time	20.32 seconds
Started	Apr 18 02:36:24 PM PDT 24
Finished	Apr 18 02:36:45 PM PDT 24
Peak memory	214964 kb
Host	smart-bf02801a-33a0-4a89-acf8-339125a9f2c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592138076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.2592138076
Directory	/workspace/25.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/25.sram_ctrl_max_throughput.2599584396
Short name	T643
Test name
Test status
Simulation time	6066832207 ps
CPU time	6.4 seconds
Started	Apr 18 02:36:18 PM PDT 24
Finished	Apr 18 02:36:24 PM PDT 24
Peak memory	211128 kb
Host	smart-8c9747e6-7844-4c59-aec2-02816f3f4981
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599584396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.2599584396
Directory	/workspace/25.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2576732502
Short name	T386
Test name
Test status
Simulation time	1097912733 ps
CPU time	67.64 seconds
Started	Apr 18 02:36:27 PM PDT 24
Finished	Apr 18 02:37:35 PM PDT 24
Peak memory	211212 kb
Host	smart-d5efd30a-fa7f-45ce-9968-b9f5d9690efe
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576732502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.2576732502
Directory	/workspace/25.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_walk.517656158
Short name	T867
Test name
Test status
Simulation time	7589960297 ps
CPU time	129.97 seconds
Started	Apr 18 02:36:22 PM PDT 24
Finished	Apr 18 02:38:33 PM PDT 24
Peak memory	203536 kb
Host	smart-a2869cd0-18aa-4369-8e7e-73b1d4545ca1
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517656158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl _mem_walk.517656158
Directory	/workspace/25.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/25.sram_ctrl_multiple_keys.3077492159
Short name	T236
Test name
Test status
Simulation time	38888718561 ps
CPU time	433.18 seconds
Started	Apr 18 02:36:12 PM PDT 24
Finished	Apr 18 02:43:25 PM PDT 24
Peak memory	367424 kb
Host	smart-acc3c63c-3fdf-4f40-a392-5c121fb5cc08
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077492159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.3077492159
Directory	/workspace/25.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access.1721432728
Short name	T603
Test name
Test status
Simulation time	1358691988 ps
CPU time	6.31 seconds
Started	Apr 18 02:36:19 PM PDT 24
Finished	Apr 18 02:36:25 PM PDT 24
Peak memory	203072 kb
Host	smart-e98b6345-f9b8-450e-8604-f604c9cd1328
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721432728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.1721432728
Directory	/workspace/25.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3654460779
Short name	T291
Test name
Test status
Simulation time	13218016739 ps
CPU time	311.05 seconds
Started	Apr 18 02:36:18 PM PDT 24
Finished	Apr 18 02:41:30 PM PDT 24
Peak memory	203172 kb
Host	smart-8b43eba3-b1a8-49aa-9f7a-91224d732d9a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654460779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.3654460779
Directory	/workspace/25.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/25.sram_ctrl_ram_cfg.2225814046
Short name	T784
Test name
Test status
Simulation time	1407772768 ps
CPU time	3.55 seconds
Started	Apr 18 02:36:22 PM PDT 24
Finished	Apr 18 02:36:25 PM PDT 24
Peak memory	203060 kb
Host	smart-e67000f8-41f3-4dbe-8921-40b1595a1faf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225814046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2225814046
Directory	/workspace/25.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/25.sram_ctrl_regwen.1485513803
Short name	T28
Test name
Test status
Simulation time	21415643727 ps
CPU time	1646.87 seconds
Started	Apr 18 02:36:23 PM PDT 24
Finished	Apr 18 03:03:50 PM PDT 24
Peak memory	379172 kb
Host	smart-40d8bf02-9a13-472b-aff6-6421cc1c6f07
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485513803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1485513803
Directory	/workspace/25.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/25.sram_ctrl_smoke.673834695
Short name	T372
Test name
Test status
Simulation time	5019575463 ps
CPU time	16.32 seconds
Started	Apr 18 02:36:11 PM PDT 24
Finished	Apr 18 02:36:28 PM PDT 24
Peak memory	203124 kb
Host	smart-5933a313-87eb-416a-8c81-de9c3ccc4439
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673834695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.673834695
Directory	/workspace/25.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all.3823416168
Short name	T876
Test name
Test status
Simulation time	155557987230 ps
CPU time	6625.69 seconds
Started	Apr 18 02:36:27 PM PDT 24
Finished	Apr 18 04:26:54 PM PDT 24
Peak memory	390280 kb
Host	smart-b06058f7-c1ac-4140-9192-77f46a891997
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823416168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.3823416168
Directory	/workspace/25.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4170580992
Short name	T425
Test name
Test status
Simulation time	874731018 ps
CPU time	26.82 seconds
Started	Apr 18 02:36:27 PM PDT 24
Finished	Apr 18 02:36:55 PM PDT 24
Peak memory	212752 kb
Host	smart-4cc32c63-09b0-4546-a3a3-58387027961f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4170580992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.4170580992
Directory	/workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2266320757
Short name	T202
Test name
Test status
Simulation time	5917928395 ps
CPU time	228.3 seconds
Started	Apr 18 02:36:10 PM PDT 24
Finished	Apr 18 02:39:59 PM PDT 24
Peak memory	203388 kb
Host	smart-3d707cf9-4ca6-48c0-9902-9a745e07d68a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266320757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.2266320757
Directory	/workspace/25.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2126855410
Short name	T655
Test name
Test status
Simulation time	3207453713 ps
CPU time	82.02 seconds
Started	Apr 18 02:36:19 PM PDT 24
Finished	Apr 18 02:37:41 PM PDT 24
Peak memory	354284 kb
Host	smart-4c316b24-668b-4a49-987d-50d080ba2a07
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126855410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.2126855410
Directory	/workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2902546908
Short name	T16
Test name
Test status
Simulation time	1922561068 ps
CPU time	95.68 seconds
Started	Apr 18 02:36:43 PM PDT 24
Finished	Apr 18 02:38:19 PM PDT 24
Peak memory	318468 kb
Host	smart-7dc0d5ca-f5e2-4e00-90f8-f154df38f258
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902546908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.2902546908
Directory	/workspace/26.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/26.sram_ctrl_alert_test.1050237874
Short name	T577
Test name
Test status
Simulation time	51281464 ps
CPU time	0.62 seconds
Started	Apr 18 02:37:01 PM PDT 24
Finished	Apr 18 02:37:02 PM PDT 24
Peak memory	202812 kb
Host	smart-ecf1896d-c6b3-49aa-8d74-8639e039ac0b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050237874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.1050237874
Directory	/workspace/26.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.sram_ctrl_bijection.1365315212
Short name	T471
Test name
Test status
Simulation time	139149730801 ps
CPU time	568.21 seconds
Started	Apr 18 02:36:26 PM PDT 24
Finished	Apr 18 02:45:55 PM PDT 24
Peak memory	203336 kb
Host	smart-afeb1654-0718-4a95-9e61-c4ce8648f842
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365315212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .1365315212
Directory	/workspace/26.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/26.sram_ctrl_executable.1793324438
Short name	T46
Test name
Test status
Simulation time	27154328700 ps
CPU time	808.02 seconds
Started	Apr 18 02:36:43 PM PDT 24
Finished	Apr 18 02:50:11 PM PDT 24
Peak memory	376912 kb
Host	smart-6428bf33-5985-4299-ba0b-2125a33ee9ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793324438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.1793324438
Directory	/workspace/26.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/26.sram_ctrl_lc_escalation.1997117603
Short name	T741
Test name
Test status
Simulation time	13026352571 ps
CPU time	81.4 seconds
Started	Apr 18 02:36:38 PM PDT 24
Finished	Apr 18 02:38:00 PM PDT 24
Peak memory	203088 kb
Host	smart-73892b88-7568-4fbb-9456-41f87ec281a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997117603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.1997117603
Directory	/workspace/26.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/26.sram_ctrl_max_throughput.2362086285
Short name	T141
Test name
Test status
Simulation time	14048378537 ps
CPU time	24.82 seconds
Started	Apr 18 02:36:32 PM PDT 24
Finished	Apr 18 02:36:57 PM PDT 24
Peak memory	268468 kb
Host	smart-115bbd0a-7c20-4e10-8d76-a7019bd43e97
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362086285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.2362086285
Directory	/workspace/26.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.825115428
Short name	T180
Test name
Test status
Simulation time	4157162214 ps
CPU time	60.34 seconds
Started	Apr 18 02:36:47 PM PDT 24
Finished	Apr 18 02:37:48 PM PDT 24
Peak memory	211308 kb
Host	smart-a656bef3-a8b5-41d5-b6b0-a9582e175cc9
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825115428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_mem_partial_access.825115428
Directory	/workspace/26.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_walk.3039079958
Short name	T266
Test name
Test status
Simulation time	21928837509 ps
CPU time	131.2 seconds
Started	Apr 18 02:37:01 PM PDT 24
Finished	Apr 18 02:39:13 PM PDT 24
Peak memory	203224 kb
Host	smart-bbc3ef30-c56c-411a-9bd9-81301185505f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039079958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.3039079958
Directory	/workspace/26.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/26.sram_ctrl_multiple_keys.2748939970
Short name	T132
Test name
Test status
Simulation time	78279159471 ps
CPU time	1337.46 seconds
Started	Apr 18 02:36:27 PM PDT 24
Finished	Apr 18 02:58:45 PM PDT 24
Peak memory	381068 kb
Host	smart-cabeeecc-1cc6-4f4d-a243-9a67b01eff0c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748939970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.2748939970
Directory	/workspace/26.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access.2089272649
Short name	T932
Test name
Test status
Simulation time	2421553683 ps
CPU time	33.38 seconds
Started	Apr 18 02:36:33 PM PDT 24
Finished	Apr 18 02:37:07 PM PDT 24
Peak memory	295092 kb
Host	smart-207e5890-e652-4e11-8adb-ffb4164dc513
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089272649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.2089272649
Directory	/workspace/26.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3510177914
Short name	T249
Test name
Test status
Simulation time	22282426302 ps
CPU time	130.91 seconds
Started	Apr 18 02:36:32 PM PDT 24
Finished	Apr 18 02:38:43 PM PDT 24
Peak memory	203156 kb
Host	smart-81bc0bb4-f1d0-4761-9bc7-888626b07bf9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510177914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.3510177914
Directory	/workspace/26.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/26.sram_ctrl_ram_cfg.726037538
Short name	T605
Test name
Test status
Simulation time	1354228670 ps
CPU time	3.57 seconds
Started	Apr 18 02:37:00 PM PDT 24
Finished	Apr 18 02:37:04 PM PDT 24
Peak memory	203064 kb
Host	smart-685751cc-74ac-4e5a-b04a-1034c32e2756
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726037538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.726037538
Directory	/workspace/26.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/26.sram_ctrl_regwen.3927690318
Short name	T189
Test name
Test status
Simulation time	17164311602 ps
CPU time	530.46 seconds
Started	Apr 18 02:36:44 PM PDT 24
Finished	Apr 18 02:45:35 PM PDT 24
Peak memory	377028 kb
Host	smart-c6719001-6cd8-4e1d-a606-727cd371fd09
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927690318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3927690318
Directory	/workspace/26.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/26.sram_ctrl_smoke.1538512606
Short name	T678
Test name
Test status
Simulation time	3230155266 ps
CPU time	11.72 seconds
Started	Apr 18 02:36:27 PM PDT 24
Finished	Apr 18 02:36:39 PM PDT 24
Peak memory	203064 kb
Host	smart-4b1745be-553d-4805-a3cc-c97c383f469a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538512606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1538512606
Directory	/workspace/26.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_all.153311430
Short name	T395
Test name
Test status
Simulation time	1580003333351 ps
CPU time	3321.23 seconds
Started	Apr 18 02:37:00 PM PDT 24
Finished	Apr 18 03:32:22 PM PDT 24
Peak memory	376988 kb
Host	smart-2c652773-8b44-4008-98d3-617aa6b81f77
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153311430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_stress_all.153311430
Directory	/workspace/26.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2688620218
Short name	T104
Test name
Test status
Simulation time	238186218 ps
CPU time	8.52 seconds
Started	Apr 18 02:37:00 PM PDT 24
Finished	Apr 18 02:37:09 PM PDT 24
Peak memory	211256 kb
Host	smart-7a73c3cf-3a3a-43bb-be14-7d707c4bcbf7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2688620218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.2688620218
Directory	/workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.3223116790
Short name	T698
Test name
Test status
Simulation time	4974695762 ps
CPU time	315.93 seconds
Started	Apr 18 02:36:31 PM PDT 24
Finished	Apr 18 02:41:47 PM PDT 24
Peak memory	203216 kb
Host	smart-1fa5fe2b-67e2-4d47-be90-3743bc44e279
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223116790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.3223116790
Directory	/workspace/26.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2894419382
Short name	T856
Test name
Test status
Simulation time	1557363581 ps
CPU time	101.35 seconds
Started	Apr 18 02:36:39 PM PDT 24
Finished	Apr 18 02:38:20 PM PDT 24
Peak memory	338912 kb
Host	smart-f25eb999-da43-4fe3-9c06-80d9b7627e6c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894419382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2894419382
Directory	/workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1557462240
Short name	T646
Test name
Test status
Simulation time	3846446895 ps
CPU time	192.38 seconds
Started	Apr 18 02:37:02 PM PDT 24
Finished	Apr 18 02:40:14 PM PDT 24
Peak memory	372156 kb
Host	smart-4f3fd206-2432-4e9e-974a-25101382b171
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557462240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.1557462240
Directory	/workspace/27.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/27.sram_ctrl_alert_test.463747334
Short name	T679
Test name
Test status
Simulation time	83652515 ps
CPU time	0.66 seconds
Started	Apr 18 02:37:13 PM PDT 24
Finished	Apr 18 02:37:14 PM PDT 24
Peak memory	202740 kb
Host	smart-957127e2-3e97-43e6-bc02-c4ac494a8172
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463747334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.463747334
Directory	/workspace/27.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.sram_ctrl_bijection.2348537789
Short name	T133
Test name
Test status
Simulation time	42625543432 ps
CPU time	1496.5 seconds
Started	Apr 18 02:37:01 PM PDT 24
Finished	Apr 18 03:01:58 PM PDT 24
Peak memory	203140 kb
Host	smart-81ce1732-052a-434a-b26c-5f9ac4e00c85
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348537789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .2348537789
Directory	/workspace/27.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/27.sram_ctrl_executable.2639962420
Short name	T842
Test name
Test status
Simulation time	7205407596 ps
CPU time	466.2 seconds
Started	Apr 18 02:37:02 PM PDT 24
Finished	Apr 18 02:44:48 PM PDT 24
Peak memory	376948 kb
Host	smart-457a818c-e6e8-4270-8804-137a0b4048a2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639962420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.2639962420
Directory	/workspace/27.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/27.sram_ctrl_lc_escalation.855996572
Short name	T870
Test name
Test status
Simulation time	128197772420 ps
CPU time	114.82 seconds
Started	Apr 18 02:37:02 PM PDT 24
Finished	Apr 18 02:38:57 PM PDT 24
Peak memory	211252 kb
Host	smart-743925af-2901-4c7d-ac54-bd7a9396f6bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855996572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_esc alation.855996572
Directory	/workspace/27.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/27.sram_ctrl_max_throughput.1747673004
Short name	T39
Test name
Test status
Simulation time	691167054 ps
CPU time	12.74 seconds
Started	Apr 18 02:37:03 PM PDT 24
Finished	Apr 18 02:37:16 PM PDT 24
Peak memory	236928 kb
Host	smart-73e43eab-b547-4223-a335-46ee5babead2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747673004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.1747673004
Directory	/workspace/27.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3624203123
Short name	T66
Test name
Test status
Simulation time	18170819139 ps
CPU time	150.28 seconds
Started	Apr 18 02:37:14 PM PDT 24
Finished	Apr 18 02:39:44 PM PDT 24
Peak memory	211388 kb
Host	smart-9a70bc1c-f7c9-43e7-8d0d-8f45dd04c8ba
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624203123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.3624203123
Directory	/workspace/27.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_walk.3976282061
Short name	T595
Test name
Test status
Simulation time	3944519926 ps
CPU time	244.4 seconds
Started	Apr 18 02:37:08 PM PDT 24
Finished	Apr 18 02:41:13 PM PDT 24
Peak memory	203236 kb
Host	smart-20ac507b-6bee-4002-973c-80c0b342011b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976282061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.3976282061
Directory	/workspace/27.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/27.sram_ctrl_multiple_keys.971752214
Short name	T498
Test name
Test status
Simulation time	6163954172 ps
CPU time	118.17 seconds
Started	Apr 18 02:36:54 PM PDT 24
Finished	Apr 18 02:38:52 PM PDT 24
Peak memory	314556 kb
Host	smart-0cbd78ff-9c04-4d7f-82f8-c60e6511aa8a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971752214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multip le_keys.971752214
Directory	/workspace/27.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access.3610428834
Short name	T560
Test name
Test status
Simulation time	7101444342 ps
CPU time	28.24 seconds
Started	Apr 18 02:37:00 PM PDT 24
Finished	Apr 18 02:37:29 PM PDT 24
Peak memory	203192 kb
Host	smart-57a3a3de-d398-4323-9458-65c279cf7188
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610428834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.3610428834
Directory	/workspace/27.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1798574676
Short name	T392
Test name
Test status
Simulation time	7232250473 ps
CPU time	212.13 seconds
Started	Apr 18 02:36:59 PM PDT 24
Finished	Apr 18 02:40:32 PM PDT 24
Peak memory	203132 kb
Host	smart-75dddae8-385c-49ce-abc9-5aa2f30a2ad9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798574676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.1798574676
Directory	/workspace/27.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/27.sram_ctrl_ram_cfg.3858623622
Short name	T520
Test name
Test status
Simulation time	398794222 ps
CPU time	3.32 seconds
Started	Apr 18 02:37:08 PM PDT 24
Finished	Apr 18 02:37:11 PM PDT 24
Peak memory	203060 kb
Host	smart-835cc4db-3b08-4855-86f4-1bbcd0bd0d75
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858623622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3858623622
Directory	/workspace/27.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/27.sram_ctrl_regwen.3895259569
Short name	T27
Test name
Test status
Simulation time	3190832604 ps
CPU time	824.06 seconds
Started	Apr 18 02:37:03 PM PDT 24
Finished	Apr 18 02:50:47 PM PDT 24
Peak memory	378932 kb
Host	smart-0b45b05f-d891-4df9-90b6-318b26b38310
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895259569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3895259569
Directory	/workspace/27.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/27.sram_ctrl_smoke.4182964437
Short name	T554
Test name
Test status
Simulation time	2067254193 ps
CPU time	7.19 seconds
Started	Apr 18 02:37:01 PM PDT 24
Finished	Apr 18 02:37:09 PM PDT 24
Peak memory	202976 kb
Host	smart-5ac44ca3-a80b-44c4-bed6-f57c4232b3c1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182964437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.4182964437
Directory	/workspace/27.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_all.3208660834
Short name	T599
Test name
Test status
Simulation time	192048894652 ps
CPU time	2027.22 seconds
Started	Apr 18 02:37:14 PM PDT 24
Finished	Apr 18 03:11:01 PM PDT 24
Peak memory	380064 kb
Host	smart-9f9e8f09-4dd2-46b3-bba0-5496cf826da4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208660834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.3208660834
Directory	/workspace/27.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.355088987
Short name	T106
Test name
Test status
Simulation time	4447250919 ps
CPU time	140.93 seconds
Started	Apr 18 02:37:14 PM PDT 24
Finished	Apr 18 02:39:36 PM PDT 24
Peak memory	374908 kb
Host	smart-d39876ac-c47f-4b51-8f9c-9dd9b13918e7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=355088987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.355088987
Directory	/workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2075612823
Short name	T713
Test name
Test status
Simulation time	23025553813 ps
CPU time	368.43 seconds
Started	Apr 18 02:36:58 PM PDT 24
Finished	Apr 18 02:43:07 PM PDT 24
Peak memory	203132 kb
Host	smart-8613e394-d0f0-40da-a775-c2c73a2e4791
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075612823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.2075612823
Directory	/workspace/27.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3840409100
Short name	T619
Test name
Test status
Simulation time	12918457615 ps
CPU time	102.67 seconds
Started	Apr 18 02:37:03 PM PDT 24
Finished	Apr 18 02:38:46 PM PDT 24
Peak memory	362572 kb
Host	smart-dd0a957e-68e1-445c-b91c-550bc00889df
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840409100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3840409100
Directory	/workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.2087412173
Short name	T483
Test name
Test status
Simulation time	17369509644 ps
CPU time	274.77 seconds
Started	Apr 18 02:37:24 PM PDT 24
Finished	Apr 18 02:41:59 PM PDT 24
Peak memory	332560 kb
Host	smart-503c1577-a7ca-454a-93b3-2a75d07a31f7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087412173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.2087412173
Directory	/workspace/28.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/28.sram_ctrl_alert_test.803602149
Short name	T773
Test name
Test status
Simulation time	73589982 ps
CPU time	0.6 seconds
Started	Apr 18 02:37:40 PM PDT 24
Finished	Apr 18 02:37:40 PM PDT 24
Peak memory	202808 kb
Host	smart-808677b5-fc8b-498d-a1c6-e72da8bbb9fa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803602149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.803602149
Directory	/workspace/28.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.sram_ctrl_executable.4097099815
Short name	T346
Test name
Test status
Simulation time	6875465951 ps
CPU time	484.7 seconds
Started	Apr 18 02:37:23 PM PDT 24
Finished	Apr 18 02:45:28 PM PDT 24
Peak memory	367720 kb
Host	smart-2ca9991d-cb4b-47d4-bb77-4052c73ed684
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097099815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.4097099815
Directory	/workspace/28.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/28.sram_ctrl_lc_escalation.502697494
Short name	T548
Test name
Test status
Simulation time	41572465672 ps
CPU time	68.42 seconds
Started	Apr 18 02:37:18 PM PDT 24
Finished	Apr 18 02:38:26 PM PDT 24
Peak memory	211304 kb
Host	smart-ca604aa7-905e-4103-bad5-08e353095f8c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502697494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_esc alation.502697494
Directory	/workspace/28.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/28.sram_ctrl_max_throughput.3713194977
Short name	T197
Test name
Test status
Simulation time	11647144336 ps
CPU time	21.33 seconds
Started	Apr 18 02:37:18 PM PDT 24
Finished	Apr 18 02:37:39 PM PDT 24
Peak memory	256992 kb
Host	smart-c3b94dd9-d8b6-4d70-9ec1-def602014ad8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713194977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.3713194977
Directory	/workspace/28.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.1589447838
Short name	T594
Test name
Test status
Simulation time	1865168692 ps
CPU time	62.13 seconds
Started	Apr 18 02:37:28 PM PDT 24
Finished	Apr 18 02:38:30 PM PDT 24
Peak memory	211276 kb
Host	smart-6dcaa4c6-621d-401c-8eed-30bab90fa140
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589447838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.1589447838
Directory	/workspace/28.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_walk.969955893
Short name	T706
Test name
Test status
Simulation time	86010170992 ps
CPU time	153.33 seconds
Started	Apr 18 02:37:27 PM PDT 24
Finished	Apr 18 02:40:01 PM PDT 24
Peak memory	203748 kb
Host	smart-024c584b-a8eb-4f00-99ba-ba2caf3be31e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969955893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl _mem_walk.969955893
Directory	/workspace/28.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/28.sram_ctrl_multiple_keys.277003255
Short name	T828
Test name
Test status
Simulation time	23389611407 ps
CPU time	430.48 seconds
Started	Apr 18 02:37:13 PM PDT 24
Finished	Apr 18 02:44:23 PM PDT 24
Peak memory	357508 kb
Host	smart-0c6838e4-899b-46f2-9879-9d9df93dd611
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277003255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multip le_keys.277003255
Directory	/workspace/28.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access.882945548
Short name	T852
Test name
Test status
Simulation time	1551385937 ps
CPU time	9.23 seconds
Started	Apr 18 02:37:18 PM PDT 24
Finished	Apr 18 02:37:28 PM PDT 24
Peak memory	230460 kb
Host	smart-12844ebc-3cc8-457b-b272-a8222f123997
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882945548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s ram_ctrl_partial_access.882945548
Directory	/workspace/28.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.661110522
Short name	T618
Test name
Test status
Simulation time	69322540687 ps
CPU time	378.17 seconds
Started	Apr 18 02:37:18 PM PDT 24
Finished	Apr 18 02:43:36 PM PDT 24
Peak memory	203160 kb
Host	smart-786a0227-d2ed-4674-b93f-f85847a60271
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661110522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.sram_ctrl_partial_access_b2b.661110522
Directory	/workspace/28.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/28.sram_ctrl_ram_cfg.1253890876
Short name	T409
Test name
Test status
Simulation time	1866334666 ps
CPU time	3.47 seconds
Started	Apr 18 02:37:28 PM PDT 24
Finished	Apr 18 02:37:32 PM PDT 24
Peak memory	203028 kb
Host	smart-84d6cfe8-50f1-418a-a27c-1cb72abbf5c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253890876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1253890876
Directory	/workspace/28.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/28.sram_ctrl_regwen.4067343062
Short name	T794
Test name
Test status
Simulation time	16454327688 ps
CPU time	1351.49 seconds
Started	Apr 18 02:37:23 PM PDT 24
Finished	Apr 18 02:59:55 PM PDT 24
Peak memory	378856 kb
Host	smart-cef27c0a-0120-4a1d-b6b9-f235f2befd57
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067343062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.4067343062
Directory	/workspace/28.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/28.sram_ctrl_smoke.4042563803
Short name	T597
Test name
Test status
Simulation time	1170898868 ps
CPU time	18.5 seconds
Started	Apr 18 02:37:14 PM PDT 24
Finished	Apr 18 02:37:33 PM PDT 24
Peak memory	203000 kb
Host	smart-9d97d6b2-32e7-4d9d-847c-32f9346b6e6f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042563803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.4042563803
Directory	/workspace/28.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all.2037423618
Short name	T505
Test name
Test status
Simulation time	1004070470980 ps
CPU time	6184.6 seconds
Started	Apr 18 02:37:46 PM PDT 24
Finished	Apr 18 04:20:51 PM PDT 24
Peak memory	381064 kb
Host	smart-0bd7bedf-590a-48a9-8d5f-be6c9a837b7d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037423618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.2037423618
Directory	/workspace/28.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.375328366
Short name	T798
Test name
Test status
Simulation time	6613101254 ps
CPU time	58.63 seconds
Started	Apr 18 02:37:35 PM PDT 24
Finished	Apr 18 02:38:34 PM PDT 24
Peak memory	211388 kb
Host	smart-9083a2ce-9002-40e9-b38c-67d765a0bc71
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=375328366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.375328366
Directory	/workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.1018419079
Short name	T93
Test name
Test status
Simulation time	6666836261 ps
CPU time	138.44 seconds
Started	Apr 18 02:37:19 PM PDT 24
Finished	Apr 18 02:39:38 PM PDT 24
Peak memory	203148 kb
Host	smart-eb751a6f-58da-44cb-af3f-f052a5a2827a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018419079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.1018419079
Directory	/workspace/28.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3547741242
Short name	T760
Test name
Test status
Simulation time	690251952 ps
CPU time	8.48 seconds
Started	Apr 18 02:37:19 PM PDT 24
Finished	Apr 18 02:37:28 PM PDT 24
Peak memory	223192 kb
Host	smart-da95b308-f7b4-49b5-b6d9-733a0d03103f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547741242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.3547741242
Directory	/workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.884894083
Short name	T591
Test name
Test status
Simulation time	14207861114 ps
CPU time	240.3 seconds
Started	Apr 18 02:37:43 PM PDT 24
Finished	Apr 18 02:41:44 PM PDT 24
Peak memory	373392 kb
Host	smart-9bbf67d0-9b96-4411-88a0-275a1547f2ee
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884894083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 29.sram_ctrl_access_during_key_req.884894083
Directory	/workspace/29.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/29.sram_ctrl_alert_test.3671305935
Short name	T805
Test name
Test status
Simulation time	35655704 ps
CPU time	0.64 seconds
Started	Apr 18 02:37:59 PM PDT 24
Finished	Apr 18 02:38:00 PM PDT 24
Peak memory	202804 kb
Host	smart-4d3bbe35-697d-418a-811c-d1063fca22b0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671305935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.3671305935
Directory	/workspace/29.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.sram_ctrl_bijection.1900034878
Short name	T496
Test name
Test status
Simulation time	11283192409 ps
CPU time	743.59 seconds
Started	Apr 18 02:37:40 PM PDT 24
Finished	Apr 18 02:50:04 PM PDT 24
Peak memory	203308 kb
Host	smart-9c6e0215-af60-49af-8761-b7ad0407c1b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900034878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .1900034878
Directory	/workspace/29.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/29.sram_ctrl_executable.4220405616
Short name	T443
Test name
Test status
Simulation time	14272235463 ps
CPU time	349.65 seconds
Started	Apr 18 02:37:49 PM PDT 24
Finished	Apr 18 02:43:38 PM PDT 24
Peak memory	363696 kb
Host	smart-764e2429-b535-4641-8595-1f74e7fe52d0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220405616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.4220405616
Directory	/workspace/29.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/29.sram_ctrl_lc_escalation.2744519881
Short name	T726
Test name
Test status
Simulation time	13717602416 ps
CPU time	80.59 seconds
Started	Apr 18 02:37:49 PM PDT 24
Finished	Apr 18 02:39:09 PM PDT 24
Peak memory	211316 kb
Host	smart-5a697578-94a6-4af2-aef2-763bf15f0f08
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744519881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.2744519881
Directory	/workspace/29.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/29.sram_ctrl_max_throughput.968558331
Short name	T256
Test name
Test status
Simulation time	1535331408 ps
CPU time	48.6 seconds
Started	Apr 18 02:37:43 PM PDT 24
Finished	Apr 18 02:38:32 PM PDT 24
Peak memory	320564 kb
Host	smart-47534cd5-d571-4e3e-bfa3-f6fb4db2378f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968558331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.sram_ctrl_max_throughput.968558331
Directory	/workspace/29.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2490103042
Short name	T73
Test name
Test status
Simulation time	4803035913 ps
CPU time	71.28 seconds
Started	Apr 18 02:37:52 PM PDT 24
Finished	Apr 18 02:39:04 PM PDT 24
Peak memory	211372 kb
Host	smart-6fff7f3e-e116-4e8f-a77c-8c261c7f8444
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490103042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.2490103042
Directory	/workspace/29.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_walk.2974079994
Short name	T478
Test name
Test status
Simulation time	16414194362 ps
CPU time	244.99 seconds
Started	Apr 18 02:37:49 PM PDT 24
Finished	Apr 18 02:41:55 PM PDT 24
Peak memory	203648 kb
Host	smart-3fb6234f-9769-4c74-bdfe-018276d69ffe
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974079994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.2974079994
Directory	/workspace/29.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/29.sram_ctrl_multiple_keys.2454743010
Short name	T171
Test name
Test status
Simulation time	5176024341 ps
CPU time	826.49 seconds
Started	Apr 18 02:37:39 PM PDT 24
Finished	Apr 18 02:51:26 PM PDT 24
Peak memory	380284 kb
Host	smart-c5f09620-143e-4c50-96dd-f14dd506795d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454743010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.2454743010
Directory	/workspace/29.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access.4215776097
Short name	T176
Test name
Test status
Simulation time	896838202 ps
CPU time	18.82 seconds
Started	Apr 18 02:37:38 PM PDT 24
Finished	Apr 18 02:37:57 PM PDT 24
Peak memory	202944 kb
Host	smart-84894518-28ca-42cb-abd5-94332e4ede08
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215776097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.4215776097
Directory	/workspace/29.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.32322304
Short name	T883
Test name
Test status
Simulation time	28277882088 ps
CPU time	361.37 seconds
Started	Apr 18 02:37:43 PM PDT 24
Finished	Apr 18 02:43:45 PM PDT 24
Peak memory	203084 kb
Host	smart-dd68049a-4c35-430e-85c6-fa7eaa66d453
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32322304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_partial_access_b2b.32322304
Directory	/workspace/29.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/29.sram_ctrl_ram_cfg.2046690849
Short name	T768
Test name
Test status
Simulation time	1348061209 ps
CPU time	3.3 seconds
Started	Apr 18 02:37:46 PM PDT 24
Finished	Apr 18 02:37:50 PM PDT 24
Peak memory	203060 kb
Host	smart-b1c9fa72-a9eb-449c-837e-a4ed850a85a3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046690849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2046690849
Directory	/workspace/29.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/29.sram_ctrl_regwen.3464508585
Short name	T697
Test name
Test status
Simulation time	29240205140 ps
CPU time	722.56 seconds
Started	Apr 18 02:37:49 PM PDT 24
Finished	Apr 18 02:49:52 PM PDT 24
Peak memory	380004 kb
Host	smart-6bcc9277-fd60-4258-a1c8-b1a89de13eb5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464508585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3464508585
Directory	/workspace/29.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/29.sram_ctrl_smoke.2457841476
Short name	T570
Test name
Test status
Simulation time	367822779 ps
CPU time	3.56 seconds
Started	Apr 18 02:37:39 PM PDT 24
Finished	Apr 18 02:37:43 PM PDT 24
Peak memory	202792 kb
Host	smart-6c0fca85-78c6-4d24-b648-9d264b7949dc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457841476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2457841476
Directory	/workspace/29.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all.2918033167
Short name	T224
Test name
Test status
Simulation time	77436070726 ps
CPU time	1719.53 seconds
Started	Apr 18 02:37:51 PM PDT 24
Finished	Apr 18 03:06:31 PM PDT 24
Peak memory	381128 kb
Host	smart-206340fa-ca0e-465e-916c-85db6b5d7ce2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918033167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.2918033167
Directory	/workspace/29.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2704456803
Short name	T398
Test name
Test status
Simulation time	1243469480 ps
CPU time	17.4 seconds
Started	Apr 18 02:37:54 PM PDT 24
Finished	Apr 18 02:38:12 PM PDT 24
Peak memory	211388 kb
Host	smart-e42369f9-199c-4dcf-9d6d-fdfe8f52a264
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2704456803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.2704456803
Directory	/workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3602999493
Short name	T257
Test name
Test status
Simulation time	17935876055 ps
CPU time	304.55 seconds
Started	Apr 18 02:37:38 PM PDT 24
Finished	Apr 18 02:42:43 PM PDT 24
Peak memory	203164 kb
Host	smart-cefdda24-564e-4ade-900e-d63e5c7ba9fd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602999493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3602999493
Directory	/workspace/29.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1835721377
Short name	T148
Test name
Test status
Simulation time	1634500020 ps
CPU time	148.03 seconds
Started	Apr 18 02:37:49 PM PDT 24
Finished	Apr 18 02:40:17 PM PDT 24
Peak memory	371664 kb
Host	smart-40c3211f-0374-4243-b04c-adce460f7e49
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835721377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1835721377
Directory	/workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.2035917452
Short name	T383
Test name
Test status
Simulation time	20567370402 ps
CPU time	855.3 seconds
Started	Apr 18 02:30:51 PM PDT 24
Finished	Apr 18 02:45:07 PM PDT 24
Peak memory	381120 kb
Host	smart-8947118e-8f1e-444c-ae44-00ce0e6a81c5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035917452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.2035917452
Directory	/workspace/3.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/3.sram_ctrl_alert_test.3521851273
Short name	T451
Test name
Test status
Simulation time	24345563 ps
CPU time	0.69 seconds
Started	Apr 18 02:30:52 PM PDT 24
Finished	Apr 18 02:30:54 PM PDT 24
Peak memory	202600 kb
Host	smart-5ff9c70a-6f4c-4678-b263-41de74f1eb73
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521851273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.3521851273
Directory	/workspace/3.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.sram_ctrl_bijection.1431282906
Short name	T208
Test name
Test status
Simulation time	51329666138 ps
CPU time	1117.39 seconds
Started	Apr 18 02:30:52 PM PDT 24
Finished	Apr 18 02:49:30 PM PDT 24
Peak memory	203156 kb
Host	smart-1763ba81-e3ec-49be-a129-fee860513300
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431282906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 1431282906
Directory	/workspace/3.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/3.sram_ctrl_executable.2091017317
Short name	T454
Test name
Test status
Simulation time	19492170526 ps
CPU time	448.94 seconds
Started	Apr 18 02:30:52 PM PDT 24
Finished	Apr 18 02:38:21 PM PDT 24
Peak memory	376876 kb
Host	smart-fc418a1a-da03-4b21-98c0-20a83b4a1e30
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091017317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.2091017317
Directory	/workspace/3.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/3.sram_ctrl_lc_escalation.2364463244
Short name	T652
Test name
Test status
Simulation time	30233269600 ps
CPU time	54.85 seconds
Started	Apr 18 02:30:53 PM PDT 24
Finished	Apr 18 02:31:48 PM PDT 24
Peak memory	211256 kb
Host	smart-888704a0-d217-4fb1-9d6d-bbfa178453c8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364463244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.2364463244
Directory	/workspace/3.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/3.sram_ctrl_max_throughput.2927829462
Short name	T765
Test name
Test status
Simulation time	1409962711 ps
CPU time	8.98 seconds
Started	Apr 18 02:30:52 PM PDT 24
Finished	Apr 18 02:31:01 PM PDT 24
Peak memory	220428 kb
Host	smart-6b82cf0d-3a1f-4c81-89ff-4ddda0ca8402
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927829462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.2927829462
Directory	/workspace/3.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3948200433
Short name	T477
Test name
Test status
Simulation time	10130775842 ps
CPU time	76.89 seconds
Started	Apr 18 02:30:53 PM PDT 24
Finished	Apr 18 02:32:10 PM PDT 24
Peak memory	211352 kb
Host	smart-f819fcb1-fce3-4ae7-9bdd-ace172746b87
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948200433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.3948200433
Directory	/workspace/3.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_walk.813987275
Short name	T663
Test name
Test status
Simulation time	49192338789 ps
CPU time	140.71 seconds
Started	Apr 18 02:30:53 PM PDT 24
Finished	Apr 18 02:33:14 PM PDT 24
Peak memory	203188 kb
Host	smart-cf17083e-39fd-432c-b65f-4699988aa58e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813987275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ mem_walk.813987275
Directory	/workspace/3.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/3.sram_ctrl_multiple_keys.2751061357
Short name	T153
Test name
Test status
Simulation time	6517112930 ps
CPU time	276.22 seconds
Started	Apr 18 02:30:55 PM PDT 24
Finished	Apr 18 02:35:31 PM PDT 24
Peak memory	344240 kb
Host	smart-ca7dff87-6168-4294-bafb-7dfd8d0751dd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751061357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.2751061357
Directory	/workspace/3.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access.2502636440
Short name	T431
Test name
Test status
Simulation time	1004261482 ps
CPU time	25.73 seconds
Started	Apr 18 02:30:52 PM PDT 24
Finished	Apr 18 02:31:18 PM PDT 24
Peak memory	276352 kb
Host	smart-de3b0b3f-e0cd-49a5-b879-7d85d8047466
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502636440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.2502636440
Directory	/workspace/3.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2092508350
Short name	T906
Test name
Test status
Simulation time	23207419941 ps
CPU time	520.19 seconds
Started	Apr 18 02:30:51 PM PDT 24
Finished	Apr 18 02:39:32 PM PDT 24
Peak memory	203200 kb
Host	smart-0b49ca83-9982-4a5e-b355-53e01021a1e6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092508350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.2092508350
Directory	/workspace/3.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/3.sram_ctrl_ram_cfg.3505264688
Short name	T276
Test name
Test status
Simulation time	360527328 ps
CPU time	3.22 seconds
Started	Apr 18 02:30:52 PM PDT 24
Finished	Apr 18 02:30:56 PM PDT 24
Peak memory	203020 kb
Host	smart-0ea7f44d-f447-475e-8001-03bd809509b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505264688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3505264688
Directory	/workspace/3.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/3.sram_ctrl_regwen.2521079126
Short name	T686
Test name
Test status
Simulation time	2829515115 ps
CPU time	240.68 seconds
Started	Apr 18 02:30:52 PM PDT 24
Finished	Apr 18 02:34:53 PM PDT 24
Peak memory	374812 kb
Host	smart-128a2f6a-6840-4edf-8205-63db8047d5da
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521079126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2521079126
Directory	/workspace/3.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/3.sram_ctrl_sec_cm.3924896261
Short name	T36
Test name
Test status
Simulation time	268815261 ps
CPU time	3.17 seconds
Started	Apr 18 02:30:54 PM PDT 24
Finished	Apr 18 02:30:58 PM PDT 24
Peak memory	222816 kb
Host	smart-f9fa62ca-6947-4798-b2c8-cc24fadaca67
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924896261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.3924896261
Directory	/workspace/3.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.sram_ctrl_smoke.1309645478
Short name	T253
Test name
Test status
Simulation time	1215584940 ps
CPU time	96.5 seconds
Started	Apr 18 02:30:50 PM PDT 24
Finished	Apr 18 02:32:27 PM PDT 24
Peak memory	349144 kb
Host	smart-3fd8d8a6-083e-4604-ab5e-26c37d8c625d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309645478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1309645478
Directory	/workspace/3.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all.2169762308
Short name	T255
Test name
Test status
Simulation time	133179347902 ps
CPU time	3080.66 seconds
Started	Apr 18 02:30:51 PM PDT 24
Finished	Apr 18 03:22:13 PM PDT 24
Peak memory	378992 kb
Host	smart-5f959bb9-e638-4536-af42-a1c7f54bdb2d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169762308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.2169762308
Directory	/workspace/3.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.84464189
Short name	T517
Test name
Test status
Simulation time	2914454253 ps
CPU time	46.18 seconds
Started	Apr 18 02:30:55 PM PDT 24
Finished	Apr 18 02:31:42 PM PDT 24
Peak memory	211328 kb
Host	smart-f04db4fb-6b25-4697-b0d8-18fa5f8687ac
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=84464189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.84464189
Directory	/workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_pipeline.181374683
Short name	T580
Test name
Test status
Simulation time	3086629767 ps
CPU time	164.29 seconds
Started	Apr 18 02:30:51 PM PDT 24
Finished	Apr 18 02:33:36 PM PDT 24
Peak memory	203076 kb
Host	smart-775a29d6-012b-4227-b8eb-a445d3e2cac4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181374683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_stress_pipeline.181374683
Directory	/workspace/3.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1227974761
Short name	T630
Test name
Test status
Simulation time	4188725039 ps
CPU time	55.9 seconds
Started	Apr 18 02:30:50 PM PDT 24
Finished	Apr 18 02:31:46 PM PDT 24
Peak memory	326636 kb
Host	smart-95d55e84-55cf-420f-88f6-0f7564acaeff
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227974761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1227974761
Directory	/workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2936880185
Short name	T441
Test name
Test status
Simulation time	9478136805 ps
CPU time	1032.65 seconds
Started	Apr 18 02:38:09 PM PDT 24
Finished	Apr 18 02:55:22 PM PDT 24
Peak memory	379036 kb
Host	smart-5930efd1-08a2-4a8d-a850-f6e951dddd31
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936880185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.2936880185
Directory	/workspace/30.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/30.sram_ctrl_alert_test.392943515
Short name	T23
Test name
Test status
Simulation time	69965027 ps
CPU time	0.63 seconds
Started	Apr 18 02:38:19 PM PDT 24
Finished	Apr 18 02:38:20 PM PDT 24
Peak memory	202844 kb
Host	smart-60ae40fc-e59b-45d8-8f1c-f795a1c6c538
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392943515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.392943515
Directory	/workspace/30.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.sram_ctrl_bijection.1436223481
Short name	T475
Test name
Test status
Simulation time	71246797378 ps
CPU time	1495.83 seconds
Started	Apr 18 02:38:03 PM PDT 24
Finished	Apr 18 03:02:59 PM PDT 24
Peak memory	203492 kb
Host	smart-83ef1435-67a8-4e06-9ee9-4e21555514e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436223481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .1436223481
Directory	/workspace/30.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/30.sram_ctrl_executable.1042980477
Short name	T380
Test name
Test status
Simulation time	18329992462 ps
CPU time	611.73 seconds
Started	Apr 18 02:38:13 PM PDT 24
Finished	Apr 18 02:48:25 PM PDT 24
Peak memory	372900 kb
Host	smart-dc741c5a-2540-43d2-83ca-6ec6fc8bf0fe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042980477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.1042980477
Directory	/workspace/30.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/30.sram_ctrl_lc_escalation.681385043
Short name	T912
Test name
Test status
Simulation time	68524469204 ps
CPU time	86.46 seconds
Started	Apr 18 02:38:07 PM PDT 24
Finished	Apr 18 02:39:34 PM PDT 24
Peak memory	203148 kb
Host	smart-a067e9e6-04cd-4181-91f9-bf339a5984a7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681385043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_esc alation.681385043
Directory	/workspace/30.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/30.sram_ctrl_max_throughput.4249344261
Short name	T482
Test name
Test status
Simulation time	1505453886 ps
CPU time	69.44 seconds
Started	Apr 18 02:38:05 PM PDT 24
Finished	Apr 18 02:39:14 PM PDT 24
Peak memory	321584 kb
Host	smart-dce87c3b-9fd0-47c5-8907-fad59842ba68
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249344261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.4249344261
Directory	/workspace/30.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1453476190
Short name	T512
Test name
Test status
Simulation time	3304263106 ps
CPU time	121.8 seconds
Started	Apr 18 02:38:15 PM PDT 24
Finished	Apr 18 02:40:17 PM PDT 24
Peak memory	211296 kb
Host	smart-cbdf2f83-c581-4582-80e4-7ded24c70a6b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453476190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.1453476190
Directory	/workspace/30.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_walk.91049558
Short name	T445
Test name
Test status
Simulation time	127617439627 ps
CPU time	147.87 seconds
Started	Apr 18 02:38:12 PM PDT 24
Finished	Apr 18 02:40:40 PM PDT 24
Peak memory	203192 kb
Host	smart-59fed198-f9d5-47c3-b0bb-784a23ed1970
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91049558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ mem_walk.91049558
Directory	/workspace/30.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/30.sram_ctrl_multiple_keys.2489951503
Short name	T779
Test name
Test status
Simulation time	9778041720 ps
CPU time	1139.48 seconds
Started	Apr 18 02:38:00 PM PDT 24
Finished	Apr 18 02:57:00 PM PDT 24
Peak memory	377852 kb
Host	smart-aa54dc9d-6da3-4b1c-bd0e-7cc2a44f227f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489951503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.2489951503
Directory	/workspace/30.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access.2386060104
Short name	T589
Test name
Test status
Simulation time	875159422 ps
CPU time	23.07 seconds
Started	Apr 18 02:38:05 PM PDT 24
Finished	Apr 18 02:38:28 PM PDT 24
Peak memory	274256 kb
Host	smart-2b351d66-ee00-49fe-9c89-3fa415393f7d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386060104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.2386060104
Directory	/workspace/30.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3378356273
Short name	T128
Test name
Test status
Simulation time	32076548928 ps
CPU time	356.02 seconds
Started	Apr 18 02:38:02 PM PDT 24
Finished	Apr 18 02:43:58 PM PDT 24
Peak memory	203148 kb
Host	smart-ce5e0ecc-683c-4727-bb0e-141b13778584
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378356273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3378356273
Directory	/workspace/30.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/30.sram_ctrl_ram_cfg.1461895519
Short name	T363
Test name
Test status
Simulation time	351462788 ps
CPU time	3.31 seconds
Started	Apr 18 02:38:14 PM PDT 24
Finished	Apr 18 02:38:17 PM PDT 24
Peak memory	203084 kb
Host	smart-73c90f84-5d76-497b-82a4-1759880e7bbd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461895519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1461895519
Directory	/workspace/30.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/30.sram_ctrl_regwen.2816958583
Short name	T26
Test name
Test status
Simulation time	4215700893 ps
CPU time	186.8 seconds
Started	Apr 18 02:38:14 PM PDT 24
Finished	Apr 18 02:41:21 PM PDT 24
Peak memory	326320 kb
Host	smart-dd5184a9-799b-4b07-9ac4-2617e810c1e7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816958583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2816958583
Directory	/workspace/30.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/30.sram_ctrl_smoke.906278610
Short name	T324
Test name
Test status
Simulation time	971850323 ps
CPU time	104 seconds
Started	Apr 18 02:37:58 PM PDT 24
Finished	Apr 18 02:39:42 PM PDT 24
Peak memory	368496 kb
Host	smart-7798eccc-57e2-46af-9946-38a46e233fe9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906278610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.906278610
Directory	/workspace/30.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all.3676561370
Short name	T616
Test name
Test status
Simulation time	1349553852919 ps
CPU time	6511.43 seconds
Started	Apr 18 02:38:20 PM PDT 24
Finished	Apr 18 04:26:53 PM PDT 24
Peak memory	383136 kb
Host	smart-b0e178e7-eecc-4af8-9afc-e82c27cae0b9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676561370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.3676561370
Directory	/workspace/30.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2145681209
Short name	T664
Test name
Test status
Simulation time	1935314245 ps
CPU time	189.2 seconds
Started	Apr 18 02:38:14 PM PDT 24
Finished	Apr 18 02:41:24 PM PDT 24
Peak memory	372636 kb
Host	smart-975db71c-46fb-4609-9741-75091cbd1e7d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2145681209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.2145681209
Directory	/workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1389204564
Short name	T833
Test name
Test status
Simulation time	3709069757 ps
CPU time	197.79 seconds
Started	Apr 18 02:38:03 PM PDT 24
Finished	Apr 18 02:41:21 PM PDT 24
Peak memory	203124 kb
Host	smart-211bcbbb-88ed-4ef3-8fca-421c6b2f4dba
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389204564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.1389204564
Directory	/workspace/30.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3678571997
Short name	T263
Test name
Test status
Simulation time	3690889327 ps
CPU time	59.33 seconds
Started	Apr 18 02:38:10 PM PDT 24
Finished	Apr 18 02:39:10 PM PDT 24
Peak memory	306764 kb
Host	smart-10ae6576-1589-4dcf-9566-8ce7a5354b62
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678571997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.3678571997
Directory	/workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.652396392
Short name	T587
Test name
Test status
Simulation time	23479348328 ps
CPU time	261.14 seconds
Started	Apr 18 02:38:29 PM PDT 24
Finished	Apr 18 02:42:51 PM PDT 24
Peak memory	371704 kb
Host	smart-15750052-c41e-4c16-b142-fdea91683df4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652396392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 31.sram_ctrl_access_during_key_req.652396392
Directory	/workspace/31.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/31.sram_ctrl_alert_test.2599821696
Short name	T348
Test name
Test status
Simulation time	14202985 ps
CPU time	0.65 seconds
Started	Apr 18 02:38:41 PM PDT 24
Finished	Apr 18 02:38:42 PM PDT 24
Peak memory	202792 kb
Host	smart-056f282a-0b4c-4dda-adac-4a838f1d6bb2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599821696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2599821696
Directory	/workspace/31.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.sram_ctrl_bijection.1053980901
Short name	T460
Test name
Test status
Simulation time	32798498326 ps
CPU time	1061.96 seconds
Started	Apr 18 02:38:24 PM PDT 24
Finished	Apr 18 02:56:06 PM PDT 24
Peak memory	203344 kb
Host	smart-e9e31f61-15ed-4fe3-a756-42635042de36
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053980901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .1053980901
Directory	/workspace/31.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/31.sram_ctrl_executable.613754244
Short name	T528
Test name
Test status
Simulation time	7652683585 ps
CPU time	1402.26 seconds
Started	Apr 18 02:38:35 PM PDT 24
Finished	Apr 18 03:01:58 PM PDT 24
Peak memory	380996 kb
Host	smart-f44134b3-bafd-4595-bae5-3505fe5c9cff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613754244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executabl e.613754244
Directory	/workspace/31.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/31.sram_ctrl_lc_escalation.3120529701
Short name	T427
Test name
Test status
Simulation time	17769861045 ps
CPU time	52.08 seconds
Started	Apr 18 02:38:33 PM PDT 24
Finished	Apr 18 02:39:25 PM PDT 24
Peak memory	203132 kb
Host	smart-1942d376-8789-43ef-b1da-d2d71231e8ff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120529701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.3120529701
Directory	/workspace/31.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/31.sram_ctrl_max_throughput.2354765295
Short name	T657
Test name
Test status
Simulation time	2533367423 ps
CPU time	122.3 seconds
Started	Apr 18 02:38:31 PM PDT 24
Finished	Apr 18 02:40:33 PM PDT 24
Peak memory	364664 kb
Host	smart-58645fd6-6ad0-49ac-bdc0-b04e813bcd81
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354765295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.2354765295
Directory	/workspace/31.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2140143021
Short name	T207
Test name
Test status
Simulation time	1618106724 ps
CPU time	118.79 seconds
Started	Apr 18 02:38:35 PM PDT 24
Finished	Apr 18 02:40:34 PM PDT 24
Peak memory	211288 kb
Host	smart-dc2d97e6-acad-41e8-b948-c17e0e75e0c0
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140143021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.2140143021
Directory	/workspace/31.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_walk.3575119763
Short name	T825
Test name
Test status
Simulation time	16422262616 ps
CPU time	240.86 seconds
Started	Apr 18 02:38:36 PM PDT 24
Finished	Apr 18 02:42:38 PM PDT 24
Peak memory	203716 kb
Host	smart-ae87cbc9-0473-4b84-b3f6-e1295ab25177
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575119763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.3575119763
Directory	/workspace/31.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/31.sram_ctrl_multiple_keys.1736261356
Short name	T708
Test name
Test status
Simulation time	84712555898 ps
CPU time	212 seconds
Started	Apr 18 02:38:19 PM PDT 24
Finished	Apr 18 02:41:51 PM PDT 24
Peak memory	347932 kb
Host	smart-4507db0e-3977-4e4f-bc97-bea0559ca40f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736261356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.1736261356
Directory	/workspace/31.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access.685108390
Short name	T221
Test name
Test status
Simulation time	1570419799 ps
CPU time	8.48 seconds
Started	Apr 18 02:38:27 PM PDT 24
Finished	Apr 18 02:38:36 PM PDT 24
Peak memory	203028 kb
Host	smart-88455942-93b8-4caf-8a18-a21c0329b383
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685108390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.s ram_ctrl_partial_access.685108390
Directory	/workspace/31.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3397777513
Short name	T576
Test name
Test status
Simulation time	24491846167 ps
CPU time	287.21 seconds
Started	Apr 18 02:38:27 PM PDT 24
Finished	Apr 18 02:43:15 PM PDT 24
Peak memory	203168 kb
Host	smart-12d851c5-3fd1-449f-9a4f-52eaa515bad6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397777513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.3397777513
Directory	/workspace/31.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/31.sram_ctrl_ram_cfg.1753267670
Short name	T240
Test name
Test status
Simulation time	680541651 ps
CPU time	3.26 seconds
Started	Apr 18 02:38:36 PM PDT 24
Finished	Apr 18 02:38:40 PM PDT 24
Peak memory	203052 kb
Host	smart-57e42d75-9f60-46b2-b23e-52e2d305d69a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753267670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1753267670
Directory	/workspace/31.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/31.sram_ctrl_regwen.3971326131
Short name	T624
Test name
Test status
Simulation time	259618875335 ps
CPU time	1252 seconds
Started	Apr 18 02:38:38 PM PDT 24
Finished	Apr 18 02:59:30 PM PDT 24
Peak memory	380032 kb
Host	smart-e6b013cb-0a3d-4e52-8a8e-092dbe174b9d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971326131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3971326131
Directory	/workspace/31.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/31.sram_ctrl_smoke.1632732596
Short name	T323
Test name
Test status
Simulation time	1457583021 ps
CPU time	21.44 seconds
Started	Apr 18 02:38:20 PM PDT 24
Finished	Apr 18 02:38:42 PM PDT 24
Peak memory	271792 kb
Host	smart-bad51f88-977a-4be3-bd73-0f8dc143a178
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632732596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1632732596
Directory	/workspace/31.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all.4097558087
Short name	T378
Test name
Test status
Simulation time	165649019189 ps
CPU time	3560.74 seconds
Started	Apr 18 02:38:41 PM PDT 24
Finished	Apr 18 03:38:03 PM PDT 24
Peak memory	382084 kb
Host	smart-f2737139-8942-40ba-b067-f0993dce2970
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097558087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.4097558087
Directory	/workspace/31.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4125556798
Short name	T863
Test name
Test status
Simulation time	973187853 ps
CPU time	7.85 seconds
Started	Apr 18 02:38:36 PM PDT 24
Finished	Apr 18 02:38:44 PM PDT 24
Peak memory	211308 kb
Host	smart-7b4269e0-9096-4b29-a842-c93095fefd09
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4125556798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.4125556798
Directory	/workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.692120434
Short name	T173
Test name
Test status
Simulation time	4218140898 ps
CPU time	293.81 seconds
Started	Apr 18 02:38:27 PM PDT 24
Finished	Apr 18 02:43:21 PM PDT 24
Peak memory	203112 kb
Host	smart-9a717bdd-5355-4eb3-9ce1-ac8c9059e342
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692120434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .sram_ctrl_stress_pipeline.692120434
Directory	/workspace/31.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1552425337
Short name	T804
Test name
Test status
Simulation time	744244271 ps
CPU time	12.93 seconds
Started	Apr 18 02:38:35 PM PDT 24
Finished	Apr 18 02:38:49 PM PDT 24
Peak memory	237056 kb
Host	smart-adda36ea-674f-4e72-9458-19aa2be2acb2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552425337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1552425337
Directory	/workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3668574480
Short name	T437
Test name
Test status
Simulation time	268689517564 ps
CPU time	853.5 seconds
Started	Apr 18 02:38:56 PM PDT 24
Finished	Apr 18 02:53:10 PM PDT 24
Peak memory	379184 kb
Host	smart-2e3a6e40-8630-4150-b7a8-7b01f28ec8e3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668574480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.3668574480
Directory	/workspace/32.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/32.sram_ctrl_alert_test.1852192888
Short name	T408
Test name
Test status
Simulation time	12129758 ps
CPU time	0.65 seconds
Started	Apr 18 02:39:06 PM PDT 24
Finished	Apr 18 02:39:07 PM PDT 24
Peak memory	202840 kb
Host	smart-16b155c8-185b-4cd6-8fdb-f49b89b16fd7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852192888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.1852192888
Directory	/workspace/32.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.sram_ctrl_bijection.1838888260
Short name	T519
Test name
Test status
Simulation time	88885367750 ps
CPU time	1393.98 seconds
Started	Apr 18 02:38:46 PM PDT 24
Finished	Apr 18 03:02:01 PM PDT 24
Peak memory	203020 kb
Host	smart-7d1f6a3b-9311-467c-8145-3f7d09b23ae3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838888260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .1838888260
Directory	/workspace/32.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/32.sram_ctrl_executable.2641242428
Short name	T756
Test name
Test status
Simulation time	114820416159 ps
CPU time	2084.27 seconds
Started	Apr 18 02:38:57 PM PDT 24
Finished	Apr 18 03:13:42 PM PDT 24
Peak memory	377916 kb
Host	smart-3d360a66-a5ac-4bd8-b13f-f3960b030640
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641242428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.2641242428
Directory	/workspace/32.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/32.sram_ctrl_lc_escalation.3479300460
Short name	T107
Test name
Test status
Simulation time	33651528445 ps
CPU time	45.91 seconds
Started	Apr 18 02:38:57 PM PDT 24
Finished	Apr 18 02:39:43 PM PDT 24
Peak memory	211328 kb
Host	smart-3bd49271-d787-472a-b51f-86cc875509d3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479300460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.3479300460
Directory	/workspace/32.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/32.sram_ctrl_max_throughput.1737215498
Short name	T806
Test name
Test status
Simulation time	1532303944 ps
CPU time	60.3 seconds
Started	Apr 18 02:38:56 PM PDT 24
Finished	Apr 18 02:39:57 PM PDT 24
Peak memory	345112 kb
Host	smart-0cf912a4-7122-45a7-b452-6372dd081098
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737215498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.1737215498
Directory	/workspace/32.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3044600452
Short name	T210
Test name
Test status
Simulation time	5096460627 ps
CPU time	76.35 seconds
Started	Apr 18 02:39:39 PM PDT 24
Finished	Apr 18 02:40:56 PM PDT 24
Peak memory	211260 kb
Host	smart-a2bfaaae-3dee-4f43-ade7-fcf0a117feea
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044600452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.3044600452
Directory	/workspace/32.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_walk.659881511
Short name	T147
Test name
Test status
Simulation time	14334656386 ps
CPU time	282.88 seconds
Started	Apr 18 02:39:03 PM PDT 24
Finished	Apr 18 02:43:46 PM PDT 24
Peak memory	203160 kb
Host	smart-d04bca12-07ca-4006-b20b-7f84ddb35071
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659881511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl _mem_walk.659881511
Directory	/workspace/32.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/32.sram_ctrl_multiple_keys.3060143237
Short name	T508
Test name
Test status
Simulation time	9927955257 ps
CPU time	517.09 seconds
Started	Apr 18 02:38:46 PM PDT 24
Finished	Apr 18 02:47:23 PM PDT 24
Peak memory	357276 kb
Host	smart-fb9f587b-5774-4786-ac2e-07bbd16866ac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060143237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.3060143237
Directory	/workspace/32.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access.2691538714
Short name	T355
Test name
Test status
Simulation time	1406772616 ps
CPU time	154.79 seconds
Started	Apr 18 02:38:48 PM PDT 24
Finished	Apr 18 02:41:23 PM PDT 24
Peak memory	368628 kb
Host	smart-f3a5a5e5-437e-4a46-be5e-68850690de21
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691538714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.2691538714
Directory	/workspace/32.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4139341272
Short name	T885
Test name
Test status
Simulation time	3922649016 ps
CPU time	162.71 seconds
Started	Apr 18 02:38:51 PM PDT 24
Finished	Apr 18 02:41:34 PM PDT 24
Peak memory	203084 kb
Host	smart-e0b145c4-969d-4174-9899-89c102219a6d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139341272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.4139341272
Directory	/workspace/32.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/32.sram_ctrl_ram_cfg.2872401059
Short name	T239
Test name
Test status
Simulation time	353882396 ps
CPU time	3.33 seconds
Started	Apr 18 02:38:56 PM PDT 24
Finished	Apr 18 02:39:00 PM PDT 24
Peak memory	203040 kb
Host	smart-ec91d2c1-e83f-41bc-af31-54cdd8ee7fc6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872401059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2872401059
Directory	/workspace/32.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/32.sram_ctrl_regwen.2717754865
Short name	T929
Test name
Test status
Simulation time	3701186971 ps
CPU time	66.73 seconds
Started	Apr 18 02:38:57 PM PDT 24
Finished	Apr 18 02:40:04 PM PDT 24
Peak memory	319504 kb
Host	smart-72f138b8-2f71-4520-b6db-a3323d8d48a2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717754865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2717754865
Directory	/workspace/32.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/32.sram_ctrl_smoke.1539279706
Short name	T277
Test name
Test status
Simulation time	940142076 ps
CPU time	48.91 seconds
Started	Apr 18 02:38:46 PM PDT 24
Finished	Apr 18 02:39:35 PM PDT 24
Peak memory	314324 kb
Host	smart-45879cff-822d-4e27-9694-f4b0664f2f39
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539279706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1539279706
Directory	/workspace/32.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3393949470
Short name	T933
Test name
Test status
Simulation time	1450443252 ps
CPU time	17.13 seconds
Started	Apr 18 02:39:06 PM PDT 24
Finished	Apr 18 02:39:23 PM PDT 24
Peak memory	211248 kb
Host	smart-a8ac91f0-deaf-4e7e-b795-68e1df3abd50
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3393949470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3393949470
Directory	/workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.45914553
Short name	T278
Test name
Test status
Simulation time	3728756781 ps
CPU time	276.88 seconds
Started	Apr 18 02:38:46 PM PDT 24
Finished	Apr 18 02:43:23 PM PDT 24
Peak memory	203048 kb
Host	smart-46663f81-c559-407e-b704-79640a2676f4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45914553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_stress_pipeline.45914553
Directory	/workspace/32.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.688487495
Short name	T343
Test name
Test status
Simulation time	724669183 ps
CPU time	11.64 seconds
Started	Apr 18 02:38:57 PM PDT 24
Finished	Apr 18 02:39:09 PM PDT 24
Peak memory	236764 kb
Host	smart-952c890f-939e-4bf3-98df-bd763d19099e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688487495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_throughput_w_partial_write.688487495
Directory	/workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2107409931
Short name	T412
Test name
Test status
Simulation time	12620772746 ps
CPU time	850 seconds
Started	Apr 18 02:39:16 PM PDT 24
Finished	Apr 18 02:53:26 PM PDT 24
Peak memory	375856 kb
Host	smart-abbfcae4-6c00-4210-9db7-9c2525dbab12
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107409931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.2107409931
Directory	/workspace/33.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/33.sram_ctrl_alert_test.2587848588
Short name	T339
Test name
Test status
Simulation time	21874536 ps
CPU time	0.62 seconds
Started	Apr 18 02:39:25 PM PDT 24
Finished	Apr 18 02:39:26 PM PDT 24
Peak memory	202632 kb
Host	smart-1db87374-953c-4d64-9739-649738065c0b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587848588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.2587848588
Directory	/workspace/33.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.sram_ctrl_bijection.4029480001
Short name	T158
Test name
Test status
Simulation time	689571393104 ps
CPU time	2857.55 seconds
Started	Apr 18 02:39:11 PM PDT 24
Finished	Apr 18 03:26:49 PM PDT 24
Peak memory	203276 kb
Host	smart-a7d9d76d-3bbc-49c0-96c3-86bd49c61a2a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029480001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .4029480001
Directory	/workspace/33.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/33.sram_ctrl_executable.3765863440
Short name	T504
Test name
Test status
Simulation time	926353981 ps
CPU time	19.57 seconds
Started	Apr 18 02:39:17 PM PDT 24
Finished	Apr 18 02:39:37 PM PDT 24
Peak memory	239368 kb
Host	smart-2e9bfd65-14de-470a-b2e1-a1d408e9db54
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765863440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.3765863440
Directory	/workspace/33.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/33.sram_ctrl_lc_escalation.2784872151
Short name	T923
Test name
Test status
Simulation time	6658666789 ps
CPU time	19.52 seconds
Started	Apr 18 02:39:15 PM PDT 24
Finished	Apr 18 02:39:34 PM PDT 24
Peak memory	215192 kb
Host	smart-47cfb62c-26f4-408a-8835-9beca6986216
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784872151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.2784872151
Directory	/workspace/33.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/33.sram_ctrl_max_throughput.883164524
Short name	T896
Test name
Test status
Simulation time	1479316316 ps
CPU time	54.23 seconds
Started	Apr 18 02:39:15 PM PDT 24
Finished	Apr 18 02:40:09 PM PDT 24
Peak memory	295956 kb
Host	smart-f0a12e1a-6362-4d38-8951-2214294dbd11
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883164524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.sram_ctrl_max_throughput.883164524
Directory	/workspace/33.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3476718902
Short name	T321
Test name
Test status
Simulation time	4806786341 ps
CPU time	140.97 seconds
Started	Apr 18 02:39:20 PM PDT 24
Finished	Apr 18 02:41:41 PM PDT 24
Peak memory	211300 kb
Host	smart-8fd914e4-4bb2-46eb-9803-2eb922e5a047
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476718902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.3476718902
Directory	/workspace/33.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_walk.3350713856
Short name	T137
Test name
Test status
Simulation time	7307284088 ps
CPU time	126.06 seconds
Started	Apr 18 02:39:19 PM PDT 24
Finished	Apr 18 02:41:26 PM PDT 24
Peak memory	203528 kb
Host	smart-8514e245-9134-41aa-b22f-1136edb0e5b1
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350713856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.3350713856
Directory	/workspace/33.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/33.sram_ctrl_multiple_keys.2176710100
Short name	T588
Test name
Test status
Simulation time	21376895949 ps
CPU time	757.44 seconds
Started	Apr 18 02:39:05 PM PDT 24
Finished	Apr 18 02:51:43 PM PDT 24
Peak memory	379920 kb
Host	smart-e154053e-fb0b-46c7-9cc8-94e850f4a274
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176710100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.2176710100
Directory	/workspace/33.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access.3415459377
Short name	T692
Test name
Test status
Simulation time	1321269010 ps
CPU time	22.72 seconds
Started	Apr 18 02:39:11 PM PDT 24
Finished	Apr 18 02:39:34 PM PDT 24
Peak memory	203044 kb
Host	smart-fc538c0a-cce9-4525-b747-8f9804ea4556
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415459377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.3415459377
Directory	/workspace/33.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2539975465
Short name	T177
Test name
Test status
Simulation time	19071981741 ps
CPU time	453.65 seconds
Started	Apr 18 02:39:16 PM PDT 24
Finished	Apr 18 02:46:50 PM PDT 24
Peak memory	203192 kb
Host	smart-67fa8a5c-4dfc-489f-a8a4-0854fd93c052
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539975465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.2539975465
Directory	/workspace/33.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/33.sram_ctrl_ram_cfg.2993969101
Short name	T320
Test name
Test status
Simulation time	1350377405 ps
CPU time	3.63 seconds
Started	Apr 18 02:39:19 PM PDT 24
Finished	Apr 18 02:39:23 PM PDT 24
Peak memory	203044 kb
Host	smart-fbe20e0c-8ac2-4475-b687-ad98af55c7d8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993969101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2993969101
Directory	/workspace/33.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/33.sram_ctrl_smoke.2136802088
Short name	T617
Test name
Test status
Simulation time	687676941 ps
CPU time	9.12 seconds
Started	Apr 18 02:39:07 PM PDT 24
Finished	Apr 18 02:39:17 PM PDT 24
Peak memory	222340 kb
Host	smart-175ccf4b-ea8e-4cdd-9445-09541704c882
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136802088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2136802088
Directory	/workspace/33.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all.977134789
Short name	T700
Test name
Test status
Simulation time	529062499624 ps
CPU time	6005.87 seconds
Started	Apr 18 02:39:25 PM PDT 24
Finished	Apr 18 04:19:32 PM PDT 24
Peak memory	390300 kb
Host	smart-840f4c27-3d66-405f-bd8d-9d98a0d20093
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977134789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_stress_all.977134789
Directory	/workspace/33.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1468242096
Short name	T832
Test name
Test status
Simulation time	1190497159 ps
CPU time	42.15 seconds
Started	Apr 18 02:39:25 PM PDT 24
Finished	Apr 18 02:40:08 PM PDT 24
Peak memory	211252 kb
Host	smart-c304cecf-de34-4f5a-816f-c8b86e415cfa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1468242096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1468242096
Directory	/workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1766363071
Short name	T872
Test name
Test status
Simulation time	33645998435 ps
CPU time	365.78 seconds
Started	Apr 18 02:39:11 PM PDT 24
Finished	Apr 18 02:45:17 PM PDT 24
Peak memory	203176 kb
Host	smart-78fb859d-58ca-44b2-8b10-046d68929088
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766363071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.1766363071
Directory	/workspace/33.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2295083295
Short name	T164
Test name
Test status
Simulation time	2849857296 ps
CPU time	10.3 seconds
Started	Apr 18 02:39:15 PM PDT 24
Finished	Apr 18 02:39:26 PM PDT 24
Peak memory	235308 kb
Host	smart-f0b57032-d614-42a7-aaeb-95f81e262ef4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295083295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.2295083295
Directory	/workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3411615539
Short name	T586
Test name
Test status
Simulation time	4941750976 ps
CPU time	113.21 seconds
Started	Apr 18 02:39:41 PM PDT 24
Finished	Apr 18 02:41:35 PM PDT 24
Peak memory	239408 kb
Host	smart-7f5b35fe-3185-4bc3-8aa3-366ed50a4d64
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411615539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.3411615539
Directory	/workspace/34.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/34.sram_ctrl_alert_test.3100712725
Short name	T699
Test name
Test status
Simulation time	35251198 ps
CPU time	0.61 seconds
Started	Apr 18 02:39:50 PM PDT 24
Finished	Apr 18 02:39:51 PM PDT 24
Peak memory	202772 kb
Host	smart-ceeb529a-cb96-47de-9df2-d7881dcefc16
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100712725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3100712725
Directory	/workspace/34.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.sram_ctrl_bijection.234383971
Short name	T629
Test name
Test status
Simulation time	62255060589 ps
CPU time	2074.63 seconds
Started	Apr 18 02:39:31 PM PDT 24
Finished	Apr 18 03:14:06 PM PDT 24
Peak memory	203208 kb
Host	smart-3d1753a5-e4d9-4c39-9cd9-0096095ef1fa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234383971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection. 234383971
Directory	/workspace/34.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/34.sram_ctrl_executable.799100131
Short name	T762
Test name
Test status
Simulation time	8439900125 ps
CPU time	1204.26 seconds
Started	Apr 18 02:39:42 PM PDT 24
Finished	Apr 18 02:59:47 PM PDT 24
Peak memory	379064 kb
Host	smart-c0fe81f1-2e1f-465d-96b3-1f2dcb91ad24
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799100131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executabl e.799100131
Directory	/workspace/34.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/34.sram_ctrl_lc_escalation.1418406912
Short name	T797
Test name
Test status
Simulation time	3541183522 ps
CPU time	6.62 seconds
Started	Apr 18 02:39:41 PM PDT 24
Finished	Apr 18 02:39:48 PM PDT 24
Peak memory	211288 kb
Host	smart-bbce4581-dfa4-4533-9a41-09855cfa304e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418406912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.1418406912
Directory	/workspace/34.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/34.sram_ctrl_max_throughput.3964508045
Short name	T369
Test name
Test status
Simulation time	791589587 ps
CPU time	54.13 seconds
Started	Apr 18 02:39:38 PM PDT 24
Finished	Apr 18 02:40:32 PM PDT 24
Peak memory	331108 kb
Host	smart-0e0eb49a-a92c-4b36-8593-134f72c22731
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964508045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.3964508045
Directory	/workspace/34.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2180188474
Short name	T578
Test name
Test status
Simulation time	8160735119 ps
CPU time	122.06 seconds
Started	Apr 18 02:39:46 PM PDT 24
Finished	Apr 18 02:41:48 PM PDT 24
Peak memory	211360 kb
Host	smart-fbc8baf7-86d9-4508-a634-87055edf5f35
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180188474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.2180188474
Directory	/workspace/34.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_walk.2112975935
Short name	T748
Test name
Test status
Simulation time	41291190987 ps
CPU time	156.38 seconds
Started	Apr 18 02:39:47 PM PDT 24
Finished	Apr 18 02:42:24 PM PDT 24
Peak memory	203716 kb
Host	smart-58a7e44e-043a-4133-b733-bdb3b92afd7a
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112975935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.2112975935
Directory	/workspace/34.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/34.sram_ctrl_multiple_keys.43504637
Short name	T223
Test name
Test status
Simulation time	32109355156 ps
CPU time	1216.42 seconds
Started	Apr 18 02:39:30 PM PDT 24
Finished	Apr 18 02:59:47 PM PDT 24
Peak memory	375964 kb
Host	smart-05138061-4639-42af-ae6e-42a78fc8e365
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43504637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multipl e_keys.43504637
Directory	/workspace/34.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access.1181911795
Short name	T213
Test name
Test status
Simulation time	901907891 ps
CPU time	43.29 seconds
Started	Apr 18 02:39:40 PM PDT 24
Finished	Apr 18 02:40:24 PM PDT 24
Peak memory	289032 kb
Host	smart-00052faf-cad3-4483-99d3-566933ec2302
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181911795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.1181911795
Directory	/workspace/34.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.866632975
Short name	T316
Test name
Test status
Simulation time	45720082943 ps
CPU time	275.69 seconds
Started	Apr 18 02:39:39 PM PDT 24
Finished	Apr 18 02:44:15 PM PDT 24
Peak memory	203196 kb
Host	smart-a071cd9b-425d-47ba-baf9-2164228dbae4
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866632975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.sram_ctrl_partial_access_b2b.866632975
Directory	/workspace/34.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/34.sram_ctrl_ram_cfg.2475417977
Short name	T886
Test name
Test status
Simulation time	1341840628 ps
CPU time	3.26 seconds
Started	Apr 18 02:39:45 PM PDT 24
Finished	Apr 18 02:39:48 PM PDT 24
Peak memory	203048 kb
Host	smart-1e4307ae-0278-4ab2-a75a-33f37c8eb334
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475417977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2475417977
Directory	/workspace/34.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/34.sram_ctrl_regwen.3247571760
Short name	T859
Test name
Test status
Simulation time	17683199659 ps
CPU time	434.14 seconds
Started	Apr 18 02:39:47 PM PDT 24
Finished	Apr 18 02:47:02 PM PDT 24
Peak memory	372812 kb
Host	smart-c7f22679-24b0-433c-9bc7-15fcb4c111b6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247571760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3247571760
Directory	/workspace/34.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/34.sram_ctrl_smoke.4164075449
Short name	T275
Test name
Test status
Simulation time	1849012376 ps
CPU time	27.98 seconds
Started	Apr 18 02:39:30 PM PDT 24
Finished	Apr 18 02:39:58 PM PDT 24
Peak memory	283712 kb
Host	smart-d2ab5765-d551-4c0c-b2c4-016fb97b6f6a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164075449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.4164075449
Directory	/workspace/34.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_all.1089158370
Short name	T360
Test name
Test status
Simulation time	982487931054 ps
CPU time	2286.75 seconds
Started	Apr 18 02:39:46 PM PDT 24
Finished	Apr 18 03:17:54 PM PDT 24
Peak memory	376092 kb
Host	smart-14a0a7e6-cd36-43c5-a78c-04528238daa2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089158370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.1089158370
Directory	/workspace/34.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3990562801
Short name	T10
Test name
Test status
Simulation time	1843371387 ps
CPU time	169.38 seconds
Started	Apr 18 02:39:46 PM PDT 24
Finished	Apr 18 02:42:35 PM PDT 24
Peak memory	371768 kb
Host	smart-086cbb94-42ed-49bd-82ec-f4826caee410
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3990562801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3990562801
Directory	/workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1726364544
Short name	T178
Test name
Test status
Simulation time	26409957649 ps
CPU time	498.43 seconds
Started	Apr 18 02:39:40 PM PDT 24
Finished	Apr 18 02:47:59 PM PDT 24
Peak memory	203124 kb
Host	smart-e7a32300-e65c-4eb0-9a20-90f372d059f3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726364544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.1726364544
Directory	/workspace/34.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2041895769
Short name	T515
Test name
Test status
Simulation time	775908691 ps
CPU time	66.88 seconds
Started	Apr 18 02:39:40 PM PDT 24
Finished	Apr 18 02:40:47 PM PDT 24
Peak memory	321472 kb
Host	smart-9e5736e8-f4dd-45a2-9504-fd5f3a772696
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041895769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2041895769
Directory	/workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1465859731
Short name	T402
Test name
Test status
Simulation time	28092757630 ps
CPU time	480.55 seconds
Started	Apr 18 02:39:58 PM PDT 24
Finished	Apr 18 02:47:59 PM PDT 24
Peak memory	352352 kb
Host	smart-66d798c6-1f98-4c82-af9f-8601558514f6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465859731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.1465859731
Directory	/workspace/35.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/35.sram_ctrl_alert_test.1114834777
Short name	T24
Test name
Test status
Simulation time	22382271 ps
CPU time	0.61 seconds
Started	Apr 18 02:40:10 PM PDT 24
Finished	Apr 18 02:40:11 PM PDT 24
Peak memory	202756 kb
Host	smart-fe5602aa-22a8-49be-87bf-27bd48d49d99
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114834777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1114834777
Directory	/workspace/35.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.sram_ctrl_bijection.2584951293
Short name	T606
Test name
Test status
Simulation time	75431881127 ps
CPU time	1240.73 seconds
Started	Apr 18 02:39:50 PM PDT 24
Finished	Apr 18 03:00:31 PM PDT 24
Peak memory	203108 kb
Host	smart-9fdbab3a-1bb3-4113-adc1-723df09c6e34
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584951293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .2584951293
Directory	/workspace/35.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/35.sram_ctrl_executable.3651101
Short name	T927
Test name
Test status
Simulation time	9839458035 ps
CPU time	1075.04 seconds
Started	Apr 18 02:40:00 PM PDT 24
Finished	Apr 18 02:57:56 PM PDT 24
Peak memory	375956 kb
Host	smart-3ac0d617-048b-4f99-8899-dd535159c6be
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.3651101
Directory	/workspace/35.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/35.sram_ctrl_lc_escalation.4057748621
Short name	T154
Test name
Test status
Simulation time	10592429629 ps
CPU time	69.88 seconds
Started	Apr 18 02:40:01 PM PDT 24
Finished	Apr 18 02:41:12 PM PDT 24
Peak memory	211320 kb
Host	smart-a8ed9512-f4d2-4e96-8e18-8b1cc861dddd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057748621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.4057748621
Directory	/workspace/35.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/35.sram_ctrl_max_throughput.3191661021
Short name	T325
Test name
Test status
Simulation time	1461703070 ps
CPU time	17.96 seconds
Started	Apr 18 02:40:00 PM PDT 24
Finished	Apr 18 02:40:18 PM PDT 24
Peak memory	256416 kb
Host	smart-817c058f-2274-4c8d-83c8-34d7d953ee15
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191661021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.3191661021
Directory	/workspace/35.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.285882779
Short name	T892
Test name
Test status
Simulation time	1604872100 ps
CPU time	117.81 seconds
Started	Apr 18 02:40:05 PM PDT 24
Finished	Apr 18 02:42:04 PM PDT 24
Peak memory	211220 kb
Host	smart-574a42ce-2a4a-4cba-bc3c-f822c6a0d24b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285882779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .sram_ctrl_mem_partial_access.285882779
Directory	/workspace/35.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_walk.3358958540
Short name	T527
Test name
Test status
Simulation time	2018929381 ps
CPU time	116.34 seconds
Started	Apr 18 02:40:07 PM PDT 24
Finished	Apr 18 02:42:04 PM PDT 24
Peak memory	203168 kb
Host	smart-6390f63b-5402-4b91-ac79-a2417c2e7af6
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358958540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.3358958540
Directory	/workspace/35.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/35.sram_ctrl_multiple_keys.4252676146
Short name	T532
Test name
Test status
Simulation time	23340190741 ps
CPU time	393.85 seconds
Started	Apr 18 02:39:52 PM PDT 24
Finished	Apr 18 02:46:26 PM PDT 24
Peak memory	354440 kb
Host	smart-f68e0f0d-97dc-49f4-94e4-7bf24f9c8bcf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252676146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.4252676146
Directory	/workspace/35.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access.2976806200
Short name	T145
Test name
Test status
Simulation time	17284802966 ps
CPU time	23.53 seconds
Started	Apr 18 02:39:54 PM PDT 24
Finished	Apr 18 02:40:18 PM PDT 24
Peak memory	203120 kb
Host	smart-2d60bad2-371f-4ec7-97a1-6f6137bfe87e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976806200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.2976806200
Directory	/workspace/35.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1793012013
Short name	T95
Test name
Test status
Simulation time	29391610432 ps
CPU time	385.82 seconds
Started	Apr 18 02:39:55 PM PDT 24
Finished	Apr 18 02:46:21 PM PDT 24
Peak memory	203152 kb
Host	smart-1ba32586-fe34-4094-a810-a50bcd0e3259
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793012013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.1793012013
Directory	/workspace/35.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/35.sram_ctrl_ram_cfg.567271625
Short name	T294
Test name
Test status
Simulation time	355014863 ps
CPU time	3.5 seconds
Started	Apr 18 02:40:01 PM PDT 24
Finished	Apr 18 02:40:05 PM PDT 24
Peak memory	203068 kb
Host	smart-0e51c0ca-35b8-4d3e-a805-c8282702c47c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567271625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.567271625
Directory	/workspace/35.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/35.sram_ctrl_regwen.915816555
Short name	T509
Test name
Test status
Simulation time	133627472511 ps
CPU time	993.85 seconds
Started	Apr 18 02:40:00 PM PDT 24
Finished	Apr 18 02:56:34 PM PDT 24
Peak memory	375984 kb
Host	smart-d7ebc1bb-586b-42c1-87a0-d6fa7357cbe2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915816555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.915816555
Directory	/workspace/35.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/35.sram_ctrl_smoke.1984030110
Short name	T579
Test name
Test status
Simulation time	1830818666 ps
CPU time	10.47 seconds
Started	Apr 18 02:39:52 PM PDT 24
Finished	Apr 18 02:40:03 PM PDT 24
Peak memory	202976 kb
Host	smart-9ecfb35d-29ab-484f-b993-8bf8a90484e9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984030110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.1984030110
Directory	/workspace/35.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all.2057892650
Short name	T728
Test name
Test status
Simulation time	490909310247 ps
CPU time	2106.76 seconds
Started	Apr 18 02:40:09 PM PDT 24
Finished	Apr 18 03:15:16 PM PDT 24
Peak memory	316240 kb
Host	smart-92794212-8232-4242-bb63-6a34073e2b39
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057892650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.2057892650
Directory	/workspace/35.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3790778533
Short name	T526
Test name
Test status
Simulation time	5219355291 ps
CPU time	113.76 seconds
Started	Apr 18 02:40:06 PM PDT 24
Finished	Apr 18 02:42:00 PM PDT 24
Peak memory	334092 kb
Host	smart-f7be1a5c-a4e8-47d7-9a03-f162b64f2413
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3790778533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3790778533
Directory	/workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.2185499998
Short name	T836
Test name
Test status
Simulation time	4520056435 ps
CPU time	310.14 seconds
Started	Apr 18 02:39:55 PM PDT 24
Finished	Apr 18 02:45:05 PM PDT 24
Peak memory	203156 kb
Host	smart-8f7615eb-1ba3-4a7e-9b6f-042a76090c8f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185499998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.2185499998
Directory	/workspace/35.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2683509742
Short name	T252
Test name
Test status
Simulation time	798644513 ps
CPU time	101.35 seconds
Started	Apr 18 02:40:02 PM PDT 24
Finished	Apr 18 02:41:43 PM PDT 24
Peak memory	366840 kb
Host	smart-ea0292a4-20dd-4ab5-87c5-e3e690a36ab7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683509742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.2683509742
Directory	/workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2716472057
Short name	T701
Test name
Test status
Simulation time	101199540357 ps
CPU time	1397.51 seconds
Started	Apr 18 02:40:20 PM PDT 24
Finished	Apr 18 03:03:38 PM PDT 24
Peak memory	374860 kb
Host	smart-7b2cc2ed-88dd-4982-8a93-81ede8489bde
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716472057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.2716472057
Directory	/workspace/36.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/36.sram_ctrl_alert_test.3634521036
Short name	T510
Test name
Test status
Simulation time	42138868 ps
CPU time	0.62 seconds
Started	Apr 18 02:40:37 PM PDT 24
Finished	Apr 18 02:40:38 PM PDT 24
Peak memory	202756 kb
Host	smart-a42f14b2-c86e-4c8b-a847-4e383c263db7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634521036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.3634521036
Directory	/workspace/36.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.sram_ctrl_bijection.3455471360
Short name	T310
Test name
Test status
Simulation time	324599375676 ps
CPU time	731.86 seconds
Started	Apr 18 02:40:09 PM PDT 24
Finished	Apr 18 02:52:21 PM PDT 24
Peak memory	203184 kb
Host	smart-a7c9b8ba-214e-4ddb-99a0-5454c4faa137
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455471360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .3455471360
Directory	/workspace/36.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/36.sram_ctrl_executable.4002333541
Short name	T331
Test name
Test status
Simulation time	7625444411 ps
CPU time	942.09 seconds
Started	Apr 18 02:40:25 PM PDT 24
Finished	Apr 18 02:56:08 PM PDT 24
Peak memory	369792 kb
Host	smart-9df59f20-3084-4004-9856-e88fb572dcac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002333541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.4002333541
Directory	/workspace/36.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/36.sram_ctrl_lc_escalation.227889361
Short name	T314
Test name
Test status
Simulation time	5604623104 ps
CPU time	35.67 seconds
Started	Apr 18 02:40:21 PM PDT 24
Finished	Apr 18 02:40:57 PM PDT 24
Peak memory	203212 kb
Host	smart-5c7f13be-aa6f-4115-9188-6162854bcfeb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227889361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_esc alation.227889361
Directory	/workspace/36.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/36.sram_ctrl_max_throughput.3637236313
Short name	T552
Test name
Test status
Simulation time	2650595569 ps
CPU time	10.41 seconds
Started	Apr 18 02:40:21 PM PDT 24
Finished	Apr 18 02:40:32 PM PDT 24
Peak memory	235408 kb
Host	smart-18387dd0-1f5d-474c-a908-55dfcf11c0a5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637236313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.3637236313
Directory	/workspace/36.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3845471884
Short name	T80
Test name
Test status
Simulation time	14503364886 ps
CPU time	78.7 seconds
Started	Apr 18 02:40:34 PM PDT 24
Finished	Apr 18 02:41:53 PM PDT 24
Peak memory	211376 kb
Host	smart-2bf35948-4562-4ffe-b3c0-8428e2c32cbc
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845471884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.3845471884
Directory	/workspace/36.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_walk.3869980374
Short name	T747
Test name
Test status
Simulation time	27530483395 ps
CPU time	146.24 seconds
Started	Apr 18 02:40:30 PM PDT 24
Finished	Apr 18 02:42:57 PM PDT 24
Peak memory	203516 kb
Host	smart-5581a84c-a6d4-4c60-914e-c78a64aa61d7
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869980374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.3869980374
Directory	/workspace/36.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/36.sram_ctrl_multiple_keys.3645268321
Short name	T353
Test name
Test status
Simulation time	19706636837 ps
CPU time	785.02 seconds
Started	Apr 18 02:40:11 PM PDT 24
Finished	Apr 18 02:53:16 PM PDT 24
Peak memory	370344 kb
Host	smart-0684de25-0171-403a-b546-c21d256bb32d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645268321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.3645268321
Directory	/workspace/36.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access.146605984
Short name	T217
Test name
Test status
Simulation time	2369356722 ps
CPU time	19.67 seconds
Started	Apr 18 02:40:14 PM PDT 24
Finished	Apr 18 02:40:34 PM PDT 24
Peak memory	259024 kb
Host	smart-51a80990-123a-49cd-88c6-506c24bd9d5e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146605984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s ram_ctrl_partial_access.146605984
Directory	/workspace/36.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1577718379
Short name	T470
Test name
Test status
Simulation time	13870686625 ps
CPU time	356.08 seconds
Started	Apr 18 02:40:14 PM PDT 24
Finished	Apr 18 02:46:10 PM PDT 24
Peak memory	203180 kb
Host	smart-afc59b38-b8ef-437f-909c-33f743db0007
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577718379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.1577718379
Directory	/workspace/36.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/36.sram_ctrl_ram_cfg.606582645
Short name	T653
Test name
Test status
Simulation time	381139157 ps
CPU time	3.08 seconds
Started	Apr 18 02:40:27 PM PDT 24
Finished	Apr 18 02:40:30 PM PDT 24
Peak memory	203108 kb
Host	smart-bd097671-f5ed-4e2c-9e7e-cff151d5d7cf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606582645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.606582645
Directory	/workspace/36.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/36.sram_ctrl_regwen.1808867830
Short name	T928
Test name
Test status
Simulation time	4712677210 ps
CPU time	697.15 seconds
Started	Apr 18 02:40:27 PM PDT 24
Finished	Apr 18 02:52:05 PM PDT 24
Peak memory	374884 kb
Host	smart-0c46eea5-c5e4-4b71-93c1-2bccf5e8f920
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808867830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1808867830
Directory	/workspace/36.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/36.sram_ctrl_smoke.1870615033
Short name	T187
Test name
Test status
Simulation time	864182617 ps
CPU time	5.65 seconds
Started	Apr 18 02:40:09 PM PDT 24
Finished	Apr 18 02:40:15 PM PDT 24
Peak memory	212180 kb
Host	smart-74ec5967-b34c-4c5c-899d-ab2ba6e1eb3e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870615033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1870615033
Directory	/workspace/36.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all.1537348403
Short name	T315
Test name
Test status
Simulation time	413284884392 ps
CPU time	3490.47 seconds
Started	Apr 18 02:40:36 PM PDT 24
Finished	Apr 18 03:38:48 PM PDT 24
Peak memory	380116 kb
Host	smart-5eb5a14b-01a3-4208-866c-d6cebe396a37
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537348403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.1537348403
Directory	/workspace/36.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3755524863
Short name	T105
Test name
Test status
Simulation time	3503396496 ps
CPU time	46.7 seconds
Started	Apr 18 02:40:31 PM PDT 24
Finished	Apr 18 02:41:18 PM PDT 24
Peak memory	218692 kb
Host	smart-038d301d-e2ef-4670-8c27-d54592837984
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3755524863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3755524863
Directory	/workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3455778957
Short name	T861
Test name
Test status
Simulation time	10185496183 ps
CPU time	356.45 seconds
Started	Apr 18 02:40:09 PM PDT 24
Finished	Apr 18 02:46:05 PM PDT 24
Peak memory	203172 kb
Host	smart-664d8acf-e447-4845-bb5a-d80df2a73c85
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455778957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.3455778957
Directory	/workspace/36.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2444594955
Short name	T658
Test name
Test status
Simulation time	810818587 ps
CPU time	107.64 seconds
Started	Apr 18 02:40:21 PM PDT 24
Finished	Apr 18 02:42:09 PM PDT 24
Peak memory	370588 kb
Host	smart-5da38ed1-f7b0-4dcf-83fd-7f966f119b35
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444594955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2444594955
Directory	/workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2842397735
Short name	T340
Test name
Test status
Simulation time	38829906817 ps
CPU time	397.92 seconds
Started	Apr 18 02:40:46 PM PDT 24
Finished	Apr 18 02:47:25 PM PDT 24
Peak memory	376916 kb
Host	smart-f73985fb-f833-457b-b750-633068254224
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842397735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.2842397735
Directory	/workspace/37.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/37.sram_ctrl_alert_test.941571811
Short name	T565
Test name
Test status
Simulation time	34832698 ps
CPU time	0.62 seconds
Started	Apr 18 02:40:56 PM PDT 24
Finished	Apr 18 02:40:57 PM PDT 24
Peak memory	202628 kb
Host	smart-bc0314c8-7668-4eb1-977b-e7ec2644d26a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941571811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.941571811
Directory	/workspace/37.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.sram_ctrl_bijection.9551935
Short name	T311
Test name
Test status
Simulation time	70449611858 ps
CPU time	2352.53 seconds
Started	Apr 18 02:40:41 PM PDT 24
Finished	Apr 18 03:19:55 PM PDT 24
Peak memory	203252 kb
Host	smart-35236a21-6832-4c46-ab83-ceff406bd311
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9551935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijecti on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.9551935
Directory	/workspace/37.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/37.sram_ctrl_executable.3105441700
Short name	T233
Test name
Test status
Simulation time	43082576250 ps
CPU time	546.25 seconds
Started	Apr 18 02:40:46 PM PDT 24
Finished	Apr 18 02:49:53 PM PDT 24
Peak memory	377408 kb
Host	smart-f4feedbf-7b0f-4ff4-9a2a-062e0657875a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105441700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.3105441700
Directory	/workspace/37.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/37.sram_ctrl_lc_escalation.1176615500
Short name	T710
Test name
Test status
Simulation time	79148779233 ps
CPU time	75.97 seconds
Started	Apr 18 02:40:46 PM PDT 24
Finished	Apr 18 02:42:03 PM PDT 24
Peak memory	211260 kb
Host	smart-a9f827b7-bef1-4243-a675-27f2ee0a8e15
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176615500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.1176615500
Directory	/workspace/37.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/37.sram_ctrl_max_throughput.2910581136
Short name	T186
Test name
Test status
Simulation time	3647912511 ps
CPU time	129.23 seconds
Started	Apr 18 02:40:46 PM PDT 24
Finished	Apr 18 02:42:56 PM PDT 24
Peak memory	370776 kb
Host	smart-50ad5d16-213e-4107-90b3-353e9cca7775
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910581136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.2910581136
Directory	/workspace/37.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3934763484
Short name	T632
Test name
Test status
Simulation time	21474286664 ps
CPU time	75.95 seconds
Started	Apr 18 02:40:50 PM PDT 24
Finished	Apr 18 02:42:07 PM PDT 24
Peak memory	211332 kb
Host	smart-0bb70f0f-7c94-41ac-a394-b82a1502892f
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934763484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.3934763484
Directory	/workspace/37.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_walk.2013913850
Short name	T150
Test name
Test status
Simulation time	8228390640 ps
CPU time	124.77 seconds
Started	Apr 18 02:40:52 PM PDT 24
Finished	Apr 18 02:42:57 PM PDT 24
Peak memory	203512 kb
Host	smart-fb99a5bb-57d0-48ba-b880-ca5ca5182591
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013913850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.2013913850
Directory	/workspace/37.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/37.sram_ctrl_multiple_keys.328916517
Short name	T668
Test name
Test status
Simulation time	5894020711 ps
CPU time	991.44 seconds
Started	Apr 18 02:40:37 PM PDT 24
Finished	Apr 18 02:57:09 PM PDT 24
Peak memory	380788 kb
Host	smart-f09186f3-3e9c-4bdd-bf99-6d5c8f1ede07
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328916517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multip le_keys.328916517
Directory	/workspace/37.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access.943579495
Short name	T831
Test name
Test status
Simulation time	490400118 ps
CPU time	45.32 seconds
Started	Apr 18 02:40:44 PM PDT 24
Finished	Apr 18 02:41:30 PM PDT 24
Peak memory	314452 kb
Host	smart-0207a791-8e66-49dc-8b2d-4634a465f68a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943579495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.s ram_ctrl_partial_access.943579495
Directory	/workspace/37.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.362268051
Short name	T738
Test name
Test status
Simulation time	53840739881 ps
CPU time	264.66 seconds
Started	Apr 18 02:40:40 PM PDT 24
Finished	Apr 18 02:45:06 PM PDT 24
Peak memory	203160 kb
Host	smart-8745aa4c-0a66-4407-ab3e-0d4c764626f9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362268051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.sram_ctrl_partial_access_b2b.362268051
Directory	/workspace/37.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/37.sram_ctrl_ram_cfg.263650228
Short name	T835
Test name
Test status
Simulation time	1462446006 ps
CPU time	3.68 seconds
Started	Apr 18 02:40:52 PM PDT 24
Finished	Apr 18 02:40:56 PM PDT 24
Peak memory	203064 kb
Host	smart-781d4488-71bc-446d-a92a-1405a1bc0861
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263650228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.263650228
Directory	/workspace/37.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/37.sram_ctrl_regwen.3328052341
Short name	T367
Test name
Test status
Simulation time	69090541541 ps
CPU time	1099.55 seconds
Started	Apr 18 02:40:52 PM PDT 24
Finished	Apr 18 02:59:11 PM PDT 24
Peak memory	374896 kb
Host	smart-13ed5ac2-e58d-474e-bed7-eae493aec312
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328052341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3328052341
Directory	/workspace/37.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/37.sram_ctrl_smoke.2971725314
Short name	T556
Test name
Test status
Simulation time	1121878705 ps
CPU time	15.38 seconds
Started	Apr 18 02:40:37 PM PDT 24
Finished	Apr 18 02:40:53 PM PDT 24
Peak memory	203172 kb
Host	smart-6ab48c7f-f9af-4868-b025-e13a33fc5c50
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971725314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2971725314
Directory	/workspace/37.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all.1049991396
Short name	T345
Test name
Test status
Simulation time	724549298522 ps
CPU time	5860.42 seconds
Started	Apr 18 02:40:51 PM PDT 24
Finished	Apr 18 04:18:32 PM PDT 24
Peak memory	390280 kb
Host	smart-77814ea6-2c55-46bd-ab59-24c234d1abbf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049991396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.1049991396
Directory	/workspace/37.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3056845914
Short name	T746
Test name
Test status
Simulation time	4558758584 ps
CPU time	153.43 seconds
Started	Apr 18 02:40:51 PM PDT 24
Finished	Apr 18 02:43:24 PM PDT 24
Peak memory	370836 kb
Host	smart-c7a4949e-e631-491b-97b1-821dc7ff4a15
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3056845914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3056845914
Directory	/workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1937787397
Short name	T878
Test name
Test status
Simulation time	2934290090 ps
CPU time	167.02 seconds
Started	Apr 18 02:40:42 PM PDT 24
Finished	Apr 18 02:43:30 PM PDT 24
Peak memory	203144 kb
Host	smart-039a5f0b-9713-4b20-a29a-945d92d32a64
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937787397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.1937787397
Directory	/workspace/37.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3704658574
Short name	T288
Test name
Test status
Simulation time	2799952970 ps
CPU time	14.25 seconds
Started	Apr 18 02:40:46 PM PDT 24
Finished	Apr 18 02:41:00 PM PDT 24
Peak memory	251972 kb
Host	smart-27b8c430-56f9-4870-a633-610506a845e1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704658574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.3704658574
Directory	/workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1073459429
Short name	T604
Test name
Test status
Simulation time	20962052709 ps
CPU time	465.17 seconds
Started	Apr 18 02:41:07 PM PDT 24
Finished	Apr 18 02:48:52 PM PDT 24
Peak memory	374892 kb
Host	smart-2dd85f54-c8a2-4240-8a01-805d64cb470c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073459429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.1073459429
Directory	/workspace/38.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/38.sram_ctrl_alert_test.949632770
Short name	T626
Test name
Test status
Simulation time	38791000 ps
CPU time	0.62 seconds
Started	Apr 18 02:41:24 PM PDT 24
Finished	Apr 18 02:41:25 PM PDT 24
Peak memory	202788 kb
Host	smart-fe75cdce-5bcc-44ed-983a-ea8d25e3c10b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949632770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.949632770
Directory	/workspace/38.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.sram_ctrl_bijection.1778122320
Short name	T736
Test name
Test status
Simulation time	107849623186 ps
CPU time	2047.91 seconds
Started	Apr 18 02:40:57 PM PDT 24
Finished	Apr 18 03:15:05 PM PDT 24
Peak memory	203432 kb
Host	smart-c53b7ace-e34b-4a3f-b955-c800b89517e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778122320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .1778122320
Directory	/workspace/38.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/38.sram_ctrl_executable.1882392371
Short name	T435
Test name
Test status
Simulation time	3235831830 ps
CPU time	10.6 seconds
Started	Apr 18 02:41:14 PM PDT 24
Finished	Apr 18 02:41:25 PM PDT 24
Peak memory	203024 kb
Host	smart-05ce9118-ca3b-46c8-878a-fc4effb88c71
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882392371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.1882392371
Directory	/workspace/38.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/38.sram_ctrl_lc_escalation.2627133688
Short name	T909
Test name
Test status
Simulation time	89951105614 ps
CPU time	80.57 seconds
Started	Apr 18 02:41:07 PM PDT 24
Finished	Apr 18 02:42:28 PM PDT 24
Peak memory	203100 kb
Host	smart-bbc4cfa8-d481-4e86-94a6-4df5b414de58
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627133688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.2627133688
Directory	/workspace/38.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/38.sram_ctrl_max_throughput.887424082
Short name	T776
Test name
Test status
Simulation time	2485005026 ps
CPU time	30.54 seconds
Started	Apr 18 02:41:06 PM PDT 24
Finished	Apr 18 02:41:37 PM PDT 24
Peak memory	289972 kb
Host	smart-c3ee82d9-7903-40d7-9b34-cfee6a2b128e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887424082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.sram_ctrl_max_throughput.887424082
Directory	/workspace/38.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1840168939
Short name	T667
Test name
Test status
Simulation time	7439765806 ps
CPU time	123.04 seconds
Started	Apr 18 02:41:18 PM PDT 24
Finished	Apr 18 02:43:21 PM PDT 24
Peak memory	211344 kb
Host	smart-fc9a6d47-3f64-4ae1-8757-ec6b371876a4
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840168939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.1840168939
Directory	/workspace/38.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_walk.1734954510
Short name	T837
Test name
Test status
Simulation time	43063505469 ps
CPU time	157.46 seconds
Started	Apr 18 02:41:12 PM PDT 24
Finished	Apr 18 02:43:50 PM PDT 24
Peak memory	203188 kb
Host	smart-46e53d06-8377-4575-ac90-fb8e3f2d13a8
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734954510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.1734954510
Directory	/workspace/38.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/38.sram_ctrl_multiple_keys.1290930542
Short name	T309
Test name
Test status
Simulation time	17797466527 ps
CPU time	992.09 seconds
Started	Apr 18 02:40:57 PM PDT 24
Finished	Apr 18 02:57:30 PM PDT 24
Peak memory	377964 kb
Host	smart-db16e46f-3ba7-453c-9fed-ca972f0807cd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290930542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.1290930542
Directory	/workspace/38.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access.127759549
Short name	T561
Test name
Test status
Simulation time	3461762210 ps
CPU time	18.85 seconds
Started	Apr 18 02:41:07 PM PDT 24
Finished	Apr 18 02:41:26 PM PDT 24
Peak memory	250132 kb
Host	smart-e4a1e941-87f0-4209-975b-04f8181bff35
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127759549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s ram_ctrl_partial_access.127759549
Directory	/workspace/38.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3631137634
Short name	T212
Test name
Test status
Simulation time	23105019090 ps
CPU time	308.02 seconds
Started	Apr 18 02:41:07 PM PDT 24
Finished	Apr 18 02:46:15 PM PDT 24
Peak memory	203200 kb
Host	smart-5ef5a461-d7d4-4135-9fdf-17af4bd98033
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631137634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.3631137634
Directory	/workspace/38.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/38.sram_ctrl_ram_cfg.2467893068
Short name	T559
Test name
Test status
Simulation time	358920462 ps
CPU time	3.32 seconds
Started	Apr 18 02:41:13 PM PDT 24
Finished	Apr 18 02:41:16 PM PDT 24
Peak memory	203072 kb
Host	smart-6b7a7a75-1db4-43b0-b215-d89fd893d8ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467893068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2467893068
Directory	/workspace/38.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/38.sram_ctrl_regwen.409529801
Short name	T680
Test name
Test status
Simulation time	7442602721 ps
CPU time	338.3 seconds
Started	Apr 18 02:41:14 PM PDT 24
Finished	Apr 18 02:46:52 PM PDT 24
Peak memory	347252 kb
Host	smart-c77ed273-fd17-4c2e-b19a-d16284348e1e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409529801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.409529801
Directory	/workspace/38.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/38.sram_ctrl_smoke.325613851
Short name	T424
Test name
Test status
Simulation time	537606060 ps
CPU time	15.37 seconds
Started	Apr 18 02:40:57 PM PDT 24
Finished	Apr 18 02:41:12 PM PDT 24
Peak memory	251692 kb
Host	smart-65affe14-c963-4871-82d0-07641b09b971
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325613851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.325613851
Directory	/workspace/38.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all.1584092605
Short name	T535
Test name
Test status
Simulation time	890783012916 ps
CPU time	3930.13 seconds
Started	Apr 18 02:41:17 PM PDT 24
Finished	Apr 18 03:46:48 PM PDT 24
Peak memory	381072 kb
Host	smart-a0f10524-7206-46f9-998b-a73d667ea7ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584092605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.1584092605
Directory	/workspace/38.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2004830354
Short name	T550
Test name
Test status
Simulation time	998138786 ps
CPU time	8.7 seconds
Started	Apr 18 02:41:16 PM PDT 24
Finished	Apr 18 02:41:25 PM PDT 24
Peak memory	211304 kb
Host	smart-1850657e-28a6-48f9-8b47-02f9735c7ac0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2004830354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2004830354
Directory	/workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1011808420
Short name	T823
Test name
Test status
Simulation time	3944835021 ps
CPU time	196.32 seconds
Started	Apr 18 02:41:06 PM PDT 24
Finished	Apr 18 02:44:23 PM PDT 24
Peak memory	203132 kb
Host	smart-c6712585-9c87-4953-a22b-01348dd38137
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011808420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.1011808420
Directory	/workspace/38.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.370868589
Short name	T881
Test name
Test status
Simulation time	3112019926 ps
CPU time	48.77 seconds
Started	Apr 18 02:41:06 PM PDT 24
Finished	Apr 18 02:41:56 PM PDT 24
Peak memory	307480 kb
Host	smart-20319850-31f6-49f0-9db4-2878e1a425de
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370868589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.370868589
Directory	/workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2481209454
Short name	T687
Test name
Test status
Simulation time	10045711186 ps
CPU time	654.85 seconds
Started	Apr 18 02:41:32 PM PDT 24
Finished	Apr 18 02:52:28 PM PDT 24
Peak memory	373788 kb
Host	smart-a66e0122-3312-47a9-a1d6-2b354aacec65
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481209454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.2481209454
Directory	/workspace/39.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/39.sram_ctrl_alert_test.683193774
Short name	T681
Test name
Test status
Simulation time	29950441 ps
CPU time	0.63 seconds
Started	Apr 18 02:41:46 PM PDT 24
Finished	Apr 18 02:41:47 PM PDT 24
Peak memory	202788 kb
Host	smart-86a6d20d-fc25-42fa-96da-7912eecca919
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683193774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.683193774
Directory	/workspace/39.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.sram_ctrl_bijection.3703600398
Short name	T839
Test name
Test status
Simulation time	43406758260 ps
CPU time	907.53 seconds
Started	Apr 18 02:41:28 PM PDT 24
Finished	Apr 18 02:56:36 PM PDT 24
Peak memory	203216 kb
Host	smart-1a408f2c-a6ae-4ecb-b6db-63cf1238bfe4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703600398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .3703600398
Directory	/workspace/39.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/39.sram_ctrl_executable.2630937527
Short name	T488
Test name
Test status
Simulation time	17866813034 ps
CPU time	219.75 seconds
Started	Apr 18 02:41:42 PM PDT 24
Finished	Apr 18 02:45:22 PM PDT 24
Peak memory	367688 kb
Host	smart-96d9e905-2133-46d6-9bc3-5de3056d9a32
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630937527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.2630937527
Directory	/workspace/39.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/39.sram_ctrl_lc_escalation.3358372553
Short name	T274
Test name
Test status
Simulation time	48004473506 ps
CPU time	60.88 seconds
Started	Apr 18 02:41:35 PM PDT 24
Finished	Apr 18 02:42:36 PM PDT 24
Peak memory	203124 kb
Host	smart-612d1452-4a3e-48fd-a0f2-b8a90f869228
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358372553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.3358372553
Directory	/workspace/39.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/39.sram_ctrl_max_throughput.1728735054
Short name	T546
Test name
Test status
Simulation time	2823455741 ps
CPU time	124.99 seconds
Started	Apr 18 02:41:33 PM PDT 24
Finished	Apr 18 02:43:38 PM PDT 24
Peak memory	363564 kb
Host	smart-c4d38b82-c170-42c9-b1ad-9714fa0029eb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728735054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.1728735054
Directory	/workspace/39.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.3688462662
Short name	T541
Test name
Test status
Simulation time	32223501914 ps
CPU time	163.03 seconds
Started	Apr 18 02:41:47 PM PDT 24
Finished	Apr 18 02:44:30 PM PDT 24
Peak memory	211288 kb
Host	smart-7fb38e7c-5917-4ca4-86a1-983afb624774
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688462662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.3688462662
Directory	/workspace/39.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_walk.333651374
Short name	T165
Test name
Test status
Simulation time	21522555842 ps
CPU time	310.86 seconds
Started	Apr 18 02:41:42 PM PDT 24
Finished	Apr 18 02:46:53 PM PDT 24
Peak memory	203688 kb
Host	smart-d55597f0-ab03-45f0-91f5-7b8edd2775da
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333651374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _mem_walk.333651374
Directory	/workspace/39.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/39.sram_ctrl_multiple_keys.1543982467
Short name	T259
Test name
Test status
Simulation time	21591674884 ps
CPU time	1326.86 seconds
Started	Apr 18 02:41:27 PM PDT 24
Finished	Apr 18 03:03:35 PM PDT 24
Peak memory	378904 kb
Host	smart-1bbab2e3-f2f2-4d4a-89f4-522b7753a578
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543982467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.1543982467
Directory	/workspace/39.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access.2230042804
Short name	T711
Test name
Test status
Simulation time	3069571260 ps
CPU time	48.15 seconds
Started	Apr 18 02:41:28 PM PDT 24
Finished	Apr 18 02:42:16 PM PDT 24
Peak memory	298124 kb
Host	smart-2b36788e-f0e5-4c10-808e-8137899476c6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230042804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.2230042804
Directory	/workspace/39.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.909318131
Short name	T468
Test name
Test status
Simulation time	4508946868 ps
CPU time	221.78 seconds
Started	Apr 18 02:41:36 PM PDT 24
Finished	Apr 18 02:45:18 PM PDT 24
Peak memory	203168 kb
Host	smart-dc9ae323-fcd0-4dc6-90f6-faea0cb6be88
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909318131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.sram_ctrl_partial_access_b2b.909318131
Directory	/workspace/39.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/39.sram_ctrl_ram_cfg.1895103323
Short name	T813
Test name
Test status
Simulation time	345439948 ps
CPU time	3.52 seconds
Started	Apr 18 02:41:42 PM PDT 24
Finished	Apr 18 02:41:46 PM PDT 24
Peak memory	203040 kb
Host	smart-6313e17a-9340-45bc-b29d-982ad4d6ad29
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895103323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1895103323
Directory	/workspace/39.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/39.sram_ctrl_regwen.1392949402
Short name	T244
Test name
Test status
Simulation time	5897678767 ps
CPU time	1064.31 seconds
Started	Apr 18 02:41:43 PM PDT 24
Finished	Apr 18 02:59:28 PM PDT 24
Peak memory	377964 kb
Host	smart-2595dfe2-b8c2-40d0-a0c0-160e273a1dfa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392949402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1392949402
Directory	/workspace/39.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/39.sram_ctrl_smoke.2322743712
Short name	T234
Test name
Test status
Simulation time	4628834290 ps
CPU time	60.98 seconds
Started	Apr 18 02:41:27 PM PDT 24
Finished	Apr 18 02:42:29 PM PDT 24
Peak memory	333040 kb
Host	smart-86a44c19-9054-4a55-8ba6-b09d4f8c6208
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322743712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2322743712
Directory	/workspace/39.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all.90870258
Short name	T622
Test name
Test status
Simulation time	31391493658 ps
CPU time	2326.66 seconds
Started	Apr 18 02:41:49 PM PDT 24
Finished	Apr 18 03:20:36 PM PDT 24
Peak memory	385172 kb
Host	smart-7576f1b6-fa0c-4f77-b2ca-d5c800ba565d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90870258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.sram_ctrl_stress_all.90870258
Directory	/workspace/39.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.4104636516
Short name	T819
Test name
Test status
Simulation time	747379799 ps
CPU time	11.83 seconds
Started	Apr 18 02:41:48 PM PDT 24
Finished	Apr 18 02:42:00 PM PDT 24
Peak memory	211332 kb
Host	smart-e3632a53-40cf-4e6e-871d-b11939c10c67
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4104636516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.4104636516
Directory	/workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1661915531
Short name	T226
Test name
Test status
Simulation time	5742275088 ps
CPU time	138.7 seconds
Started	Apr 18 02:41:28 PM PDT 24
Finished	Apr 18 02:43:47 PM PDT 24
Peak memory	203144 kb
Host	smart-131c4f47-3731-4dc4-838f-82f032ba8d07
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661915531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1661915531
Directory	/workspace/39.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3438533117
Short name	T615
Test name
Test status
Simulation time	3127898047 ps
CPU time	75.73 seconds
Started	Apr 18 02:41:33 PM PDT 24
Finished	Apr 18 02:42:49 PM PDT 24
Peak memory	325668 kb
Host	smart-b0ce0a6c-8e7a-4918-b59f-c3de6785ec29
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438533117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3438533117
Directory	/workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3682619174
Short name	T243
Test name
Test status
Simulation time	21652995319 ps
CPU time	545.71 seconds
Started	Apr 18 02:30:57 PM PDT 24
Finished	Apr 18 02:40:03 PM PDT 24
Peak memory	368728 kb
Host	smart-7c5e90ff-9367-4175-8ce2-384e7b086f5f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682619174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.3682619174
Directory	/workspace/4.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/4.sram_ctrl_alert_test.1939050906
Short name	T149
Test name
Test status
Simulation time	68133976 ps
CPU time	0.64 seconds
Started	Apr 18 02:30:57 PM PDT 24
Finished	Apr 18 02:30:58 PM PDT 24
Peak memory	202828 kb
Host	smart-0b05f100-5c0f-4689-b0e7-5c4610ada3f5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939050906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.1939050906
Directory	/workspace/4.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.sram_ctrl_bijection.918229629
Short name	T749
Test name
Test status
Simulation time	59982776628 ps
CPU time	1093.62 seconds
Started	Apr 18 02:30:55 PM PDT 24
Finished	Apr 18 02:49:09 PM PDT 24
Peak memory	203368 kb
Host	smart-05337166-9993-4c33-8f95-c7cc540eb705
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918229629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.918229629
Directory	/workspace/4.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/4.sram_ctrl_executable.1463327700
Short name	T374
Test name
Test status
Simulation time	12267809112 ps
CPU time	289.76 seconds
Started	Apr 18 02:30:51 PM PDT 24
Finished	Apr 18 02:35:41 PM PDT 24
Peak memory	372708 kb
Host	smart-f12b483f-26c6-4631-85b7-1f5b1eed6e47
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463327700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.1463327700
Directory	/workspace/4.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/4.sram_ctrl_lc_escalation.2777587209
Short name	T506
Test name
Test status
Simulation time	1735855529 ps
CPU time	3.75 seconds
Started	Apr 18 02:30:54 PM PDT 24
Finished	Apr 18 02:30:58 PM PDT 24
Peak memory	202792 kb
Host	smart-deb476f1-54b5-4f5e-ace8-39e73a6a2b5d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777587209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.2777587209
Directory	/workspace/4.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/4.sram_ctrl_max_throughput.1471663783
Short name	T422
Test name
Test status
Simulation time	1726317168 ps
CPU time	118.69 seconds
Started	Apr 18 02:30:56 PM PDT 24
Finished	Apr 18 02:32:55 PM PDT 24
Peak memory	370596 kb
Host	smart-f2d54696-4e32-4d74-aad0-1ac4884e22c3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471663783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.1471663783
Directory	/workspace/4.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2199185423
Short name	T74
Test name
Test status
Simulation time	6464548786 ps
CPU time	127.32 seconds
Started	Apr 18 02:30:59 PM PDT 24
Finished	Apr 18 02:33:07 PM PDT 24
Peak memory	211556 kb
Host	smart-5249757d-8ea7-4af3-b208-6e140b0882b5
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199185423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.2199185423
Directory	/workspace/4.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_walk.3744899718
Short name	T790
Test name
Test status
Simulation time	38223773872 ps
CPU time	162.11 seconds
Started	Apr 18 02:30:57 PM PDT 24
Finished	Apr 18 02:33:39 PM PDT 24
Peak memory	203748 kb
Host	smart-c48d0b3c-ff97-489e-a256-c2999d5ce6cb
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744899718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.3744899718
Directory	/workspace/4.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/4.sram_ctrl_multiple_keys.2970076865
Short name	T900
Test name
Test status
Simulation time	52444197321 ps
CPU time	674.56 seconds
Started	Apr 18 02:31:08 PM PDT 24
Finished	Apr 18 02:42:23 PM PDT 24
Peak memory	378156 kb
Host	smart-4a787a91-25eb-4e57-bdb5-1f709884bd56
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970076865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.2970076865
Directory	/workspace/4.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access.686521611
Short name	T228
Test name
Test status
Simulation time	464068598 ps
CPU time	5.23 seconds
Started	Apr 18 02:30:51 PM PDT 24
Finished	Apr 18 02:30:57 PM PDT 24
Peak memory	202976 kb
Host	smart-ccdfc973-98cf-439b-90e3-2a3da318ac7f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686521611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr am_ctrl_partial_access.686521611
Directory	/workspace/4.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.472009197
Short name	T869
Test name
Test status
Simulation time	25883313878 ps
CPU time	257.29 seconds
Started	Apr 18 02:30:54 PM PDT 24
Finished	Apr 18 02:35:12 PM PDT 24
Peak memory	203160 kb
Host	smart-7b589232-b267-4fb7-9e49-50380ac76a0d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472009197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.sram_ctrl_partial_access_b2b.472009197
Directory	/workspace/4.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/4.sram_ctrl_ram_cfg.3505521369
Short name	T334
Test name
Test status
Simulation time	1346479974 ps
CPU time	3.15 seconds
Started	Apr 18 02:30:57 PM PDT 24
Finished	Apr 18 02:31:00 PM PDT 24
Peak memory	203088 kb
Host	smart-f8a1b4a9-cdb0-44a4-91a4-73cd9fd10dc8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505521369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.3505521369
Directory	/workspace/4.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/4.sram_ctrl_regwen.254760042
Short name	T365
Test name
Test status
Simulation time	2454620419 ps
CPU time	510.75 seconds
Started	Apr 18 02:30:55 PM PDT 24
Finished	Apr 18 02:39:26 PM PDT 24
Peak memory	378224 kb
Host	smart-bf3bbd2d-15b7-4f75-a61f-7f513ebaf9b5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254760042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.254760042
Directory	/workspace/4.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/4.sram_ctrl_sec_cm.2777747081
Short name	T21
Test name
Test status
Simulation time	786198089 ps
CPU time	2.89 seconds
Started	Apr 18 02:30:56 PM PDT 24
Finished	Apr 18 02:31:00 PM PDT 24
Peak memory	222132 kb
Host	smart-5f372e0d-9071-4dcb-b74f-d4942ac69827
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777747081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.2777747081
Directory	/workspace/4.sram_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.sram_ctrl_smoke.1952109109
Short name	T390
Test name
Test status
Simulation time	816579681 ps
CPU time	8.18 seconds
Started	Apr 18 02:30:53 PM PDT 24
Finished	Apr 18 02:31:02 PM PDT 24
Peak memory	203028 kb
Host	smart-78b67c38-80e9-4a42-9891-25ae26f3cb9b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952109109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1952109109
Directory	/workspace/4.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_all.4286150813
Short name	T826
Test name
Test status
Simulation time	132438172880 ps
CPU time	1897.03 seconds
Started	Apr 18 02:30:57 PM PDT 24
Finished	Apr 18 03:02:35 PM PDT 24
Peak memory	380044 kb
Host	smart-479a9cec-036b-46ad-bf1c-992ed9cac6bb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286150813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.4286150813
Directory	/workspace/4.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.189004846
Short name	T304
Test name
Test status
Simulation time	759534585 ps
CPU time	12.01 seconds
Started	Apr 18 02:30:57 PM PDT 24
Finished	Apr 18 02:31:10 PM PDT 24
Peak memory	211300 kb
Host	smart-ef94aa22-aff5-4a2b-8a39-7a70427928fd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=189004846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.189004846
Directory	/workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1798658897
Short name	T96
Test name
Test status
Simulation time	18531307780 ps
CPU time	343.89 seconds
Started	Apr 18 02:30:53 PM PDT 24
Finished	Apr 18 02:36:38 PM PDT 24
Peak memory	203224 kb
Host	smart-04c0c2ec-271e-45e8-abf4-8306eba48501
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798658897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.1798658897
Directory	/workspace/4.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1846669444
Short name	T735
Test name
Test status
Simulation time	791717648 ps
CPU time	137.91 seconds
Started	Apr 18 02:30:55 PM PDT 24
Finished	Apr 18 02:33:13 PM PDT 24
Peak memory	361324 kb
Host	smart-bb690390-d9f2-46a9-bd57-7ee2c25c4ca7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846669444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1846669444
Directory	/workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2985923350
Short name	T501
Test name
Test status
Simulation time	8450596845 ps
CPU time	669.08 seconds
Started	Apr 18 02:41:56 PM PDT 24
Finished	Apr 18 02:53:05 PM PDT 24
Peak memory	376908 kb
Host	smart-6c626d3c-ab16-4f85-9d44-c6b0f1d2ba14
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985923350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.2985923350
Directory	/workspace/40.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/40.sram_ctrl_alert_test.1657326954
Short name	T513
Test name
Test status
Simulation time	42244065 ps
CPU time	0.66 seconds
Started	Apr 18 02:42:10 PM PDT 24
Finished	Apr 18 02:42:11 PM PDT 24
Peak memory	202768 kb
Host	smart-afc92225-de25-4ea9-ab4c-d5e20f3cc7e9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657326954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1657326954
Directory	/workspace/40.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.sram_ctrl_bijection.1016058081
Short name	T406
Test name
Test status
Simulation time	57277813747 ps
CPU time	1218.29 seconds
Started	Apr 18 02:41:51 PM PDT 24
Finished	Apr 18 03:02:10 PM PDT 24
Peak memory	203308 kb
Host	smart-ba931e9d-3148-4f19-98a4-d1cb9e025dbf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016058081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .1016058081
Directory	/workspace/40.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/40.sram_ctrl_executable.4234088463
Short name	T916
Test name
Test status
Simulation time	19642740250 ps
CPU time	1415.15 seconds
Started	Apr 18 02:42:00 PM PDT 24
Finished	Apr 18 03:05:36 PM PDT 24
Peak memory	380028 kb
Host	smart-7b992589-baf0-460e-bbaf-e405e64b3d73
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234088463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.4234088463
Directory	/workspace/40.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/40.sram_ctrl_lc_escalation.477462140
Short name	T193
Test name
Test status
Simulation time	9068439321 ps
CPU time	55.45 seconds
Started	Apr 18 02:41:57 PM PDT 24
Finished	Apr 18 02:42:53 PM PDT 24
Peak memory	203112 kb
Host	smart-022d3a97-b413-4108-9c77-969004547669
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477462140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc alation.477462140
Directory	/workspace/40.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/40.sram_ctrl_max_throughput.2944303052
Short name	T44
Test name
Test status
Simulation time	695471514 ps
CPU time	11.14 seconds
Started	Apr 18 02:41:57 PM PDT 24
Finished	Apr 18 02:42:08 PM PDT 24
Peak memory	235752 kb
Host	smart-6f25dbb7-a50f-4fbf-b6a0-8e581c50d242
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944303052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 40.sram_ctrl_max_throughput.2944303052
Directory	/workspace/40.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1572982171
Short name	T567
Test name
Test status
Simulation time	2014419466 ps
CPU time	69.02 seconds
Started	Apr 18 02:42:02 PM PDT 24
Finished	Apr 18 02:43:11 PM PDT 24
Peak memory	211252 kb
Host	smart-ccded855-0b66-4e82-b265-fbad8176dbb7
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572982171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.1572982171
Directory	/workspace/40.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_walk.3799929394
Short name	T816
Test name
Test status
Simulation time	4296835933 ps
CPU time	128.99 seconds
Started	Apr 18 02:42:01 PM PDT 24
Finished	Apr 18 02:44:11 PM PDT 24
Peak memory	203900 kb
Host	smart-f25bc1c6-b15f-4779-92ec-20f71684ac0f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799929394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.3799929394
Directory	/workspace/40.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/40.sram_ctrl_multiple_keys.3128910173
Short name	T791
Test name
Test status
Simulation time	1738515944 ps
CPU time	37.08 seconds
Started	Apr 18 02:41:51 PM PDT 24
Finished	Apr 18 02:42:29 PM PDT 24
Peak memory	202904 kb
Host	smart-e2cd3b15-37ba-4295-8a3f-5b7251a5924a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128910173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.3128910173
Directory	/workspace/40.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access.2506333463
Short name	T809
Test name
Test status
Simulation time	805765253 ps
CPU time	5.31 seconds
Started	Apr 18 02:41:56 PM PDT 24
Finished	Apr 18 02:42:01 PM PDT 24
Peak memory	209136 kb
Host	smart-5ee48a36-8fcc-447c-af85-fd8267a200e8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506333463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.2506333463
Directory	/workspace/40.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4184864112
Short name	T905
Test name
Test status
Simulation time	16374812405 ps
CPU time	283.01 seconds
Started	Apr 18 02:41:57 PM PDT 24
Finished	Apr 18 02:46:41 PM PDT 24
Peak memory	203184 kb
Host	smart-b5a25ccc-be00-47c7-b902-8a535e8d046f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184864112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.4184864112
Directory	/workspace/40.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/40.sram_ctrl_ram_cfg.2758682370
Short name	T413
Test name
Test status
Simulation time	359359931 ps
CPU time	3.33 seconds
Started	Apr 18 02:42:03 PM PDT 24
Finished	Apr 18 02:42:06 PM PDT 24
Peak memory	203060 kb
Host	smart-034c0c21-3192-41dc-b26e-d3c0c0d3dcaa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758682370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2758682370
Directory	/workspace/40.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/40.sram_ctrl_regwen.263136957
Short name	T685
Test name
Test status
Simulation time	4578386459 ps
CPU time	339 seconds
Started	Apr 18 02:42:02 PM PDT 24
Finished	Apr 18 02:47:42 PM PDT 24
Peak memory	367696 kb
Host	smart-4958c067-389c-45f3-bdc9-b20de18813be
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263136957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.263136957
Directory	/workspace/40.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/40.sram_ctrl_smoke.3510434210
Short name	T159
Test name
Test status
Simulation time	909921741 ps
CPU time	11.39 seconds
Started	Apr 18 02:41:47 PM PDT 24
Finished	Apr 18 02:41:59 PM PDT 24
Peak memory	203028 kb
Host	smart-b71e1952-dc48-4af1-ae94-fe207fdf40b8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510434210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3510434210
Directory	/workspace/40.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_all.3266139882
Short name	T873
Test name
Test status
Simulation time	170618680128 ps
CPU time	3829.9 seconds
Started	Apr 18 02:42:02 PM PDT 24
Finished	Apr 18 03:45:53 PM PDT 24
Peak memory	385140 kb
Host	smart-eaa19cb2-add1-4641-b178-20aea141cf88
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266139882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.3266139882
Directory	/workspace/40.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1836862651
Short name	T397
Test name
Test status
Simulation time	4649739092 ps
CPU time	18.63 seconds
Started	Apr 18 02:42:04 PM PDT 24
Finished	Apr 18 02:42:23 PM PDT 24
Peak memory	211400 kb
Host	smart-95dd663a-4b63-465e-84ca-e65f7af319dd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1836862651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1836862651
Directory	/workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.4124422197
Short name	T875
Test name
Test status
Simulation time	9979498588 ps
CPU time	283.38 seconds
Started	Apr 18 02:41:57 PM PDT 24
Finished	Apr 18 02:46:40 PM PDT 24
Peak memory	203140 kb
Host	smart-1414ebf6-a223-42ff-962e-91f49bb0fbe8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124422197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.4124422197
Directory	/workspace/40.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1945123541
Short name	T757
Test name
Test status
Simulation time	768639517 ps
CPU time	51.78 seconds
Started	Apr 18 02:41:57 PM PDT 24
Finished	Apr 18 02:42:49 PM PDT 24
Peak memory	295528 kb
Host	smart-231df5cd-5d87-4621-9b02-93d810725159
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945123541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1945123541
Directory	/workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3077163727
Short name	T553
Test name
Test status
Simulation time	10631050522 ps
CPU time	353.29 seconds
Started	Apr 18 02:42:16 PM PDT 24
Finished	Apr 18 02:48:10 PM PDT 24
Peak memory	375884 kb
Host	smart-c31ac23e-d3e5-40ba-8e9d-537ca8e77c3e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077163727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.3077163727
Directory	/workspace/41.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/41.sram_ctrl_alert_test.3622090403
Short name	T879
Test name
Test status
Simulation time	111871985 ps
CPU time	0.65 seconds
Started	Apr 18 02:42:28 PM PDT 24
Finished	Apr 18 02:42:29 PM PDT 24
Peak memory	202852 kb
Host	smart-27ca0865-ecd1-443e-b6dd-d4d06b924743
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622090403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.3622090403
Directory	/workspace/41.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.sram_ctrl_bijection.816075321
Short name	T827
Test name
Test status
Simulation time	19481929683 ps
CPU time	1256.04 seconds
Started	Apr 18 02:42:07 PM PDT 24
Finished	Apr 18 03:03:04 PM PDT 24
Peak memory	203504 kb
Host	smart-5589ce61-4935-499e-8c7c-b770b1ca260b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816075321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection. 816075321
Directory	/workspace/41.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/41.sram_ctrl_executable.662768840
Short name	T121
Test name
Test status
Simulation time	18023020849 ps
CPU time	406.12 seconds
Started	Apr 18 02:42:27 PM PDT 24
Finished	Apr 18 02:49:14 PM PDT 24
Peak memory	371332 kb
Host	smart-c881a5d5-ad92-49e0-b890-5e50214e1fcb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662768840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executabl e.662768840
Directory	/workspace/41.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/41.sram_ctrl_lc_escalation.3344427920
Short name	T897
Test name
Test status
Simulation time	119166154644 ps
CPU time	85.48 seconds
Started	Apr 18 02:42:17 PM PDT 24
Finished	Apr 18 02:43:43 PM PDT 24
Peak memory	203104 kb
Host	smart-8769fa6d-bfde-475d-b1b0-72572b264e7e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344427920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.3344427920
Directory	/workspace/41.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/41.sram_ctrl_max_throughput.984520614
Short name	T882
Test name
Test status
Simulation time	1421646116 ps
CPU time	6.78 seconds
Started	Apr 18 02:42:22 PM PDT 24
Finished	Apr 18 02:42:30 PM PDT 24
Peak memory	211192 kb
Host	smart-5702ac66-bce0-4803-b256-6f7c91eb3998
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984520614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.sram_ctrl_max_throughput.984520614
Directory	/workspace/41.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2677221419
Short name	T479
Test name
Test status
Simulation time	9293365093 ps
CPU time	145.24 seconds
Started	Apr 18 02:42:27 PM PDT 24
Finished	Apr 18 02:44:53 PM PDT 24
Peak memory	211200 kb
Host	smart-2f758848-68e0-4a03-b17e-6852c9d483ed
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677221419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.2677221419
Directory	/workspace/41.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_walk.3260582668
Short name	T904
Test name
Test status
Simulation time	27512426026 ps
CPU time	143.43 seconds
Started	Apr 18 02:42:23 PM PDT 24
Finished	Apr 18 02:44:47 PM PDT 24
Peak memory	203588 kb
Host	smart-2f3c2afb-9486-4314-92dd-468580f67e3c
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260582668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.3260582668
Directory	/workspace/41.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/41.sram_ctrl_multiple_keys.4280684645
Short name	T134
Test name
Test status
Simulation time	34020471982 ps
CPU time	854.9 seconds
Started	Apr 18 02:42:07 PM PDT 24
Finished	Apr 18 02:56:22 PM PDT 24
Peak memory	376008 kb
Host	smart-f3936774-45af-4dac-9cc0-19082e5d1854
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280684645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.4280684645
Directory	/workspace/41.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access.704331799
Short name	T192
Test name
Test status
Simulation time	1619453240 ps
CPU time	21.88 seconds
Started	Apr 18 02:42:13 PM PDT 24
Finished	Apr 18 02:42:36 PM PDT 24
Peak memory	203100 kb
Host	smart-2e6465bc-b75d-4d8b-b111-42d12b32201b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704331799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s ram_ctrl_partial_access.704331799
Directory	/workspace/41.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.707772244
Short name	T362
Test name
Test status
Simulation time	28626241113 ps
CPU time	362.34 seconds
Started	Apr 18 02:42:17 PM PDT 24
Finished	Apr 18 02:48:20 PM PDT 24
Peak memory	203140 kb
Host	smart-12e3134b-d658-4448-9515-555f813eeeab
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707772244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.sram_ctrl_partial_access_b2b.707772244
Directory	/workspace/41.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/41.sram_ctrl_ram_cfg.2710320521
Short name	T280
Test name
Test status
Simulation time	1411797124 ps
CPU time	3.81 seconds
Started	Apr 18 02:42:26 PM PDT 24
Finished	Apr 18 02:42:30 PM PDT 24
Peak memory	203028 kb
Host	smart-ef7db57a-c3d5-40c6-81c2-974d963f4057
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710320521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2710320521
Directory	/workspace/41.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/41.sram_ctrl_regwen.3203528520
Short name	T893
Test name
Test status
Simulation time	2339219331 ps
CPU time	1072.83 seconds
Started	Apr 18 02:42:22 PM PDT 24
Finished	Apr 18 03:00:15 PM PDT 24
Peak memory	375856 kb
Host	smart-2d27a833-60b9-4408-aa56-608e404b11df
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203528520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3203528520
Directory	/workspace/41.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/41.sram_ctrl_smoke.3333510241
Short name	T191
Test name
Test status
Simulation time	2483684541 ps
CPU time	19.86 seconds
Started	Apr 18 02:42:09 PM PDT 24
Finished	Apr 18 02:42:30 PM PDT 24
Peak memory	203132 kb
Host	smart-6db5672c-2fbf-4cf8-93be-1ae1fa281832
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333510241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3333510241
Directory	/workspace/41.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3163819310
Short name	T464
Test name
Test status
Simulation time	11559278275 ps
CPU time	167.42 seconds
Started	Apr 18 02:42:12 PM PDT 24
Finished	Apr 18 02:45:00 PM PDT 24
Peak memory	203176 kb
Host	smart-bce55c17-8fd5-45a6-9af1-ee4b94e3e980
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163819310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.3163819310
Directory	/workspace/41.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.4208548879
Short name	T545
Test name
Test status
Simulation time	1361985249 ps
CPU time	8.7 seconds
Started	Apr 18 02:42:17 PM PDT 24
Finished	Apr 18 02:42:26 PM PDT 24
Peak memory	220912 kb
Host	smart-12032e12-4838-4fcb-a5f0-8e9f0d9619b0
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208548879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.4208548879
Directory	/workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2104473227
Short name	T231
Test name
Test status
Simulation time	47378584849 ps
CPU time	856.28 seconds
Started	Apr 18 02:42:43 PM PDT 24
Finished	Apr 18 02:57:00 PM PDT 24
Peak memory	377532 kb
Host	smart-b5d92ab9-223d-4ff8-b925-bcc84bc0a021
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104473227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.2104473227
Directory	/workspace/42.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/42.sram_ctrl_alert_test.2945263050
Short name	T25
Test name
Test status
Simulation time	41327917 ps
CPU time	0.63 seconds
Started	Apr 18 02:42:58 PM PDT 24
Finished	Apr 18 02:42:59 PM PDT 24
Peak memory	202840 kb
Host	smart-4dcce8a8-7a6b-4c6e-9d5b-f194e7ad1ec4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945263050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.2945263050
Directory	/workspace/42.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.sram_ctrl_bijection.1029724525
Short name	T258
Test name
Test status
Simulation time	49204063120 ps
CPU time	740.08 seconds
Started	Apr 18 02:42:34 PM PDT 24
Finished	Apr 18 02:54:54 PM PDT 24
Peak memory	203100 kb
Host	smart-1e388560-51a3-4109-934c-f85a5db21369
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029724525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .1029724525
Directory	/workspace/42.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/42.sram_ctrl_executable.2933349643
Short name	T518
Test name
Test status
Simulation time	3021358972 ps
CPU time	191.45 seconds
Started	Apr 18 02:42:45 PM PDT 24
Finished	Apr 18 02:45:57 PM PDT 24
Peak memory	358264 kb
Host	smart-92c24dbb-487e-4086-b920-65d0fd036476
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933349643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.2933349643
Directory	/workspace/42.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/42.sram_ctrl_lc_escalation.515464074
Short name	T272
Test name
Test status
Simulation time	11657442408 ps
CPU time	66.82 seconds
Started	Apr 18 02:42:38 PM PDT 24
Finished	Apr 18 02:43:45 PM PDT 24
Peak memory	211328 kb
Host	smart-e8d6f693-3cab-43ff-8282-2849a1f048be
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515464074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_esc alation.515464074
Directory	/workspace/42.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/42.sram_ctrl_max_throughput.717417119
Short name	T611
Test name
Test status
Simulation time	1599813973 ps
CPU time	151.89 seconds
Started	Apr 18 02:42:40 PM PDT 24
Finished	Apr 18 02:45:12 PM PDT 24
Peak memory	370644 kb
Host	smart-9c9ef646-1fc1-4d99-aa25-19009c3f9b96
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717417119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.sram_ctrl_max_throughput.717417119
Directory	/workspace/42.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_partial_access.779722013
Short name	T469
Test name
Test status
Simulation time	10871478981 ps
CPU time	80.13 seconds
Started	Apr 18 02:42:49 PM PDT 24
Finished	Apr 18 02:44:10 PM PDT 24
Peak memory	211288 kb
Host	smart-ce849dc5-b44c-4a0f-ae39-35736b1fbd0b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779722013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sram_ctrl_mem_partial_access.779722013
Directory	/workspace/42.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_walk.1151113077
Short name	T659
Test name
Test status
Simulation time	40505143112 ps
CPU time	300.63 seconds
Started	Apr 18 02:42:46 PM PDT 24
Finished	Apr 18 02:47:47 PM PDT 24
Peak memory	203752 kb
Host	smart-8dd3d21f-2ab1-4faf-8f83-64819a1c8978
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151113077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.1151113077
Directory	/workspace/42.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/42.sram_ctrl_multiple_keys.2206541342
Short name	T183
Test name
Test status
Simulation time	1460254108 ps
CPU time	67.75 seconds
Started	Apr 18 02:42:32 PM PDT 24
Finished	Apr 18 02:43:40 PM PDT 24
Peak memory	292476 kb
Host	smart-908acebf-1be1-4b20-a2de-494865650d58
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206541342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.2206541342
Directory	/workspace/42.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access.1748146051
Short name	T769
Test name
Test status
Simulation time	1107705190 ps
CPU time	19.53 seconds
Started	Apr 18 02:42:31 PM PDT 24
Finished	Apr 18 02:42:52 PM PDT 24
Peak memory	203044 kb
Host	smart-580c19d8-a6e0-4b8d-80e5-a390969c3478
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748146051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.1748146051
Directory	/workspace/42.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.900500621
Short name	T3
Test name
Test status
Simulation time	43431457105 ps
CPU time	532.69 seconds
Started	Apr 18 02:42:37 PM PDT 24
Finished	Apr 18 02:51:30 PM PDT 24
Peak memory	203092 kb
Host	smart-a6131172-9c30-4b3d-83e3-38fa6e9e92f7
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900500621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.sram_ctrl_partial_access_b2b.900500621
Directory	/workspace/42.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/42.sram_ctrl_ram_cfg.3257740466
Short name	T417
Test name
Test status
Simulation time	2235518407 ps
CPU time	3.47 seconds
Started	Apr 18 02:42:45 PM PDT 24
Finished	Apr 18 02:42:49 PM PDT 24
Peak memory	203120 kb
Host	smart-0cc0db75-04ac-493a-b349-f950709229ee
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257740466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3257740466
Directory	/workspace/42.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/42.sram_ctrl_regwen.3371253218
Short name	T761
Test name
Test status
Simulation time	32976175631 ps
CPU time	159.42 seconds
Started	Apr 18 02:42:44 PM PDT 24
Finished	Apr 18 02:45:24 PM PDT 24
Peak memory	259292 kb
Host	smart-06bb118b-ae37-4f40-84b5-539f9accf91d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371253218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3371253218
Directory	/workspace/42.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/42.sram_ctrl_smoke.866945624
Short name	T14
Test name
Test status
Simulation time	2108639164 ps
CPU time	109.16 seconds
Started	Apr 18 02:42:37 PM PDT 24
Finished	Apr 18 02:44:26 PM PDT 24
Peak memory	367556 kb
Host	smart-e5c561e4-5cfa-460c-a5b1-28db32041cd3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866945624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.866945624
Directory	/workspace/42.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_all.2779759632
Short name	T582
Test name
Test status
Simulation time	818741943219 ps
CPU time	8426.74 seconds
Started	Apr 18 02:42:59 PM PDT 24
Finished	Apr 18 05:03:27 PM PDT 24
Peak memory	383088 kb
Host	smart-27bc15ee-8443-4570-916c-0525e2822b6d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779759632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.2779759632
Directory	/workspace/42.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1250176090
Short name	T485
Test name
Test status
Simulation time	832370423 ps
CPU time	28.37 seconds
Started	Apr 18 02:42:59 PM PDT 24
Finished	Apr 18 02:43:28 PM PDT 24
Peak memory	211224 kb
Host	smart-d9124d47-c3e4-4749-b12c-437f2056b3c5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1250176090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.1250176090
Directory	/workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3158804552
Short name	T740
Test name
Test status
Simulation time	11615515906 ps
CPU time	146.82 seconds
Started	Apr 18 02:42:36 PM PDT 24
Finished	Apr 18 02:45:03 PM PDT 24
Peak memory	203152 kb
Host	smart-4e045aaa-a0d7-412b-a1ab-db468ffec635
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158804552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.3158804552
Directory	/workspace/42.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.180456890
Short name	T399
Test name
Test status
Simulation time	685343763 ps
CPU time	6.47 seconds
Started	Apr 18 02:42:39 PM PDT 24
Finished	Apr 18 02:42:45 PM PDT 24
Peak memory	211208 kb
Host	smart-804bfb74-b7af-4969-9f66-15804492ed74
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180456890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_throughput_w_partial_write.180456890
Directory	/workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.329645734
Short name	T371
Test name
Test status
Simulation time	12489959454 ps
CPU time	880.44 seconds
Started	Apr 18 02:43:10 PM PDT 24
Finished	Apr 18 02:57:51 PM PDT 24
Peak memory	365828 kb
Host	smart-2522b73b-c8a4-466a-a863-063c329c415e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329645734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 43.sram_ctrl_access_during_key_req.329645734
Directory	/workspace/43.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/43.sram_ctrl_alert_test.2145152779
Short name	T162
Test name
Test status
Simulation time	26807261 ps
CPU time	0.65 seconds
Started	Apr 18 02:43:26 PM PDT 24
Finished	Apr 18 02:43:27 PM PDT 24
Peak memory	202644 kb
Host	smart-4d11783f-ceb9-4a6f-9459-b0b5e7ede8f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145152779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2145152779
Directory	/workspace/43.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.sram_ctrl_bijection.81531940
Short name	T583
Test name
Test status
Simulation time	14010006550 ps
CPU time	924.04 seconds
Started	Apr 18 02:43:04 PM PDT 24
Finished	Apr 18 02:58:29 PM PDT 24
Peak memory	203120 kb
Host	smart-ea23a44e-b899-4198-896f-c0d25f903e0d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81531940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.81531940
Directory	/workspace/43.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/43.sram_ctrl_executable.1329605722
Short name	T849
Test name
Test status
Simulation time	9803109579 ps
CPU time	1112.92 seconds
Started	Apr 18 02:43:09 PM PDT 24
Finished	Apr 18 03:01:42 PM PDT 24
Peak memory	375868 kb
Host	smart-47a48fc6-6ef3-4193-b1f8-fca42cbaf806
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329605722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.1329605722
Directory	/workspace/43.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/43.sram_ctrl_lc_escalation.2647410168
Short name	T625
Test name
Test status
Simulation time	50517659256 ps
CPU time	76.47 seconds
Started	Apr 18 02:43:04 PM PDT 24
Finished	Apr 18 02:44:21 PM PDT 24
Peak memory	203068 kb
Host	smart-9a58f62e-0e71-4fa3-a749-7bb929fb9a0c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647410168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.2647410168
Directory	/workspace/43.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/43.sram_ctrl_max_throughput.1061348446
Short name	T759
Test name
Test status
Simulation time	1494885832 ps
CPU time	46.04 seconds
Started	Apr 18 02:43:04 PM PDT 24
Finished	Apr 18 02:43:50 PM PDT 24
Peak memory	310008 kb
Host	smart-e356b354-a7c8-4715-9e2d-65d9e18a3c2f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061348446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.1061348446
Directory	/workspace/43.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1300855508
Short name	T585
Test name
Test status
Simulation time	12482506570 ps
CPU time	162.91 seconds
Started	Apr 18 02:43:20 PM PDT 24
Finished	Apr 18 02:46:04 PM PDT 24
Peak memory	211312 kb
Host	smart-17451a23-e9dc-4979-bf82-86b6f435175a
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300855508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.1300855508
Directory	/workspace/43.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_walk.1722794206
Short name	T592
Test name
Test status
Simulation time	3983879148 ps
CPU time	242.26 seconds
Started	Apr 18 02:43:19 PM PDT 24
Finished	Apr 18 02:47:22 PM PDT 24
Peak memory	203200 kb
Host	smart-b46951aa-8097-4a91-994b-892272bd470b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722794206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.1722794206
Directory	/workspace/43.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/43.sram_ctrl_multiple_keys.186831672
Short name	T140
Test name
Test status
Simulation time	15411455456 ps
CPU time	72.37 seconds
Started	Apr 18 02:42:59 PM PDT 24
Finished	Apr 18 02:44:12 PM PDT 24
Peak memory	267760 kb
Host	smart-842cf1fc-0abf-41ea-922a-13fa87408953
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186831672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multip le_keys.186831672
Directory	/workspace/43.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access.3577813274
Short name	T844
Test name
Test status
Simulation time	8520857450 ps
CPU time	35.35 seconds
Started	Apr 18 02:43:06 PM PDT 24
Finished	Apr 18 02:43:41 PM PDT 24
Peak memory	293216 kb
Host	smart-6140cf74-8e9f-4d3e-9fa9-bc36bd978285
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577813274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.3577813274
Directory	/workspace/43.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1183006262
Short name	T702
Test name
Test status
Simulation time	157794632368 ps
CPU time	489.04 seconds
Started	Apr 18 02:43:05 PM PDT 24
Finished	Apr 18 02:51:14 PM PDT 24
Peak memory	203156 kb
Host	smart-77ae2a35-798a-4951-bde9-31a990079bce
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183006262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.1183006262
Directory	/workspace/43.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/43.sram_ctrl_ram_cfg.34619049
Short name	T298
Test name
Test status
Simulation time	1342709841 ps
CPU time	3.49 seconds
Started	Apr 18 02:43:09 PM PDT 24
Finished	Apr 18 02:43:13 PM PDT 24
Peak memory	203048 kb
Host	smart-8263d4fc-c658-4b00-ae4f-189f577d09bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34619049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.34619049
Directory	/workspace/43.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/43.sram_ctrl_regwen.920233526
Short name	T537
Test name
Test status
Simulation time	4108841959 ps
CPU time	1200.17 seconds
Started	Apr 18 02:43:09 PM PDT 24
Finished	Apr 18 03:03:10 PM PDT 24
Peak memory	384032 kb
Host	smart-d87663a4-03db-4d7d-b245-12cf20ee0272
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920233526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.920233526
Directory	/workspace/43.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/43.sram_ctrl_smoke.1561015809
Short name	T888
Test name
Test status
Simulation time	383714572 ps
CPU time	5.08 seconds
Started	Apr 18 02:42:58 PM PDT 24
Finished	Apr 18 02:43:03 PM PDT 24
Peak memory	203020 kb
Host	smart-82e78794-6447-4f29-878a-42df99891052
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561015809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1561015809
Directory	/workspace/43.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all.2119483687
Short name	T671
Test name
Test status
Simulation time	71646405202 ps
CPU time	3780.12 seconds
Started	Apr 18 02:43:26 PM PDT 24
Finished	Apr 18 03:46:27 PM PDT 24
Peak memory	383168 kb
Host	smart-35688fa0-bf03-4abf-908b-c579caa911dd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119483687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.2119483687
Directory	/workspace/43.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1183099396
Short name	T693
Test name
Test status
Simulation time	297043689 ps
CPU time	9.07 seconds
Started	Apr 18 02:43:20 PM PDT 24
Finished	Apr 18 02:43:30 PM PDT 24
Peak memory	211300 kb
Host	smart-598b37b6-6dd4-4c8f-8348-7f8a3f252b6f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1183099396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1183099396
Directory	/workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2042809612
Short name	T222
Test name
Test status
Simulation time	22977033487 ps
CPU time	292.8 seconds
Started	Apr 18 02:43:05 PM PDT 24
Finished	Apr 18 02:47:58 PM PDT 24
Peak memory	203152 kb
Host	smart-c13b575a-f5a4-4099-9ed0-54089ac21602
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042809612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.2042809612
Directory	/workspace/43.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1826179270
Short name	T907
Test name
Test status
Simulation time	709739459 ps
CPU time	17.03 seconds
Started	Apr 18 02:43:04 PM PDT 24
Finished	Apr 18 02:43:22 PM PDT 24
Peak memory	252040 kb
Host	smart-8776972c-bf85-49fb-ab22-a7a07c908ccb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826179270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1826179270
Directory	/workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1793564549
Short name	T88
Test name
Test status
Simulation time	60835874112 ps
CPU time	1005.96 seconds
Started	Apr 18 02:43:39 PM PDT 24
Finished	Apr 18 03:00:26 PM PDT 24
Peak memory	380064 kb
Host	smart-f04ae44a-b828-40ab-b3f1-3065b7bc9f44
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793564549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.1793564549
Directory	/workspace/44.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/44.sram_ctrl_alert_test.469590828
Short name	T877
Test name
Test status
Simulation time	24639888 ps
CPU time	0.64 seconds
Started	Apr 18 02:43:54 PM PDT 24
Finished	Apr 18 02:43:55 PM PDT 24
Peak memory	202804 kb
Host	smart-0d099747-64b2-4f60-ba0a-7484839b3956
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469590828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.469590828
Directory	/workspace/44.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.sram_ctrl_bijection.3454438598
Short name	T452
Test name
Test status
Simulation time	111451707087 ps
CPU time	1861.52 seconds
Started	Apr 18 02:43:26 PM PDT 24
Finished	Apr 18 03:14:28 PM PDT 24
Peak memory	203336 kb
Host	smart-cb440dd1-f392-4600-b2ea-ae2328deb5e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454438598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .3454438598
Directory	/workspace/44.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/44.sram_ctrl_lc_escalation.1078105248
Short name	T924
Test name
Test status
Simulation time	19799292748 ps
CPU time	23.84 seconds
Started	Apr 18 02:43:39 PM PDT 24
Finished	Apr 18 02:44:03 PM PDT 24
Peak memory	211320 kb
Host	smart-cdfbca17-e968-4f0d-a718-905b712110cf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078105248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.1078105248
Directory	/workspace/44.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/44.sram_ctrl_max_throughput.3128180500
Short name	T138
Test name
Test status
Simulation time	1118433351 ps
CPU time	9.15 seconds
Started	Apr 18 02:43:30 PM PDT 24
Finished	Apr 18 02:43:40 PM PDT 24
Peak memory	225568 kb
Host	smart-ae6bece2-fd94-4b4a-8c04-00c0ce215106
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128180500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.3128180500
Directory	/workspace/44.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1183948319
Short name	T76
Test name
Test status
Simulation time	4684491298 ps
CPU time	68.68 seconds
Started	Apr 18 02:43:54 PM PDT 24
Finished	Apr 18 02:45:03 PM PDT 24
Peak memory	211344 kb
Host	smart-c8945690-aa69-459a-82b9-5c5a2849770b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183948319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.1183948319
Directory	/workspace/44.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_walk.3328186560
Short name	T354
Test name
Test status
Simulation time	16416362701 ps
CPU time	252.45 seconds
Started	Apr 18 02:43:53 PM PDT 24
Finished	Apr 18 02:48:06 PM PDT 24
Peak memory	203744 kb
Host	smart-fe72660b-51ab-406d-828d-65d67ecf7081
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328186560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.3328186560
Directory	/workspace/44.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/44.sram_ctrl_multiple_keys.2812769658
Short name	T387
Test name
Test status
Simulation time	36079892160 ps
CPU time	147.67 seconds
Started	Apr 18 02:43:25 PM PDT 24
Finished	Apr 18 02:45:53 PM PDT 24
Peak memory	376896 kb
Host	smart-66f117e7-adc7-4497-9832-02e102d4ef13
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812769658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.2812769658
Directory	/workspace/44.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access.1721249923
Short name	T558
Test name
Test status
Simulation time	2851042986 ps
CPU time	4.06 seconds
Started	Apr 18 02:43:31 PM PDT 24
Finished	Apr 18 02:43:35 PM PDT 24
Peak memory	202864 kb
Host	smart-f4002350-7908-4be5-82f7-c2755bdfdebb
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721249923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.1721249923
Directory	/workspace/44.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1194572746
Short name	T181
Test name
Test status
Simulation time	4210371122 ps
CPU time	198.55 seconds
Started	Apr 18 02:43:32 PM PDT 24
Finished	Apr 18 02:46:51 PM PDT 24
Peak memory	203064 kb
Host	smart-8e926276-1687-4d0e-a6dc-cf334e278757
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194572746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.1194572746
Directory	/workspace/44.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/44.sram_ctrl_ram_cfg.1150945588
Short name	T166
Test name
Test status
Simulation time	5611550471 ps
CPU time	3.82 seconds
Started	Apr 18 02:43:47 PM PDT 24
Finished	Apr 18 02:43:51 PM PDT 24
Peak memory	203160 kb
Host	smart-e60630f9-bcbf-4a4e-b2bc-da41d8b366df
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150945588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1150945588
Directory	/workspace/44.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/44.sram_ctrl_regwen.3598657529
Short name	T205
Test name
Test status
Simulation time	6710170511 ps
CPU time	597.09 seconds
Started	Apr 18 02:43:45 PM PDT 24
Finished	Apr 18 02:53:42 PM PDT 24
Peak memory	377744 kb
Host	smart-2fe11135-fde2-4107-b780-fb30c9131e32
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598657529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3598657529
Directory	/workspace/44.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/44.sram_ctrl_smoke.3959660803
Short name	T737
Test name
Test status
Simulation time	4137887744 ps
CPU time	15.12 seconds
Started	Apr 18 02:43:25 PM PDT 24
Finished	Apr 18 02:43:40 PM PDT 24
Peak memory	203036 kb
Host	smart-d5a9ca40-6b6f-4a96-8f51-1aded7d9aec5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959660803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3959660803
Directory	/workspace/44.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all.3484136168
Short name	T902
Test name
Test status
Simulation time	35644929560 ps
CPU time	217.68 seconds
Started	Apr 18 02:43:56 PM PDT 24
Finished	Apr 18 02:47:35 PM PDT 24
Peak memory	309192 kb
Host	smart-1576117a-afbf-4c2b-b047-b05b1f16bebc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484136168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.3484136168
Directory	/workspace/44.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2777204393
Short name	T656
Test name
Test status
Simulation time	2192414746 ps
CPU time	28.6 seconds
Started	Apr 18 02:43:54 PM PDT 24
Finished	Apr 18 02:44:23 PM PDT 24
Peak memory	211284 kb
Host	smart-0215b4cf-2f3a-4d0f-8213-28f7a5dfcb7a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2777204393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2777204393
Directory	/workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1655072948
Short name	T763
Test name
Test status
Simulation time	15769520520 ps
CPU time	266.86 seconds
Started	Apr 18 02:43:31 PM PDT 24
Finished	Apr 18 02:47:58 PM PDT 24
Peak memory	203164 kb
Host	smart-8a5f62dd-6f55-415c-9c52-9a204c8f6151
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655072948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.1655072948
Directory	/workspace/44.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3324252844
Short name	T840
Test name
Test status
Simulation time	708919615 ps
CPU time	16.28 seconds
Started	Apr 18 02:43:35 PM PDT 24
Finished	Apr 18 02:43:52 PM PDT 24
Peak memory	252048 kb
Host	smart-453de117-b433-4bf9-94a6-765c1daf0575
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324252844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.3324252844
Directory	/workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3910518893
Short name	T394
Test name
Test status
Simulation time	8329951948 ps
CPU time	490.97 seconds
Started	Apr 18 02:44:09 PM PDT 24
Finished	Apr 18 02:52:20 PM PDT 24
Peak memory	370724 kb
Host	smart-d52d2c06-8018-4cd3-988b-fc791bd085fb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910518893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.3910518893
Directory	/workspace/45.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/45.sram_ctrl_alert_test.485010539
Short name	T557
Test name
Test status
Simulation time	14305136 ps
CPU time	0.62 seconds
Started	Apr 18 02:44:15 PM PDT 24
Finished	Apr 18 02:44:16 PM PDT 24
Peak memory	202212 kb
Host	smart-ed3987e3-bf96-49ca-88f4-9e65a52f12fe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485010539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.485010539
Directory	/workspace/45.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.sram_ctrl_bijection.2964218343
Short name	T676
Test name
Test status
Simulation time	21752873669 ps
CPU time	1506.85 seconds
Started	Apr 18 02:44:01 PM PDT 24
Finished	Apr 18 03:09:08 PM PDT 24
Peak memory	203436 kb
Host	smart-51f3b9eb-2da8-4b09-9efb-bc4199ee2885
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964218343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .2964218343
Directory	/workspace/45.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/45.sram_ctrl_executable.3688307370
Short name	T503
Test name
Test status
Simulation time	6264550723 ps
CPU time	153.89 seconds
Started	Apr 18 02:44:09 PM PDT 24
Finished	Apr 18 02:46:44 PM PDT 24
Peak memory	371000 kb
Host	smart-06ae109a-6512-41ba-953e-3a85107e21d3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688307370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.3688307370
Directory	/workspace/45.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/45.sram_ctrl_lc_escalation.3222714975
Short name	T246
Test name
Test status
Simulation time	55783217647 ps
CPU time	83.47 seconds
Started	Apr 18 02:44:04 PM PDT 24
Finished	Apr 18 02:45:28 PM PDT 24
Peak memory	216160 kb
Host	smart-d6920772-1ae3-4a71-b4a1-3ff11ec2d032
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222714975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.3222714975
Directory	/workspace/45.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/45.sram_ctrl_max_throughput.2071720489
Short name	T864
Test name
Test status
Simulation time	758869335 ps
CPU time	128.96 seconds
Started	Apr 18 02:44:03 PM PDT 24
Finished	Apr 18 02:46:13 PM PDT 24
Peak memory	358360 kb
Host	smart-a5ccb86c-1f06-436b-8cf2-1ff9aed6f8bf
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071720489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.2071720489
Directory	/workspace/45.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2995201885
Short name	T487
Test name
Test status
Simulation time	2431087606 ps
CPU time	70.74 seconds
Started	Apr 18 02:44:14 PM PDT 24
Finished	Apr 18 02:45:25 PM PDT 24
Peak memory	211264 kb
Host	smart-9aaedb15-1d1b-48a5-96c9-d2c9e8e626a2
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995201885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.2995201885
Directory	/workspace/45.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_walk.2592379356
Short name	T448
Test name
Test status
Simulation time	10763338662 ps
CPU time	142.42 seconds
Started	Apr 18 02:44:14 PM PDT 24
Finished	Apr 18 02:46:37 PM PDT 24
Peak memory	203556 kb
Host	smart-bd951868-1f1d-4bd1-b11e-2a44f9b77b42
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592379356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.2592379356
Directory	/workspace/45.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/45.sram_ctrl_multiple_keys.887063754
Short name	T330
Test name
Test status
Simulation time	41881705694 ps
CPU time	384.87 seconds
Started	Apr 18 02:44:00 PM PDT 24
Finished	Apr 18 02:50:26 PM PDT 24
Peak memory	377924 kb
Host	smart-356fd077-bc57-45b4-ad89-264345a903f4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887063754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip le_keys.887063754
Directory	/workspace/45.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access.3668098158
Short name	T254
Test name
Test status
Simulation time	3549769884 ps
CPU time	24.53 seconds
Started	Apr 18 02:44:04 PM PDT 24
Finished	Apr 18 02:44:29 PM PDT 24
Peak memory	260020 kb
Host	smart-44fab3d0-5fd5-4a85-8d95-849447a11848
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668098158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.3668098158
Directory	/workspace/45.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.96223053
Short name	T935
Test name
Test status
Simulation time	117788093024 ps
CPU time	652.13 seconds
Started	Apr 18 02:44:05 PM PDT 24
Finished	Apr 18 02:54:57 PM PDT 24
Peak memory	203204 kb
Host	smart-9049f84c-998a-46b3-8a88-84f026154fca
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96223053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_partial_access_b2b.96223053
Directory	/workspace/45.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/45.sram_ctrl_ram_cfg.4233489265
Short name	T312
Test name
Test status
Simulation time	360677622 ps
CPU time	3.08 seconds
Started	Apr 18 02:44:18 PM PDT 24
Finished	Apr 18 02:44:21 PM PDT 24
Peak memory	203056 kb
Host	smart-95e6e7fe-5c8a-4e77-a029-02caf7910769
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233489265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.4233489265
Directory	/workspace/45.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/45.sram_ctrl_regwen.458702626
Short name	T845
Test name
Test status
Simulation time	3558944232 ps
CPU time	499.68 seconds
Started	Apr 18 02:44:14 PM PDT 24
Finished	Apr 18 02:52:34 PM PDT 24
Peak memory	361072 kb
Host	smart-ca1059dd-8a65-461f-b0d9-be60fbd20e1e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458702626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.458702626
Directory	/workspace/45.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/45.sram_ctrl_smoke.3349377198
Short name	T660
Test name
Test status
Simulation time	1297890374 ps
CPU time	20.37 seconds
Started	Apr 18 02:44:01 PM PDT 24
Finished	Apr 18 02:44:22 PM PDT 24
Peak memory	203028 kb
Host	smart-12d9e4cc-13d8-45c9-84fc-b3a734ea5cd8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349377198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3349377198
Directory	/workspace/45.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_all.1524759796
Short name	T860
Test name
Test status
Simulation time	100353260847 ps
CPU time	2389.58 seconds
Started	Apr 18 02:44:17 PM PDT 24
Finished	Apr 18 03:24:07 PM PDT 24
Peak memory	386180 kb
Host	smart-1470d16d-2cbb-4e22-8410-3880f4d762c6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524759796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.1524759796
Directory	/workspace/45.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1853099285
Short name	T49
Test name
Test status
Simulation time	10233152124 ps
CPU time	188.35 seconds
Started	Apr 18 02:44:17 PM PDT 24
Finished	Apr 18 02:47:26 PM PDT 24
Peak memory	380048 kb
Host	smart-68e6d82a-6cb3-41a3-8bd3-2c786f02e7f3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1853099285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1853099285
Directory	/workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2061676206
Short name	T287
Test name
Test status
Simulation time	9963070440 ps
CPU time	260.18 seconds
Started	Apr 18 02:44:02 PM PDT 24
Finished	Apr 18 02:48:23 PM PDT 24
Peak memory	203196 kb
Host	smart-17f193bd-6384-4c92-9943-6b93e7dc263d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061676206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.2061676206
Directory	/workspace/45.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.791631657
Short name	T786
Test name
Test status
Simulation time	779016735 ps
CPU time	108.88 seconds
Started	Apr 18 02:44:07 PM PDT 24
Finished	Apr 18 02:45:56 PM PDT 24
Peak memory	354320 kb
Host	smart-cb11cfa0-883e-4d5e-9e2d-1c48db76f8c5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791631657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_throughput_w_partial_write.791631657
Directory	/workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2585347190
Short name	T644
Test name
Test status
Simulation time	79193968597 ps
CPU time	1269.63 seconds
Started	Apr 18 02:44:24 PM PDT 24
Finished	Apr 18 03:05:34 PM PDT 24
Peak memory	379024 kb
Host	smart-98cd8a5d-7baa-47ae-bb35-f89521f80fa8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585347190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.2585347190
Directory	/workspace/46.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/46.sram_ctrl_alert_test.925546835
Short name	T440
Test name
Test status
Simulation time	17046532 ps
CPU time	0.65 seconds
Started	Apr 18 02:44:44 PM PDT 24
Finished	Apr 18 02:44:45 PM PDT 24
Peak memory	202804 kb
Host	smart-e43a957a-a86f-4fb0-a556-8432a816f6eb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925546835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.925546835
Directory	/workspace/46.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.sram_ctrl_bijection.3670939797
Short name	T336
Test name
Test status
Simulation time	165291921809 ps
CPU time	2585.15 seconds
Started	Apr 18 02:44:19 PM PDT 24
Finished	Apr 18 03:27:24 PM PDT 24
Peak memory	203468 kb
Host	smart-343bacd4-7c3d-41cb-beef-fa0c97cb61e9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670939797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .3670939797
Directory	/workspace/46.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/46.sram_ctrl_executable.3487717557
Short name	T855
Test name
Test status
Simulation time	44227872362 ps
CPU time	102.59 seconds
Started	Apr 18 02:44:28 PM PDT 24
Finished	Apr 18 02:46:11 PM PDT 24
Peak memory	300164 kb
Host	smart-619ac252-b5dd-47dc-b249-3020c8fce9f3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487717557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.3487717557
Directory	/workspace/46.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/46.sram_ctrl_lc_escalation.1529672827
Short name	T418
Test name
Test status
Simulation time	17977345788 ps
CPU time	61.37 seconds
Started	Apr 18 02:44:25 PM PDT 24
Finished	Apr 18 02:45:26 PM PDT 24
Peak memory	203108 kb
Host	smart-11fb00a7-f849-4051-b1d4-504defa1bf03
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529672827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.1529672827
Directory	/workspace/46.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/46.sram_ctrl_max_throughput.3352536290
Short name	T716
Test name
Test status
Simulation time	2803566430 ps
CPU time	7.59 seconds
Started	Apr 18 02:44:25 PM PDT 24
Finished	Apr 18 02:44:32 PM PDT 24
Peak memory	219132 kb
Host	smart-5fbdc879-3fc5-4a76-8a06-9320ab7c6dd3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352536290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.3352536290
Directory	/workspace/46.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1098059113
Short name	T430
Test name
Test status
Simulation time	18183419342 ps
CPU time	146.57 seconds
Started	Apr 18 02:44:38 PM PDT 24
Finished	Apr 18 02:47:05 PM PDT 24
Peak memory	211328 kb
Host	smart-d2652942-23f5-4d8f-a8e9-dd593fd1ded5
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098059113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.1098059113
Directory	/workspace/46.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_walk.4121243713
Short name	T824
Test name
Test status
Simulation time	16410273045 ps
CPU time	245.97 seconds
Started	Apr 18 02:44:35 PM PDT 24
Finished	Apr 18 02:48:41 PM PDT 24
Peak memory	203708 kb
Host	smart-bddcc00a-68c2-4eff-9bff-173a559f96cc
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121243713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.4121243713
Directory	/workspace/46.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/46.sram_ctrl_multiple_keys.1697695999
Short name	T684
Test name
Test status
Simulation time	46165146761 ps
CPU time	684.54 seconds
Started	Apr 18 02:44:17 PM PDT 24
Finished	Apr 18 02:55:43 PM PDT 24
Peak memory	377992 kb
Host	smart-72463a21-6358-4d8c-adb8-cf66a5985ca0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697695999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.1697695999
Directory	/workspace/46.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access.382405537
Short name	T822
Test name
Test status
Simulation time	2459020877 ps
CPU time	24.93 seconds
Started	Apr 18 02:44:19 PM PDT 24
Finished	Apr 18 02:44:45 PM PDT 24
Peak memory	267416 kb
Host	smart-8633b76d-c209-499c-beb4-683f1ede6a88
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382405537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s ram_ctrl_partial_access.382405537
Directory	/workspace/46.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.349705893
Short name	T198
Test name
Test status
Simulation time	202932676384 ps
CPU time	487.98 seconds
Started	Apr 18 02:44:17 PM PDT 24
Finished	Apr 18 02:52:26 PM PDT 24
Peak memory	203172 kb
Host	smart-30895ac1-cf65-4e20-af3e-516230309712
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349705893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.sram_ctrl_partial_access_b2b.349705893
Directory	/workspace/46.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/46.sram_ctrl_ram_cfg.225935296
Short name	T936
Test name
Test status
Simulation time	363766032 ps
CPU time	3.07 seconds
Started	Apr 18 02:44:34 PM PDT 24
Finished	Apr 18 02:44:37 PM PDT 24
Peak memory	203048 kb
Host	smart-27a0b7db-6d9f-4e7e-ab8a-61888c9a49c5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225935296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.225935296
Directory	/workspace/46.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/46.sram_ctrl_regwen.731541808
Short name	T292
Test name
Test status
Simulation time	12297596654 ps
CPU time	1242.65 seconds
Started	Apr 18 02:44:37 PM PDT 24
Finished	Apr 18 03:05:20 PM PDT 24
Peak memory	377960 kb
Host	smart-3879c11f-4848-44f5-9aee-77c21cf8474b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731541808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.731541808
Directory	/workspace/46.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/46.sram_ctrl_smoke.2999882539
Short name	T261
Test name
Test status
Simulation time	9747638771 ps
CPU time	18.45 seconds
Started	Apr 18 02:44:19 PM PDT 24
Finished	Apr 18 02:44:37 PM PDT 24
Peak memory	203080 kb
Host	smart-8157c8d1-2c94-4761-8929-fbc313914f26
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999882539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2999882539
Directory	/workspace/46.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_all.627219169
Short name	T467
Test name
Test status
Simulation time	78792568999 ps
CPU time	5411.39 seconds
Started	Apr 18 02:44:38 PM PDT 24
Finished	Apr 18 04:14:51 PM PDT 24
Peak memory	381120 kb
Host	smart-a1875eb1-a872-4bf7-931a-380ca2d7fd81
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627219169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_stress_all.627219169
Directory	/workspace/46.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3930709777
Short name	T466
Test name
Test status
Simulation time	1640822584 ps
CPU time	41.98 seconds
Started	Apr 18 02:44:39 PM PDT 24
Finished	Apr 18 02:45:22 PM PDT 24
Peak memory	211300 kb
Host	smart-981e6b37-713f-47cb-afeb-afee0368e249
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3930709777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3930709777
Directory	/workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2030607219
Short name	T97
Test name
Test status
Simulation time	4156769899 ps
CPU time	79.01 seconds
Started	Apr 18 02:44:18 PM PDT 24
Finished	Apr 18 02:45:37 PM PDT 24
Peak memory	203152 kb
Host	smart-5eca9d6e-fe01-4159-a594-7a5cca4bd8f0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030607219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.2030607219
Directory	/workspace/46.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3765650601
Short name	T358
Test name
Test status
Simulation time	840887859 ps
CPU time	144.79 seconds
Started	Apr 18 02:44:23 PM PDT 24
Finished	Apr 18 02:46:48 PM PDT 24
Peak memory	370632 kb
Host	smart-b70b4bf0-bb80-4468-a967-16412cbf6fdb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765650601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3765650601
Directory	/workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1293614011
Short name	T789
Test name
Test status
Simulation time	61807829227 ps
CPU time	1745.22 seconds
Started	Apr 18 02:44:52 PM PDT 24
Finished	Apr 18 03:13:58 PM PDT 24
Peak memory	378940 kb
Host	smart-85357002-ad97-49a8-8fe5-2556db6ae5c7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293614011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.1293614011
Directory	/workspace/47.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/47.sram_ctrl_alert_test.1538608758
Short name	T796
Test name
Test status
Simulation time	18694336 ps
CPU time	0.64 seconds
Started	Apr 18 02:45:09 PM PDT 24
Finished	Apr 18 02:45:10 PM PDT 24
Peak memory	203044 kb
Host	smart-7bc685c7-2e3a-4240-b0af-c3c80e36b23e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538608758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1538608758
Directory	/workspace/47.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.sram_ctrl_bijection.410033396
Short name	T531
Test name
Test status
Simulation time	171285011408 ps
CPU time	1501.79 seconds
Started	Apr 18 02:44:48 PM PDT 24
Finished	Apr 18 03:09:51 PM PDT 24
Peak memory	203540 kb
Host	smart-f0e4aefd-599f-49a6-bb2d-852bd0704c10
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410033396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection. 410033396
Directory	/workspace/47.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/47.sram_ctrl_executable.1745727106
Short name	T168
Test name
Test status
Simulation time	6616433673 ps
CPU time	737.93 seconds
Started	Apr 18 02:44:59 PM PDT 24
Finished	Apr 18 02:57:17 PM PDT 24
Peak memory	379988 kb
Host	smart-738340df-0aea-4311-a78e-0fdfc78493aa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745727106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.1745727106
Directory	/workspace/47.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/47.sram_ctrl_lc_escalation.2236253623
Short name	T444
Test name
Test status
Simulation time	24089634110 ps
CPU time	39.18 seconds
Started	Apr 18 02:44:54 PM PDT 24
Finished	Apr 18 02:45:34 PM PDT 24
Peak memory	203092 kb
Host	smart-21ce8168-6019-4ab6-aad9-5211d9839412
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236253623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.2236253623
Directory	/workspace/47.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/47.sram_ctrl_max_throughput.3560362379
Short name	T651
Test name
Test status
Simulation time	1323588851 ps
CPU time	64.79 seconds
Started	Apr 18 02:44:48 PM PDT 24
Finished	Apr 18 02:45:53 PM PDT 24
Peak memory	316360 kb
Host	smart-57c924bf-2b95-4471-8f84-505f8fc71ab1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560362379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.3560362379
Directory	/workspace/47.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2860571195
Short name	T439
Test name
Test status
Simulation time	17380727005 ps
CPU time	153.27 seconds
Started	Apr 18 02:45:05 PM PDT 24
Finished	Apr 18 02:47:39 PM PDT 24
Peak memory	211388 kb
Host	smart-48536b93-1fdb-4c37-a6da-c4fb20d1e17e
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860571195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.2860571195
Directory	/workspace/47.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_walk.2854363352
Short name	T562
Test name
Test status
Simulation time	4479651724 ps
CPU time	242.11 seconds
Started	Apr 18 02:44:59 PM PDT 24
Finished	Apr 18 02:49:01 PM PDT 24
Peak memory	203376 kb
Host	smart-ecb50cce-5a9f-4380-9124-c34874e5ada3
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854363352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.2854363352
Directory	/workspace/47.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/47.sram_ctrl_multiple_keys.4191451349
Short name	T654
Test name
Test status
Simulation time	8554102484 ps
CPU time	1757.28 seconds
Started	Apr 18 02:44:44 PM PDT 24
Finished	Apr 18 03:14:02 PM PDT 24
Peak memory	373856 kb
Host	smart-a05e0887-0df6-41cd-bd5b-bd784117c0d3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191451349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.4191451349
Directory	/workspace/47.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access.834079546
Short name	T4
Test name
Test status
Simulation time	3065815469 ps
CPU time	13.15 seconds
Started	Apr 18 02:44:48 PM PDT 24
Finished	Apr 18 02:45:02 PM PDT 24
Peak memory	203080 kb
Host	smart-7a7018d5-923e-48cd-83ca-04a77a44308e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834079546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.s ram_ctrl_partial_access.834079546
Directory	/workspace/47.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4290973733
Short name	T318
Test name
Test status
Simulation time	114873508735 ps
CPU time	319.15 seconds
Started	Apr 18 02:44:50 PM PDT 24
Finished	Apr 18 02:50:09 PM PDT 24
Peak memory	203212 kb
Host	smart-80edd62d-da0d-47a4-a1ad-9091747f4dbf
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290973733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.4290973733
Directory	/workspace/47.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/47.sram_ctrl_ram_cfg.3680614363
Short name	T38
Test name
Test status
Simulation time	352753535 ps
CPU time	3.24 seconds
Started	Apr 18 02:45:00 PM PDT 24
Finished	Apr 18 02:45:03 PM PDT 24
Peak memory	203048 kb
Host	smart-907c5640-d4bf-4a92-8610-f601b581ee40
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680614363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3680614363
Directory	/workspace/47.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/47.sram_ctrl_regwen.3089019442
Short name	T31
Test name
Test status
Simulation time	25724066412 ps
CPU time	583.24 seconds
Started	Apr 18 02:45:01 PM PDT 24
Finished	Apr 18 02:54:44 PM PDT 24
Peak memory	366592 kb
Host	smart-2dccf161-8aa3-4d71-b094-8e5ccc377c71
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089019442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3089019442
Directory	/workspace/47.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/47.sram_ctrl_smoke.2359886323
Short name	T649
Test name
Test status
Simulation time	2311090526 ps
CPU time	21.66 seconds
Started	Apr 18 02:44:44 PM PDT 24
Finished	Apr 18 02:45:06 PM PDT 24
Peak memory	272176 kb
Host	smart-2bf28aff-3112-4871-ae53-26406ddfec1f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359886323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2359886323
Directory	/workspace/47.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all.2004543591
Short name	T614
Test name
Test status
Simulation time	50118195438 ps
CPU time	1592.15 seconds
Started	Apr 18 02:45:09 PM PDT 24
Finished	Apr 18 03:11:42 PM PDT 24
Peak memory	397928 kb
Host	smart-c0b51511-41b2-4868-9ed6-711c6089af1b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004543591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.2004543591
Directory	/workspace/47.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.263191137
Short name	T48
Test name
Test status
Simulation time	869460203 ps
CPU time	23.7 seconds
Started	Apr 18 02:45:05 PM PDT 24
Finished	Apr 18 02:45:29 PM PDT 24
Peak memory	212840 kb
Host	smart-7d16bb27-1e1c-44b2-9c95-7e47dffa70a6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=263191137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.263191137
Directory	/workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3969307850
Short name	T734
Test name
Test status
Simulation time	17286323732 ps
CPU time	292.69 seconds
Started	Apr 18 02:44:51 PM PDT 24
Finished	Apr 18 02:49:44 PM PDT 24
Peak memory	203212 kb
Host	smart-3c9b3d9a-bc34-4a9c-8eea-523a9d608ba5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969307850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.3969307850
Directory	/workspace/47.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4035268397
Short name	T400
Test name
Test status
Simulation time	971819812 ps
CPU time	9.79 seconds
Started	Apr 18 02:44:53 PM PDT 24
Finished	Apr 18 02:45:03 PM PDT 24
Peak memory	235528 kb
Host	smart-cf1a7968-7a29-451a-b673-13a8a3362694
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035268397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.4035268397
Directory	/workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1456316785
Short name	T262
Test name
Test status
Simulation time	97847272001 ps
CPU time	822.42 seconds
Started	Apr 18 02:45:25 PM PDT 24
Finished	Apr 18 02:59:08 PM PDT 24
Peak memory	363680 kb
Host	smart-e8d65706-a91c-458e-82ad-fb68e2d8b9c6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456316785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.1456316785
Directory	/workspace/48.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/48.sram_ctrl_alert_test.2139206307
Short name	T248
Test name
Test status
Simulation time	17982939 ps
CPU time	0.64 seconds
Started	Apr 18 02:45:38 PM PDT 24
Finished	Apr 18 02:45:39 PM PDT 24
Peak memory	202632 kb
Host	smart-e80c00ea-1a8b-474d-bfb2-68bde0decd4f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139206307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.2139206307
Directory	/workspace/48.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.sram_ctrl_bijection.3126393948
Short name	T283
Test name
Test status
Simulation time	172629603269 ps
CPU time	1322.19 seconds
Started	Apr 18 02:45:18 PM PDT 24
Finished	Apr 18 03:07:21 PM PDT 24
Peak memory	203536 kb
Host	smart-8e0cb495-d1c2-43e2-8abe-05a438e05926
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126393948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .3126393948
Directory	/workspace/48.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/48.sram_ctrl_executable.2808203061
Short name	T601
Test name
Test status
Simulation time	12347864246 ps
CPU time	117.49 seconds
Started	Apr 18 02:45:29 PM PDT 24
Finished	Apr 18 02:47:27 PM PDT 24
Peak memory	298016 kb
Host	smart-85d58f8c-b415-479c-9e12-617d0cc5af79
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808203061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.2808203061
Directory	/workspace/48.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/48.sram_ctrl_max_throughput.2252278509
Short name	T575
Test name
Test status
Simulation time	697909839 ps
CPU time	9.44 seconds
Started	Apr 18 02:45:19 PM PDT 24
Finished	Apr 18 02:45:28 PM PDT 24
Peak memory	223944 kb
Host	smart-121c643f-3fd8-44f2-af69-ef8edfe74efc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252278509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.2252278509
Directory	/workspace/48.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.214954023
Short name	T745
Test name
Test status
Simulation time	2658689270 ps
CPU time	71.56 seconds
Started	Apr 18 02:45:40 PM PDT 24
Finished	Apr 18 02:46:52 PM PDT 24
Peak memory	211324 kb
Host	smart-5d123e10-c8ee-4301-8140-32ce1ee6206c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214954023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sram_ctrl_mem_partial_access.214954023
Directory	/workspace/48.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_walk.2715308308
Short name	T598
Test name
Test status
Simulation time	55056692421 ps
CPU time	282.11 seconds
Started	Apr 18 02:45:34 PM PDT 24
Finished	Apr 18 02:50:17 PM PDT 24
Peak memory	203720 kb
Host	smart-d1b3f473-c1df-4e0b-ae33-410371b7f435
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715308308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.2715308308
Directory	/workspace/48.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/48.sram_ctrl_multiple_keys.4849189
Short name	T55
Test name
Test status
Simulation time	36122481421 ps
CPU time	1278.52 seconds
Started	Apr 18 02:45:16 PM PDT 24
Finished	Apr 18 03:06:35 PM PDT 24
Peak memory	382028 kb
Host	smart-b63c4c3e-445b-4ee2-b0d7-690ce4d81948
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4849189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multipl e_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple _keys.4849189
Directory	/workspace/48.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access.1866239055
Short name	T911
Test name
Test status
Simulation time	3702480061 ps
CPU time	133.26 seconds
Started	Apr 18 02:45:20 PM PDT 24
Finished	Apr 18 02:47:33 PM PDT 24
Peak memory	368684 kb
Host	smart-c0b73258-d125-4638-9913-ef03fb8a0c2a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866239055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.1866239055
Directory	/workspace/48.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4224567950
Short name	T775
Test name
Test status
Simulation time	63612810756 ps
CPU time	387.54 seconds
Started	Apr 18 02:45:21 PM PDT 24
Finished	Apr 18 02:51:49 PM PDT 24
Peak memory	203148 kb
Host	smart-f5d9b52f-d8eb-484f-ba1f-f5909cba0db5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224567950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.4224567950
Directory	/workspace/48.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/48.sram_ctrl_ram_cfg.3387681593
Short name	T303
Test name
Test status
Simulation time	2815895916 ps
CPU time	3.94 seconds
Started	Apr 18 02:45:32 PM PDT 24
Finished	Apr 18 02:45:37 PM PDT 24
Peak memory	203112 kb
Host	smart-7d3efbd9-1eec-4a74-a561-4780a9cdb6c4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387681593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3387681593
Directory	/workspace/48.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/48.sram_ctrl_regwen.1661996122
Short name	T401
Test name
Test status
Simulation time	46531845391 ps
CPU time	1106.45 seconds
Started	Apr 18 02:45:30 PM PDT 24
Finished	Apr 18 03:03:57 PM PDT 24
Peak memory	380024 kb
Host	smart-f4d386a1-a279-42db-8379-23ce7bddabb0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661996122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1661996122
Directory	/workspace/48.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/48.sram_ctrl_smoke.2709515098
Short name	T184
Test name
Test status
Simulation time	1278516558 ps
CPU time	8.42 seconds
Started	Apr 18 02:45:14 PM PDT 24
Finished	Apr 18 02:45:23 PM PDT 24
Peak memory	203008 kb
Host	smart-3753669d-dfa5-4144-abda-a3a2a2f41a8e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709515098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2709515098
Directory	/workspace/48.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all.3862662455
Short name	T250
Test name
Test status
Simulation time	87497035957 ps
CPU time	2623.38 seconds
Started	Apr 18 02:45:44 PM PDT 24
Finished	Apr 18 03:29:27 PM PDT 24
Peak memory	381104 kb
Host	smart-558d6e05-013e-4299-99c2-758e39f24e6c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862662455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.3862662455
Directory	/workspace/48.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2658761899
Short name	T366
Test name
Test status
Simulation time	541515415 ps
CPU time	12.08 seconds
Started	Apr 18 02:45:40 PM PDT 24
Finished	Apr 18 02:45:52 PM PDT 24
Peak memory	212656 kb
Host	smart-094394fc-f1c0-4301-b7ef-bbac8bf520dc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2658761899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2658761899
Directory	/workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_pipeline.294228409
Short name	T569
Test name
Test status
Simulation time	4536574723 ps
CPU time	254.93 seconds
Started	Apr 18 02:45:18 PM PDT 24
Finished	Apr 18 02:49:34 PM PDT 24
Peak memory	203128 kb
Host	smart-ba01572a-50b1-41a7-84fb-fa36a904648d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294228409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sram_ctrl_stress_pipeline.294228409
Directory	/workspace/48.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1893987972
Short name	T820
Test name
Test status
Simulation time	1421892422 ps
CPU time	11.88 seconds
Started	Apr 18 02:45:18 PM PDT 24
Finished	Apr 18 02:45:30 PM PDT 24
Peak memory	237024 kb
Host	smart-f03bab07-dc96-4c2e-90c0-e4bdea0fa32e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893987972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1893987972
Directory	/workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1818523892
Short name	T18
Test name
Test status
Simulation time	22532268559 ps
CPU time	938.72 seconds
Started	Apr 18 02:45:44 PM PDT 24
Finished	Apr 18 03:01:23 PM PDT 24
Peak memory	375224 kb
Host	smart-d93edd8e-0679-42c4-bdba-2fc0d0ba0025
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818523892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.1818523892
Directory	/workspace/49.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/49.sram_ctrl_alert_test.2630493123
Short name	T573
Test name
Test status
Simulation time	20364335 ps
CPU time	0.64 seconds
Started	Apr 18 02:46:04 PM PDT 24
Finished	Apr 18 02:46:05 PM PDT 24
Peak memory	202780 kb
Host	smart-4dc3d693-5e87-479c-8071-f925353a1bc5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630493123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2630493123
Directory	/workspace/49.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.sram_ctrl_bijection.1722845436
Short name	T273
Test name
Test status
Simulation time	137939461211 ps
CPU time	2278.37 seconds
Started	Apr 18 02:45:39 PM PDT 24
Finished	Apr 18 03:23:37 PM PDT 24
Peak memory	203460 kb
Host	smart-8844a1de-d361-4e5e-9a58-30e692ef8c17
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722845436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .1722845436
Directory	/workspace/49.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/49.sram_ctrl_executable.229935543
Short name	T673
Test name
Test status
Simulation time	4682060710 ps
CPU time	192.67 seconds
Started	Apr 18 02:45:43 PM PDT 24
Finished	Apr 18 02:48:56 PM PDT 24
Peak memory	362864 kb
Host	smart-81dbc50d-b2cc-489e-b709-36ec56959565
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229935543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executabl e.229935543
Directory	/workspace/49.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/49.sram_ctrl_lc_escalation.4144352088
Short name	T608
Test name
Test status
Simulation time	10003300781 ps
CPU time	62.5 seconds
Started	Apr 18 02:45:44 PM PDT 24
Finished	Apr 18 02:46:47 PM PDT 24
Peak memory	202980 kb
Host	smart-05293831-2509-416e-9223-add111a5a3b2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144352088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.4144352088
Directory	/workspace/49.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/49.sram_ctrl_max_throughput.152234972
Short name	T282
Test name
Test status
Simulation time	793719103 ps
CPU time	77.73 seconds
Started	Apr 18 02:45:42 PM PDT 24
Finished	Apr 18 02:47:00 PM PDT 24
Peak memory	345448 kb
Host	smart-44fe1f2f-0072-438a-95ed-b3b2a6cd8241
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152234972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.sram_ctrl_max_throughput.152234972
Directory	/workspace/49.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.4055845493
Short name	T384
Test name
Test status
Simulation time	22812377208 ps
CPU time	152.68 seconds
Started	Apr 18 02:45:54 PM PDT 24
Finished	Apr 18 02:48:27 PM PDT 24
Peak memory	211336 kb
Host	smart-1410414e-fd8b-4d76-aea0-ada8ddfb0b6c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055845493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.4055845493
Directory	/workspace/49.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_walk.1353052682
Short name	T201
Test name
Test status
Simulation time	34426546499 ps
CPU time	172.32 seconds
Started	Apr 18 02:45:51 PM PDT 24
Finished	Apr 18 02:48:43 PM PDT 24
Peak memory	204016 kb
Host	smart-71952be4-0dae-4672-8808-601e51fe506a
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353052682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.1353052682
Directory	/workspace/49.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/49.sram_ctrl_multiple_keys.2665676811
Short name	T370
Test name
Test status
Simulation time	17214382452 ps
CPU time	773.58 seconds
Started	Apr 18 02:45:38 PM PDT 24
Finished	Apr 18 02:58:32 PM PDT 24
Peak memory	377980 kb
Host	smart-a0dda5ea-f1d1-4296-8aa9-22321ac889e9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665676811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.2665676811
Directory	/workspace/49.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access.1637916264
Short name	T890
Test name
Test status
Simulation time	3514735093 ps
CPU time	16.09 seconds
Started	Apr 18 02:45:39 PM PDT 24
Finished	Apr 18 02:45:55 PM PDT 24
Peak memory	203064 kb
Host	smart-7ca1113d-d297-4433-b53c-babe3e7fb071
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637916264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.1637916264
Directory	/workspace/49.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3698090389
Short name	T530
Test name
Test status
Simulation time	34424059942 ps
CPU time	479.97 seconds
Started	Apr 18 02:45:38 PM PDT 24
Finished	Apr 18 02:53:39 PM PDT 24
Peak memory	203208 kb
Host	smart-f4f2d84f-d8fd-4b37-bce5-a4d07a3e09b3
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698090389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.3698090389
Directory	/workspace/49.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/49.sram_ctrl_ram_cfg.2613687958
Short name	T772
Test name
Test status
Simulation time	1253390818 ps
CPU time	3.37 seconds
Started	Apr 18 02:45:48 PM PDT 24
Finished	Apr 18 02:45:52 PM PDT 24
Peak memory	203048 kb
Host	smart-0e236662-a3ef-4349-b6a4-9e90800a47ed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613687958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.2613687958
Directory	/workspace/49.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/49.sram_ctrl_regwen.425063291
Short name	T319
Test name
Test status
Simulation time	6450129188 ps
CPU time	459.67 seconds
Started	Apr 18 02:45:43 PM PDT 24
Finished	Apr 18 02:53:23 PM PDT 24
Peak memory	374920 kb
Host	smart-941594fb-2e3a-4f4f-a1b4-5b9f914bf36e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425063291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.425063291
Directory	/workspace/49.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/49.sram_ctrl_smoke.1761001018
Short name	T727
Test name
Test status
Simulation time	1866083633 ps
CPU time	16.34 seconds
Started	Apr 18 02:45:42 PM PDT 24
Finished	Apr 18 02:45:59 PM PDT 24
Peak memory	202932 kb
Host	smart-3860791d-6094-40b2-a3b9-cd6dad0e7504
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761001018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1761001018
Directory	/workspace/49.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1918151688
Short name	T889
Test name
Test status
Simulation time	3174409849 ps
CPU time	21.76 seconds
Started	Apr 18 02:45:57 PM PDT 24
Finished	Apr 18 02:46:19 PM PDT 24
Peak memory	211544 kb
Host	smart-56a2b6c0-c32d-49a2-abeb-498d512708c4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1918151688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1918151688
Directory	/workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.469386759
Short name	T215
Test name
Test status
Simulation time	14514657355 ps
CPU time	265.32 seconds
Started	Apr 18 02:45:38 PM PDT 24
Finished	Apr 18 02:50:03 PM PDT 24
Peak memory	203176 kb
Host	smart-39771848-fbb5-4b32-9c48-46ea0ed63570
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469386759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sram_ctrl_stress_pipeline.469386759
Directory	/workspace/49.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2468998217
Short name	T544
Test name
Test status
Simulation time	2411357275 ps
CPU time	6.87 seconds
Started	Apr 18 02:45:40 PM PDT 24
Finished	Apr 18 02:45:47 PM PDT 24
Peak memory	214364 kb
Host	smart-39a9cd8a-5b88-4b2d-a94b-d55046b6ae96
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468998217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2468998217
Directory	/workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1758965388
Short name	T650
Test name
Test status
Simulation time	26882441826 ps
CPU time	156.27 seconds
Started	Apr 18 02:31:07 PM PDT 24
Finished	Apr 18 02:33:43 PM PDT 24
Peak memory	340424 kb
Host	smart-4efd0ab6-c818-4a36-9956-aa922af9046e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758965388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.1758965388
Directory	/workspace/5.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/5.sram_ctrl_alert_test.488382292
Short name	T296
Test name
Test status
Simulation time	121204920 ps
CPU time	0.65 seconds
Started	Apr 18 02:31:06 PM PDT 24
Finished	Apr 18 02:31:07 PM PDT 24
Peak memory	202816 kb
Host	smart-ee5098ef-286e-494c-958d-a747c920ea55
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488382292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.488382292
Directory	/workspace/5.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.sram_ctrl_bijection.2519689748
Short name	T267
Test name
Test status
Simulation time	34757332342 ps
CPU time	1201.19 seconds
Started	Apr 18 02:30:57 PM PDT 24
Finished	Apr 18 02:50:58 PM PDT 24
Peak memory	203592 kb
Host	smart-bef0250c-7696-4488-a363-6a702fce65d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519689748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 2519689748
Directory	/workspace/5.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/5.sram_ctrl_executable.4169102153
Short name	T642
Test name
Test status
Simulation time	23884517319 ps
CPU time	1410.75 seconds
Started	Apr 18 02:31:06 PM PDT 24
Finished	Apr 18 02:54:37 PM PDT 24
Peak memory	380000 kb
Host	smart-474589be-14d7-45f0-869f-a42010c77df9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169102153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.4169102153
Directory	/workspace/5.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/5.sram_ctrl_lc_escalation.4047950598
Short name	T295
Test name
Test status
Simulation time	12534094175 ps
CPU time	76.72 seconds
Started	Apr 18 02:30:58 PM PDT 24
Finished	Apr 18 02:32:15 PM PDT 24
Peak memory	203172 kb
Host	smart-3c9b3e49-d97a-467c-9e0e-7cd8b51c0fa0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047950598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.4047950598
Directory	/workspace/5.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/5.sram_ctrl_max_throughput.1350601254
Short name	T269
Test name
Test status
Simulation time	1888122425 ps
CPU time	69.18 seconds
Started	Apr 18 02:30:58 PM PDT 24
Finished	Apr 18 02:32:07 PM PDT 24
Peak memory	313324 kb
Host	smart-416c05b2-5c6f-4a6f-8763-cd3edc29049e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350601254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.1350601254
Directory	/workspace/5.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_walk.2121254633
Short name	T672
Test name
Test status
Simulation time	7116926404 ps
CPU time	142.3 seconds
Started	Apr 18 02:31:07 PM PDT 24
Finished	Apr 18 02:33:30 PM PDT 24
Peak memory	203544 kb
Host	smart-61f9979c-baf0-4d78-b4d1-329ff71a9273
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121254633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.2121254633
Directory	/workspace/5.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/5.sram_ctrl_multiple_keys.2017445455
Short name	T289
Test name
Test status
Simulation time	2769989909 ps
CPU time	329.48 seconds
Started	Apr 18 02:31:06 PM PDT 24
Finished	Apr 18 02:36:36 PM PDT 24
Peak memory	367644 kb
Host	smart-92685863-6788-4832-9a23-6b18ac6089d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017445455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.2017445455
Directory	/workspace/5.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access.1287605031
Short name	T297
Test name
Test status
Simulation time	900199221 ps
CPU time	15.11 seconds
Started	Apr 18 02:30:58 PM PDT 24
Finished	Apr 18 02:31:14 PM PDT 24
Peak memory	245888 kb
Host	smart-aa32b251-82a2-496e-b7f8-92a2b9e7cf15
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287605031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.1287605031
Directory	/workspace/5.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3800601717
Short name	T127
Test name
Test status
Simulation time	24885956291 ps
CPU time	527.38 seconds
Started	Apr 18 02:30:57 PM PDT 24
Finished	Apr 18 02:39:45 PM PDT 24
Peak memory	203156 kb
Host	smart-6d2dc7a1-b16f-4f6e-872e-1962b8aebd3c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800601717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.3800601717
Directory	/workspace/5.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/5.sram_ctrl_ram_cfg.3010099474
Short name	T352
Test name
Test status
Simulation time	1463592542 ps
CPU time	3.61 seconds
Started	Apr 18 02:31:09 PM PDT 24
Finished	Apr 18 02:31:13 PM PDT 24
Peak memory	203052 kb
Host	smart-cff5fe91-f8a7-4a42-8796-2a75dba6f602
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010099474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3010099474
Directory	/workspace/5.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/5.sram_ctrl_regwen.2355780261
Short name	T862
Test name
Test status
Simulation time	9272603909 ps
CPU time	167.63 seconds
Started	Apr 18 02:31:09 PM PDT 24
Finished	Apr 18 02:33:57 PM PDT 24
Peak memory	290880 kb
Host	smart-c53e1c86-a0a8-4eb6-867c-ae39f4d35533
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355780261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2355780261
Directory	/workspace/5.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/5.sram_ctrl_smoke.1163845590
Short name	T874
Test name
Test status
Simulation time	2661239572 ps
CPU time	29.4 seconds
Started	Apr 18 02:30:58 PM PDT 24
Finished	Apr 18 02:31:28 PM PDT 24
Peak memory	281736 kb
Host	smart-b4a10b15-ee6c-4b21-9a69-79a1138ca2a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163845590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1163845590
Directory	/workspace/5.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all.1257846790
Short name	T108
Test name
Test status
Simulation time	324102475020 ps
CPU time	5659.75 seconds
Started	Apr 18 02:31:07 PM PDT 24
Finished	Apr 18 04:05:28 PM PDT 24
Peak memory	383100 kb
Host	smart-c2b1dda8-d660-4c34-8be9-551cca9d8319
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257846790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.1257846790
Directory	/workspace/5.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2080206435
Short name	T103
Test name
Test status
Simulation time	2454330809 ps
CPU time	113.94 seconds
Started	Apr 18 02:31:07 PM PDT 24
Finished	Apr 18 02:33:01 PM PDT 24
Peak memory	356464 kb
Host	smart-93674e2b-9fc8-4209-9fcb-1959e45b1acd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2080206435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2080206435
Directory	/workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2744910328
Short name	T914
Test name
Test status
Simulation time	55617881037 ps
CPU time	354.61 seconds
Started	Apr 18 02:30:57 PM PDT 24
Finished	Apr 18 02:36:53 PM PDT 24
Peak memory	203160 kb
Host	smart-19dc6146-4290-4a2d-b44b-92ca8a5a28f6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744910328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.2744910328
Directory	/workspace/5.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1519760412
Short name	T688
Test name
Test status
Simulation time	4357984753 ps
CPU time	113.97 seconds
Started	Apr 18 02:31:08 PM PDT 24
Finished	Apr 18 02:33:02 PM PDT 24
Peak memory	363648 kb
Host	smart-4981cb51-fba6-41f7-83bc-e2aa5b6a82ee
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519760412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1519760412
Directory	/workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1936685316
Short name	T921
Test name
Test status
Simulation time	27727507234 ps
CPU time	283.17 seconds
Started	Apr 18 02:31:10 PM PDT 24
Finished	Apr 18 02:35:54 PM PDT 24
Peak memory	334972 kb
Host	smart-73443076-90a0-44d7-9121-23617be11c8e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936685316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.1936685316
Directory	/workspace/6.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/6.sram_ctrl_alert_test.3350217116
Short name	T628
Test name
Test status
Simulation time	17212955 ps
CPU time	0.63 seconds
Started	Apr 18 02:31:08 PM PDT 24
Finished	Apr 18 02:31:09 PM PDT 24
Peak memory	202756 kb
Host	smart-c21726ff-5a38-46df-bb8f-ed2ebb8c8aca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350217116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3350217116
Directory	/workspace/6.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.sram_ctrl_bijection.271902972
Short name	T342
Test name
Test status
Simulation time	146699887161 ps
CPU time	1507.9 seconds
Started	Apr 18 02:31:07 PM PDT 24
Finished	Apr 18 02:56:16 PM PDT 24
Peak memory	203480 kb
Host	smart-d668e9e0-7889-46c1-852e-4313df3209cd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271902972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.271902972
Directory	/workspace/6.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/6.sram_ctrl_executable.120580982
Short name	T851
Test name
Test status
Simulation time	6956200279 ps
CPU time	76.61 seconds
Started	Apr 18 02:31:08 PM PDT 24
Finished	Apr 18 02:32:25 PM PDT 24
Peak memory	295024 kb
Host	smart-77dcfc01-8a11-4179-93fb-a8ae6d59e9d5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120580982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable .120580982
Directory	/workspace/6.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/6.sram_ctrl_lc_escalation.2041534095
Short name	T230
Test name
Test status
Simulation time	20613962342 ps
CPU time	33.7 seconds
Started	Apr 18 02:31:10 PM PDT 24
Finished	Apr 18 02:31:44 PM PDT 24
Peak memory	211256 kb
Host	smart-d84b83ae-70fe-425e-a4b1-bc0d74060817
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041534095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.2041534095
Directory	/workspace/6.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/6.sram_ctrl_max_throughput.2541419205
Short name	T357
Test name
Test status
Simulation time	3943118678 ps
CPU time	64 seconds
Started	Apr 18 02:31:10 PM PDT 24
Finished	Apr 18 02:32:14 PM PDT 24
Peak memory	348140 kb
Host	smart-fbd686c7-caac-4490-af87-0b922bb87bbc
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541419205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.2541419205
Directory	/workspace/6.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1060215444
Short name	T778
Test name
Test status
Simulation time	4331126955 ps
CPU time	62.24 seconds
Started	Apr 18 02:31:11 PM PDT 24
Finished	Apr 18 02:32:13 PM PDT 24
Peak memory	211360 kb
Host	smart-707d0da8-f2fc-4af8-85f0-f845712333ec
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060215444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.1060215444
Directory	/workspace/6.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_walk.3821591000
Short name	T281
Test name
Test status
Simulation time	20682686914 ps
CPU time	302.37 seconds
Started	Apr 18 02:31:09 PM PDT 24
Finished	Apr 18 02:36:12 PM PDT 24
Peak memory	203716 kb
Host	smart-e9b56447-1473-43ba-acae-4f98f374b658
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821591000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.3821591000
Directory	/workspace/6.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/6.sram_ctrl_multiple_keys.3167649991
Short name	T524
Test name
Test status
Simulation time	104835217958 ps
CPU time	1338.28 seconds
Started	Apr 18 02:31:06 PM PDT 24
Finished	Apr 18 02:53:25 PM PDT 24
Peak memory	379000 kb
Host	smart-c0ffc7a6-5dc2-44ea-8a37-3ed5b9b3dc95
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167649991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.3167649991
Directory	/workspace/6.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access.349711373
Short name	T729
Test name
Test status
Simulation time	4846180210 ps
CPU time	6.51 seconds
Started	Apr 18 02:31:07 PM PDT 24
Finished	Apr 18 02:31:14 PM PDT 24
Peak memory	203080 kb
Host	smart-644fa3b8-6527-4851-9c4d-efc42b0657db
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349711373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr am_ctrl_partial_access.349711373
Directory	/workspace/6.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3167851535
Short name	T94
Test name
Test status
Simulation time	35411857511 ps
CPU time	430.46 seconds
Started	Apr 18 02:31:08 PM PDT 24
Finished	Apr 18 02:38:19 PM PDT 24
Peak memory	203188 kb
Host	smart-50c48cf1-8ca9-4d8b-b4ca-4d73afb65791
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167851535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.3167851535
Directory	/workspace/6.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/6.sram_ctrl_ram_cfg.1304569347
Short name	T199
Test name
Test status
Simulation time	346752257 ps
CPU time	3.33 seconds
Started	Apr 18 02:31:10 PM PDT 24
Finished	Apr 18 02:31:14 PM PDT 24
Peak memory	203052 kb
Host	smart-081cf749-9727-4377-ae63-759cd5ffa11f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304569347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1304569347
Directory	/workspace/6.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/6.sram_ctrl_regwen.2976698993
Short name	T317
Test name
Test status
Simulation time	3392324014 ps
CPU time	814.92 seconds
Started	Apr 18 02:31:09 PM PDT 24
Finished	Apr 18 02:44:45 PM PDT 24
Peak memory	380968 kb
Host	smart-efff5678-1003-480b-b881-9f066693a809
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976698993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2976698993
Directory	/workspace/6.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/6.sram_ctrl_smoke.3099528573
Short name	T204
Test name
Test status
Simulation time	785384359 ps
CPU time	111.82 seconds
Started	Apr 18 02:31:06 PM PDT 24
Finished	Apr 18 02:32:58 PM PDT 24
Peak memory	367540 kb
Host	smart-5b70d636-0bfa-4c4d-9db9-011cd818dfda
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099528573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3099528573
Directory	/workspace/6.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_all.2081669002
Short name	T717
Test name
Test status
Simulation time	194399946495 ps
CPU time	8845.94 seconds
Started	Apr 18 02:31:10 PM PDT 24
Finished	Apr 18 04:58:37 PM PDT 24
Peak memory	382128 kb
Host	smart-86c1b562-244f-4b1c-899b-7f90aef210eb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081669002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.2081669002
Directory	/workspace/6.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2948713383
Short name	T123
Test name
Test status
Simulation time	5767423613 ps
CPU time	34.29 seconds
Started	Apr 18 02:31:10 PM PDT 24
Finished	Apr 18 02:31:44 PM PDT 24
Peak memory	219516 kb
Host	smart-c03a6a7e-9672-4ba4-9b20-1c07f21f9f24
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2948713383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2948713383
Directory	/workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.407513955
Short name	T206
Test name
Test status
Simulation time	3019050871 ps
CPU time	168.08 seconds
Started	Apr 18 02:31:06 PM PDT 24
Finished	Apr 18 02:33:55 PM PDT 24
Peak memory	203116 kb
Host	smart-37d58f50-445d-48e7-a569-b8c3cd2ea9c2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407513955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_stress_pipeline.407513955
Directory	/workspace/6.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3643052651
Short name	T432
Test name
Test status
Simulation time	809042193 ps
CPU time	57.95 seconds
Started	Apr 18 02:31:11 PM PDT 24
Finished	Apr 18 02:32:10 PM PDT 24
Peak memory	334108 kb
Host	smart-dc8e4768-3d33-47eb-a241-c03bf4f6f1f3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643052651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3643052651
Directory	/workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1737757427
Short name	T40
Test name
Test status
Simulation time	14604932419 ps
CPU time	66.42 seconds
Started	Apr 18 02:31:21 PM PDT 24
Finished	Apr 18 02:32:28 PM PDT 24
Peak memory	302308 kb
Host	smart-327c12bd-aec6-44c5-9c99-44ffb3388a88
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737757427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.1737757427
Directory	/workspace/7.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/7.sram_ctrl_alert_test.923455579
Short name	T732
Test name
Test status
Simulation time	48286898 ps
CPU time	0.66 seconds
Started	Apr 18 02:31:20 PM PDT 24
Finished	Apr 18 02:31:21 PM PDT 24
Peak memory	202788 kb
Host	smart-e85f4d61-aa80-4815-b349-5bda66be20c5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923455579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.923455579
Directory	/workspace/7.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.sram_ctrl_bijection.1696899627
Short name	T453
Test name
Test status
Simulation time	37397328780 ps
CPU time	1241.84 seconds
Started	Apr 18 02:31:15 PM PDT 24
Finished	Apr 18 02:51:57 PM PDT 24
Peak memory	203448 kb
Host	smart-0a98078b-cd6f-45b3-8660-7961eeea09af
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696899627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 1696899627
Directory	/workspace/7.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/7.sram_ctrl_executable.1240558210
Short name	T405
Test name
Test status
Simulation time	128775259389 ps
CPU time	1388.65 seconds
Started	Apr 18 02:31:21 PM PDT 24
Finished	Apr 18 02:54:30 PM PDT 24
Peak memory	372824 kb
Host	smart-63863941-20ef-4d64-9e66-4ffa4ca685ac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240558210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.1240558210
Directory	/workspace/7.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/7.sram_ctrl_lc_escalation.1543684033
Short name	T6
Test name
Test status
Simulation time	5288257258 ps
CPU time	34.91 seconds
Started	Apr 18 02:31:14 PM PDT 24
Finished	Apr 18 02:31:50 PM PDT 24
Peak memory	211372 kb
Host	smart-7095f662-71dd-4cea-83ea-02f62935c0db
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543684033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.1543684033
Directory	/workspace/7.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/7.sram_ctrl_max_throughput.84607897
Short name	T847
Test name
Test status
Simulation time	812106180 ps
CPU time	126.36 seconds
Started	Apr 18 02:31:22 PM PDT 24
Finished	Apr 18 02:33:29 PM PDT 24
Peak memory	369556 kb
Host	smart-3aaae363-b38d-401a-9987-6823894d3df2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84607897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_max_throughput.84607897
Directory	/workspace/7.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.786426118
Short name	T423
Test name
Test status
Simulation time	4698905256 ps
CPU time	80.83 seconds
Started	Apr 18 02:31:21 PM PDT 24
Finished	Apr 18 02:32:42 PM PDT 24
Peak memory	211308 kb
Host	smart-557a7ff6-9249-4ab0-9b5f-f74f4b86be0b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786426118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7. sram_ctrl_mem_partial_access.786426118
Directory	/workspace/7.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_walk.228303239
Short name	T347
Test name
Test status
Simulation time	28688381761 ps
CPU time	144.45 seconds
Started	Apr 18 02:31:21 PM PDT 24
Finished	Apr 18 02:33:46 PM PDT 24
Peak memory	203116 kb
Host	smart-c0b769bf-9a7f-4d4f-b1f2-a5f68a287ee9
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228303239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ mem_walk.228303239
Directory	/workspace/7.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/7.sram_ctrl_multiple_keys.3018074309
Short name	T420
Test name
Test status
Simulation time	25557866422 ps
CPU time	876.12 seconds
Started	Apr 18 02:31:16 PM PDT 24
Finished	Apr 18 02:45:53 PM PDT 24
Peak memory	378980 kb
Host	smart-c4a48cf5-748c-4184-9706-e12b5eb4b0f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018074309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.3018074309
Directory	/workspace/7.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access.3745422048
Short name	T333
Test name
Test status
Simulation time	2155742843 ps
CPU time	13.12 seconds
Started	Apr 18 02:31:15 PM PDT 24
Finished	Apr 18 02:31:28 PM PDT 24
Peak memory	203068 kb
Host	smart-9f03da78-ef1f-4b0e-ae34-4d90fa254454
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745422048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.3745422048
Directory	/workspace/7.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2039160587
Short name	T788
Test name
Test status
Simulation time	62671079729 ps
CPU time	355.87 seconds
Started	Apr 18 02:31:15 PM PDT 24
Finished	Apr 18 02:37:11 PM PDT 24
Peak memory	203196 kb
Host	smart-d5df0d4e-a27a-49ff-b070-41dd9aa9d043
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039160587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.2039160587
Directory	/workspace/7.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/7.sram_ctrl_ram_cfg.850655361
Short name	T190
Test name
Test status
Simulation time	1023107331 ps
CPU time	3.15 seconds
Started	Apr 18 02:31:20 PM PDT 24
Finished	Apr 18 02:31:24 PM PDT 24
Peak memory	203052 kb
Host	smart-5edda1f4-5bc9-4b57-bd61-72b73f8a0e46
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850655361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.850655361
Directory	/workspace/7.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/7.sram_ctrl_regwen.515913956
Short name	T522
Test name
Test status
Simulation time	17782861142 ps
CPU time	871.36 seconds
Started	Apr 18 02:31:19 PM PDT 24
Finished	Apr 18 02:45:51 PM PDT 24
Peak memory	381060 kb
Host	smart-702e7830-9e63-4768-a882-7d45e34cd958
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515913956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.515913956
Directory	/workspace/7.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/7.sram_ctrl_smoke.2904669497
Short name	T811
Test name
Test status
Simulation time	1517065939 ps
CPU time	27.23 seconds
Started	Apr 18 02:31:23 PM PDT 24
Finished	Apr 18 02:31:50 PM PDT 24
Peak memory	283684 kb
Host	smart-4bd0388e-186d-436f-9563-2ca0b459810f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904669497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2904669497
Directory	/workspace/7.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all.337136441
Short name	T170
Test name
Test status
Simulation time	65689664619 ps
CPU time	6117.76 seconds
Started	Apr 18 02:31:20 PM PDT 24
Finished	Apr 18 04:13:18 PM PDT 24
Peak memory	381088 kb
Host	smart-d26a20bf-ca40-44f7-9b3b-229490207ada
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337136441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_stress_all.337136441
Directory	/workspace/7.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2176468243
Short name	T771
Test name
Test status
Simulation time	224924937 ps
CPU time	11.41 seconds
Started	Apr 18 02:31:19 PM PDT 24
Finished	Apr 18 02:31:31 PM PDT 24
Peak memory	212944 kb
Host	smart-3c1cfa02-a636-4c5c-a3d5-df12107b0099
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2176468243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2176468243
Directory	/workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.770865329
Short name	T937
Test name
Test status
Simulation time	23758356473 ps
CPU time	257.83 seconds
Started	Apr 18 02:31:14 PM PDT 24
Finished	Apr 18 02:35:32 PM PDT 24
Peak memory	203388 kb
Host	smart-ec9db294-9eec-422e-afe3-508a97f16d0b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770865329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7. sram_ctrl_stress_pipeline.770865329
Directory	/workspace/7.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.697645449
Short name	T610
Test name
Test status
Simulation time	4940816607 ps
CPU time	13.48 seconds
Started	Apr 18 02:31:14 PM PDT 24
Finished	Apr 18 02:31:27 PM PDT 24
Peak memory	239580 kb
Host	smart-8e034d18-1067-4f56-b8c2-afc88f63d74b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697645449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_throughput_w_partial_write.697645449
Directory	/workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1810299184
Short name	T293
Test name
Test status
Simulation time	14001905605 ps
CPU time	1268.76 seconds
Started	Apr 18 02:31:26 PM PDT 24
Finished	Apr 18 02:52:35 PM PDT 24
Peak memory	379228 kb
Host	smart-030ce14c-e0bc-4b1a-a165-b4033beae92a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810299184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.1810299184
Directory	/workspace/8.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/8.sram_ctrl_alert_test.2425411395
Short name	T742
Test name
Test status
Simulation time	13427509 ps
CPU time	0.65 seconds
Started	Apr 18 02:31:32 PM PDT 24
Finished	Apr 18 02:31:33 PM PDT 24
Peak memory	202844 kb
Host	smart-2497cc4c-0a15-4125-8772-89aea366c488
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425411395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.2425411395
Directory	/workspace/8.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.sram_ctrl_bijection.641701354
Short name	T640
Test name
Test status
Simulation time	57087269786 ps
CPU time	732.06 seconds
Started	Apr 18 02:31:20 PM PDT 24
Finished	Apr 18 02:43:32 PM PDT 24
Peak memory	203356 kb
Host	smart-b3b020df-714d-4dc0-86af-e515d766e2bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641701354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.641701354
Directory	/workspace/8.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/8.sram_ctrl_executable.3861332816
Short name	T260
Test name
Test status
Simulation time	32282537802 ps
CPU time	736.26 seconds
Started	Apr 18 02:31:27 PM PDT 24
Finished	Apr 18 02:43:43 PM PDT 24
Peak memory	379084 kb
Host	smart-bc08ae12-8841-442b-82c9-b00f03f21330
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861332816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.3861332816
Directory	/workspace/8.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/8.sram_ctrl_lc_escalation.3014006514
Short name	T499
Test name
Test status
Simulation time	151368516898 ps
CPU time	108.72 seconds
Started	Apr 18 02:31:25 PM PDT 24
Finished	Apr 18 02:33:15 PM PDT 24
Peak memory	203044 kb
Host	smart-3a47813c-2014-4119-9442-68711afe923b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014006514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.3014006514
Directory	/workspace/8.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/8.sram_ctrl_max_throughput.2706656135
Short name	T549
Test name
Test status
Simulation time	2742613460 ps
CPU time	11.1 seconds
Started	Apr 18 02:31:27 PM PDT 24
Finished	Apr 18 02:31:38 PM PDT 24
Peak memory	235800 kb
Host	smart-8e2dc28b-701e-4370-b580-d904408f03e3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706656135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.2706656135
Directory	/workspace/8.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3743129124
Short name	T78
Test name
Test status
Simulation time	1931744486 ps
CPU time	64.8 seconds
Started	Apr 18 02:31:31 PM PDT 24
Finished	Apr 18 02:32:36 PM PDT 24
Peak memory	211224 kb
Host	smart-a9576732-55b4-4c81-b31f-5376090fa48c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743129124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.3743129124
Directory	/workspace/8.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_walk.1099903325
Short name	T235
Test name
Test status
Simulation time	12538857038 ps
CPU time	138.57 seconds
Started	Apr 18 02:31:30 PM PDT 24
Finished	Apr 18 02:33:49 PM PDT 24
Peak memory	203560 kb
Host	smart-d76081e2-741f-4953-bc7e-374ef99fb15e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099903325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.1099903325
Directory	/workspace/8.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/8.sram_ctrl_multiple_keys.2982498701
Short name	T767
Test name
Test status
Simulation time	20716178260 ps
CPU time	469.29 seconds
Started	Apr 18 02:31:21 PM PDT 24
Finished	Apr 18 02:39:11 PM PDT 24
Peak memory	378916 kb
Host	smart-52515267-1c73-4d3a-84fd-d5eb8c619afd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982498701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.2982498701
Directory	/workspace/8.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access.3534034111
Short name	T152
Test name
Test status
Simulation time	625780961 ps
CPU time	17.69 seconds
Started	Apr 18 02:31:25 PM PDT 24
Finished	Apr 18 02:31:43 PM PDT 24
Peak memory	203064 kb
Host	smart-72481d3f-bad2-437f-8f70-2e44c4bcf778
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534034111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.3534034111
Directory	/workspace/8.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3095554541
Short name	T265
Test name
Test status
Simulation time	10765662823 ps
CPU time	286.46 seconds
Started	Apr 18 02:31:25 PM PDT 24
Finished	Apr 18 02:36:12 PM PDT 24
Peak memory	203204 kb
Host	smart-4b91b3fa-aec4-4e1e-a98e-4532a0a8e2de
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095554541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.3095554541
Directory	/workspace/8.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/8.sram_ctrl_ram_cfg.2940164340
Short name	T428
Test name
Test status
Simulation time	353142197 ps
CPU time	3.17 seconds
Started	Apr 18 02:31:32 PM PDT 24
Finished	Apr 18 02:31:36 PM PDT 24
Peak memory	203052 kb
Host	smart-be522269-7baf-46bd-a2de-abfcf501c91d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940164340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2940164340
Directory	/workspace/8.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/8.sram_ctrl_regwen.3477311869
Short name	T494
Test name
Test status
Simulation time	28246518929 ps
CPU time	818.95 seconds
Started	Apr 18 02:31:29 PM PDT 24
Finished	Apr 18 02:45:08 PM PDT 24
Peak memory	380168 kb
Host	smart-94332d73-6dd2-48d5-8dc3-e094dd7edbd7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477311869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3477311869
Directory	/workspace/8.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/8.sram_ctrl_smoke.984783399
Short name	T758
Test name
Test status
Simulation time	1365773128 ps
CPU time	21.61 seconds
Started	Apr 18 02:31:21 PM PDT 24
Finished	Apr 18 02:31:43 PM PDT 24
Peak memory	202972 kb
Host	smart-23dba5ba-1be4-413e-b97a-0e14f8bfa337
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984783399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.984783399
Directory	/workspace/8.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all.1664097035
Short name	T411
Test name
Test status
Simulation time	204682123064 ps
CPU time	4783.68 seconds
Started	Apr 18 02:31:34 PM PDT 24
Finished	Apr 18 03:51:19 PM PDT 24
Peak memory	349132 kb
Host	smart-19aedd79-3930-4bbf-9dd4-2356206b76cc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664097035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.1664097035
Directory	/workspace/8.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3655189954
Short name	T305
Test name
Test status
Simulation time	8966460091 ps
CPU time	55.39 seconds
Started	Apr 18 02:31:30 PM PDT 24
Finished	Apr 18 02:32:26 PM PDT 24
Peak memory	211388 kb
Host	smart-4835ddab-6eab-4f1a-9acf-bb13d895636b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3655189954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3655189954
Directory	/workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_pipeline.4152783908
Short name	T156
Test name
Test status
Simulation time	5335836112 ps
CPU time	317.99 seconds
Started	Apr 18 02:31:20 PM PDT 24
Finished	Apr 18 02:36:38 PM PDT 24
Peak memory	203176 kb
Host	smart-4fdd6740-c868-49fc-9fd0-f88096ce1321
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152783908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.4152783908
Directory	/workspace/8.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2491379362
Short name	T620
Test name
Test status
Simulation time	1885485414 ps
CPU time	82.72 seconds
Started	Apr 18 02:31:24 PM PDT 24
Finished	Apr 18 02:32:47 PM PDT 24
Peak memory	354292 kb
Host	smart-5217b122-9060-44a5-8c38-5797c0aacec3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491379362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2491379362
Directory	/workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.30667852
Short name	T389
Test name
Test status
Simulation time	12454408553 ps
CPU time	401.98 seconds
Started	Apr 18 02:31:36 PM PDT 24
Finished	Apr 18 02:38:18 PM PDT 24
Peak memory	366156 kb
Host	smart-9ef037a6-ef41-4bbd-9568-00c622b6aba6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30667852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.sram_ctrl_access_during_key_req.30667852
Directory	/workspace/9.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/9.sram_ctrl_alert_test.2561871793
Short name	T802
Test name
Test status
Simulation time	18824774 ps
CPU time	0.68 seconds
Started	Apr 18 02:31:46 PM PDT 24
Finished	Apr 18 02:31:47 PM PDT 24
Peak memory	202796 kb
Host	smart-2a27cf2f-12f4-4bc0-b7c1-4152b2666bb0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561871793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2561871793
Directory	/workspace/9.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.sram_ctrl_bijection.4063219377
Short name	T42
Test name
Test status
Simulation time	250119887673 ps
CPU time	1324.82 seconds
Started	Apr 18 02:31:30 PM PDT 24
Finished	Apr 18 02:53:35 PM PDT 24
Peak memory	203228 kb
Host	smart-63b03cca-717f-4457-80d2-06588a3e8b88
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063219377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 4063219377
Directory	/workspace/9.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/9.sram_ctrl_executable.3993381728
Short name	T574
Test name
Test status
Simulation time	22939585826 ps
CPU time	1574.29 seconds
Started	Apr 18 02:31:36 PM PDT 24
Finished	Apr 18 02:57:51 PM PDT 24
Peak memory	379908 kb
Host	smart-62d5ced1-a1d6-4666-9954-e64cdfb29b18
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993381728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.3993381728
Directory	/workspace/9.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/9.sram_ctrl_lc_escalation.3911945714
Short name	T623
Test name
Test status
Simulation time	8497394166 ps
CPU time	58.29 seconds
Started	Apr 18 02:31:36 PM PDT 24
Finished	Apr 18 02:32:34 PM PDT 24
Peak memory	203096 kb
Host	smart-9aa9f0ec-f50d-4050-8725-370e05ffa8b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911945714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.3911945714
Directory	/workspace/9.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/9.sram_ctrl_max_throughput.2422161597
Short name	T203
Test name
Test status
Simulation time	3026112433 ps
CPU time	40.38 seconds
Started	Apr 18 02:31:34 PM PDT 24
Finished	Apr 18 02:32:15 PM PDT 24
Peak memory	301184 kb
Host	smart-f4a903cb-3013-4001-a1d6-65af5515a54a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422161597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.2422161597
Directory	/workspace/9.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.493846724
Short name	T79
Test name
Test status
Simulation time	1569288661 ps
CPU time	118.39 seconds
Started	Apr 18 02:31:34 PM PDT 24
Finished	Apr 18 02:33:33 PM PDT 24
Peak memory	211264 kb
Host	smart-e33d3fc1-d59f-4f47-807f-e351dc2c4abd
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493846724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9. sram_ctrl_mem_partial_access.493846724
Directory	/workspace/9.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_walk.3149210771
Short name	T720
Test name
Test status
Simulation time	8229639192 ps
CPU time	123.72 seconds
Started	Apr 18 02:31:35 PM PDT 24
Finished	Apr 18 02:33:39 PM PDT 24
Peak memory	203564 kb
Host	smart-f557d272-9327-49a9-8902-c552c969321d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149210771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.3149210771
Directory	/workspace/9.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/9.sram_ctrl_multiple_keys.3595384333
Short name	T480
Test name
Test status
Simulation time	27465042129 ps
CPU time	290.33 seconds
Started	Apr 18 02:31:30 PM PDT 24
Finished	Apr 18 02:36:20 PM PDT 24
Peak memory	379076 kb
Host	smart-a8d22361-b135-4294-beb1-ce9a1f14e7b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595384333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.3595384333
Directory	/workspace/9.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access.570621967
Short name	T284
Test name
Test status
Simulation time	1534090289 ps
CPU time	23.35 seconds
Started	Apr 18 02:31:37 PM PDT 24
Finished	Apr 18 02:32:01 PM PDT 24
Peak memory	203020 kb
Host	smart-f5308f3e-f504-4bee-a321-26a62e368857
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570621967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sr am_ctrl_partial_access.570621967
Directory	/workspace/9.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2885306993
Short name	T894
Test name
Test status
Simulation time	384717083349 ps
CPU time	476.2 seconds
Started	Apr 18 02:31:30 PM PDT 24
Finished	Apr 18 02:39:26 PM PDT 24
Peak memory	203184 kb
Host	smart-6ae680f1-b4a3-4fce-8656-971452b998ab
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885306993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.2885306993
Directory	/workspace/9.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/9.sram_ctrl_ram_cfg.3319296880
Short name	T458
Test name
Test status
Simulation time	678192411 ps
CPU time	3.45 seconds
Started	Apr 18 02:31:35 PM PDT 24
Finished	Apr 18 02:31:39 PM PDT 24
Peak memory	203048 kb
Host	smart-015c8fd1-4894-4a45-a938-0df2c7713bb7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319296880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3319296880
Directory	/workspace/9.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/9.sram_ctrl_regwen.3219703710
Short name	T696
Test name
Test status
Simulation time	38684935814 ps
CPU time	561.95 seconds
Started	Apr 18 02:31:35 PM PDT 24
Finished	Apr 18 02:40:58 PM PDT 24
Peak memory	376956 kb
Host	smart-c6b73c97-6ed5-4c8a-ac15-e88d2f418ec6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219703710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3219703710
Directory	/workspace/9.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/9.sram_ctrl_smoke.447134605
Short name	T492
Test name
Test status
Simulation time	2646037496 ps
CPU time	94.33 seconds
Started	Apr 18 02:31:31 PM PDT 24
Finished	Apr 18 02:33:06 PM PDT 24
Peak memory	368640 kb
Host	smart-384f621d-a55e-4834-8d0c-e58f5c523223
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447134605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.447134605
Directory	/workspace/9.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all.1353720689
Short name	T922
Test name
Test status
Simulation time	311924675218 ps
CPU time	5773.31 seconds
Started	Apr 18 02:31:41 PM PDT 24
Finished	Apr 18 04:07:56 PM PDT 24
Peak memory	385176 kb
Host	smart-cd76f8c3-2a8f-4201-9ab7-f158e220f5d3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353720689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.1353720689
Directory	/workspace/9.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3594455890
Short name	T884
Test name
Test status
Simulation time	3855207908 ps
CPU time	49.02 seconds
Started	Apr 18 02:31:35 PM PDT 24
Finished	Apr 18 02:32:25 PM PDT 24
Peak memory	220600 kb
Host	smart-25599920-aeb9-4020-9df3-276c03b74c9f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3594455890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3594455890
Directory	/workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3398441890
Short name	T755
Test name
Test status
Simulation time	20248725510 ps
CPU time	312.58 seconds
Started	Apr 18 02:31:32 PM PDT 24
Finished	Apr 18 02:36:45 PM PDT 24
Peak memory	203144 kb
Host	smart-58109309-5254-4712-a259-c796e29aec09
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398441890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.3398441890
Directory	/workspace/9.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3199940359
Short name	T722
Test name
Test status
Simulation time	713566186 ps
CPU time	6.81 seconds
Started	Apr 18 02:31:35 PM PDT 24
Finished	Apr 18 02:31:42 PM PDT 24
Peak memory	211168 kb
Host	smart-30a3873f-871d-4179-ab9d-1476c0c854e0
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199940359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3199940359
Directory	/workspace/9.sram_ctrl_throughput_w_partial_write/latest