Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16124981	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

157943170

1

T1

5766

T2

5232

T3

182967

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85703298	1			T1	3143		T2	3169		T3	100959
values[0x0]	42570990	1			T1	1556		T2	1496		T3	48504
values[0x1]	45793863	1			T1	1700		T2	1749		T3	52017

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8197093	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

165871058

1

T1

6097

T2

5798

T3

192186

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	526607	1			T1	19		T2	22		T3	997
valid_sources[0x01]	528955	1			T1	26		T2	23		T3	930
valid_sources[0x02]	555059	1			T1	6		T2	22		T3	625
valid_sources[0x03]	533688	1			T1	57		T2	32		T3	630
valid_sources[0x04]	563306	1			T1	29		T2	22		T3	778
valid_sources[0x05]	1646571	1			T1	51		T2	21		T3	783
valid_sources[0x06]	534558	1			T1	8		T2	29		T3	995
valid_sources[0x07]	602744	1			T1	18		T2	25		T3	889
valid_sources[0x08]	767981	1			T1	70		T2	21		T3	852
valid_sources[0x09]	537697	1			T1	2		T2	31		T3	861
valid_sources[0x0a]	530657	1			T1	66		T2	16		T3	861
valid_sources[0x0b]	541846	1			T1	14		T2	27		T3	783
valid_sources[0x0c]	527010	1			T1	40		T2	17		T3	865
valid_sources[0x0d]	577253	1			T1	48		T2	19		T3	893
valid_sources[0x0e]	862535	1			T2	32		T3	603		T5	26
valid_sources[0x0f]	606073	1			T1	16		T2	21		T3	746
valid_sources[0x10]	595999	1			T1	30		T2	25		T3	775
valid_sources[0x11]	578512	1			T1	30		T2	19		T3	702
valid_sources[0x12]	540215	1			T1	19		T2	28		T3	898
valid_sources[0x13]	565550	1			T2	37		T3	909		T5	37
valid_sources[0x14]	533304	1			T1	44		T2	25		T3	731
valid_sources[0x15]	543568	1			T1	17		T2	15		T3	698
valid_sources[0x16]	536126	1			T1	8		T2	23		T3	810
valid_sources[0x17]	510392	1			T1	65		T2	27		T3	826
valid_sources[0x18]	1126721	1			T2	20		T3	510		T5	19
valid_sources[0x19]	511865	1			T1	27		T2	29		T3	786
valid_sources[0x1a]	902572	1			T1	9		T2	25		T3	646
valid_sources[0x1b]	740700	1			T2	32		T3	786		T5	34
valid_sources[0x1c]	567074	1			T1	20		T2	31		T3	846
valid_sources[0x1d]	568449	1			T1	3		T2	19		T3	804
valid_sources[0x1e]	1553041	1			T1	48		T2	20		T3	1056
valid_sources[0x1f]	546105	1			T2	26		T3	917		T5	20
valid_sources[0x20]	557790	1			T1	24		T2	21		T3	802
valid_sources[0x21]	2480179	1			T1	26		T2	28		T3	904
valid_sources[0x22]	572974	1			T2	27		T3	788		T5	28
valid_sources[0x23]	525095	1			T1	17		T2	32		T3	624
valid_sources[0x24]	546822	1			T1	14		T2	30		T3	648
valid_sources[0x25]	518730	1			T1	23		T2	12		T3	738
valid_sources[0x26]	535438	1			T1	28		T2	28		T3	756
valid_sources[0x27]	529561	1			T1	10		T2	36		T3	688
valid_sources[0x28]	548138	1			T1	23		T2	24		T3	953
valid_sources[0x29]	516244	1			T1	54		T2	21		T3	525
valid_sources[0x2a]	550062	1			T1	43		T2	32		T3	941
valid_sources[0x2b]	542262	1			T1	27		T2	23		T3	735
valid_sources[0x2c]	589297	1			T2	17		T3	813		T5	34
valid_sources[0x2d]	592102	1			T1	10		T2	29		T3	518
valid_sources[0x2e]	543859	1			T1	47		T2	24		T3	704
valid_sources[0x2f]	592894	1			T1	16		T2	27		T3	725
valid_sources[0x30]	603589	1			T1	32		T2	25		T3	856
valid_sources[0x31]	584626	1			T2	29		T3	873		T5	33
valid_sources[0x32]	524760	1			T1	9		T2	35		T3	1015
valid_sources[0x33]	564684	1			T1	62		T2	14		T3	846
valid_sources[0x34]	880750	1			T1	19		T2	26		T3	815
valid_sources[0x35]	556798	1			T1	18		T2	19		T3	804
valid_sources[0x36]	590439	1			T1	11		T2	25		T3	655
valid_sources[0x37]	545944	1			T1	3		T2	17		T3	950
valid_sources[0x38]	532124	1			T1	6		T2	21		T3	725
valid_sources[0x39]	667228	1			T1	25		T2	32		T3	611
valid_sources[0x3a]	544969	1			T1	40		T2	30		T3	927
valid_sources[0x3b]	622367	1			T1	40		T2	24		T3	806
valid_sources[0x3c]	529844	1			T1	12		T2	30		T3	791
valid_sources[0x3d]	571449	1			T1	31		T2	19		T3	844
valid_sources[0x3e]	608099	1			T1	7		T2	32		T3	830
valid_sources[0x3f]	643211	1			T1	18		T2	21		T3	744
valid_sources[0x40]	519469	1			T1	61		T2	26		T3	663
valid_sources[0x41]	533018	1			T1	31		T2	25		T3	686
valid_sources[0x42]	571528	1			T2	29		T3	805		T5	24
valid_sources[0x43]	531720	1			T1	6		T2	33		T3	667
valid_sources[0x44]	527386	1			T1	8		T2	26		T3	810
valid_sources[0x45]	580589	1			T1	21		T2	32		T3	735
valid_sources[0x46]	535278	1			T1	64		T2	30		T3	1043
valid_sources[0x47]	536730	1			T2	25		T3	1031		T5	30
valid_sources[0x48]	590243	1			T1	30		T2	18		T3	808
valid_sources[0x49]	577333	1			T1	82		T2	20		T3	772
valid_sources[0x4a]	561203	1			T2	19		T3	534		T5	23
valid_sources[0x4b]	546630	1			T1	37		T2	27		T3	827
valid_sources[0x4c]	630966	1			T1	1		T2	27		T3	702
valid_sources[0x4d]	616965	1			T1	44		T2	26		T3	565
valid_sources[0x4e]	582792	1			T1	79		T2	26		T3	730
valid_sources[0x4f]	546894	1			T1	32		T2	24		T3	956
valid_sources[0x50]	589963	1			T1	20		T2	32		T3	1063
valid_sources[0x51]	631533	1			T1	28		T2	22		T3	768
valid_sources[0x52]	539408	1			T1	33		T2	32		T3	593
valid_sources[0x53]	2124861	1			T1	32		T2	18		T3	665
valid_sources[0x54]	571814	1			T1	30		T2	36		T3	931
valid_sources[0x55]	569575	1			T1	95		T2	19		T3	812
valid_sources[0x56]	554970	1			T1	39		T2	30		T3	915
valid_sources[0x57]	550822	1			T1	37		T2	22		T3	798
valid_sources[0x58]	545765	1			T1	65		T2	30		T3	711
valid_sources[0x59]	571577	1			T1	13		T2	29		T3	686
valid_sources[0x5a]	525107	1			T1	13		T2	28		T3	636
valid_sources[0x5b]	517575	1			T1	55		T2	25		T3	938
valid_sources[0x5c]	586820	1			T1	4		T2	22		T3	845
valid_sources[0x5d]	580107	1			T1	18		T2	27		T3	862
valid_sources[0x5e]	571322	1			T1	4		T2	37		T3	556
valid_sources[0x5f]	561999	1			T2	23		T3	979		T5	24
valid_sources[0x60]	549398	1			T1	27		T2	32		T3	609
valid_sources[0x61]	565712	1			T1	2		T2	26		T3	959
valid_sources[0x62]	710336	1			T2	25		T3	852		T5	37
valid_sources[0x63]	572788	1			T1	6		T2	19		T3	1071
valid_sources[0x64]	582698	1			T1	107		T2	29		T3	908
valid_sources[0x65]	542801	1			T1	16		T2	29		T3	875
valid_sources[0x66]	545910	1			T1	4		T2	28		T3	788
valid_sources[0x67]	588724	1			T1	49		T2	26		T3	824
valid_sources[0x68]	2142686	1			T1	55		T2	22		T3	372
valid_sources[0x69]	567283	1			T1	5		T2	31		T3	923
valid_sources[0x6a]	522015	1			T1	52		T2	27		T3	677
valid_sources[0x6b]	515910	1			T1	31		T2	25		T3	802
valid_sources[0x6c]	623785	1			T1	3		T2	25		T3	1009
valid_sources[0x6d]	570677	1			T1	82		T2	24		T3	927
valid_sources[0x6e]	549902	1			T1	9		T2	20		T3	773
valid_sources[0x6f]	596502	1			T1	30		T2	35		T3	727
valid_sources[0x70]	547112	1			T2	32		T3	657		T5	29
valid_sources[0x71]	550023	1			T1	19		T2	27		T3	806
valid_sources[0x72]	621616	1			T1	32		T2	28		T3	903
valid_sources[0x73]	2356995	1			T2	27		T3	620		T5	24
valid_sources[0x74]	549487	1			T1	99		T2	17		T3	963
valid_sources[0x75]	523949	1			T1	64		T2	27		T3	411
valid_sources[0x76]	1260519	1			T1	47		T2	26		T3	732
valid_sources[0x77]	547103	1			T1	19		T2	19		T3	948
valid_sources[0x78]	543859	1			T2	18		T3	1152		T5	22
valid_sources[0x79]	769532	1			T1	4		T2	27		T3	968
valid_sources[0x7a]	569642	1			T1	18		T2	35		T3	519
valid_sources[0x7b]	667467	1			T1	25		T2	27		T3	643
valid_sources[0x7c]	604880	1			T1	50		T2	29		T3	1024
valid_sources[0x7d]	589151	1			T1	6		T2	21		T3	860
valid_sources[0x7e]	532112	1			T1	13		T2	29		T3	974
valid_sources[0x7f]	567412	1			T1	17		T2	17		T3	647
valid_sources[0x80]	2184527	1			T1	11		T2	30		T3	841

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

77600583

1

T1

2837

T2

2585

T3

91746

values[0x0]

all_enables

biggest_size

40165899

1

T1

1463

T2

1317

T3

45723

values[0x1]

all_enables

biggest_size

40176688

1

T1

1466

T2

1330

T3

45498

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33435	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150259

1

T3

10

T9

4

T10

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53134	1			T3	10		T12	11		T17	219
values[0x0]	62904	1			T1	2		T3	27		T5	1
values[0x1]	67656	1			T2	2		T3	25		T5	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25167	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158527

1

T3

14

T5

1

T9

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	693	1			T17	2		T29	11		T45	25
valid_sources[0x01]	700	1			T17	4		T28	147		T7	1
valid_sources[0x02]	610	1			T17	1		T29	11		T45	24
valid_sources[0x03]	610	1			T17	6		T29	8		T45	20
valid_sources[0x04]	679	1			T17	5		T29	5		T45	18
valid_sources[0x05]	893	1			T12	5		T17	5		T29	6
valid_sources[0x06]	814	1			T11	1		T17	1		T28	3
valid_sources[0x07]	789	1			T17	1		T28	14		T37	3
valid_sources[0x08]	767	1			T17	2		T26	1		T28	98
valid_sources[0x09]	687	1			T17	5		T56	2		T36	3
valid_sources[0x0a]	642	1			T17	2		T25	6		T29	6
valid_sources[0x0b]	701	1			T3	1		T17	2		T52	1
valid_sources[0x0c]	748	1			T17	4		T6	181		T28	1
valid_sources[0x0d]	570	1			T17	1		T29	9		T45	14
valid_sources[0x0e]	764	1			T17	4		T29	6		T45	18
valid_sources[0x0f]	620	1			T17	4		T29	4		T45	22
valid_sources[0x10]	625	1			T9	3		T17	3		T28	3
valid_sources[0x11]	599	1			T17	1		T29	11		T45	20
valid_sources[0x12]	1002	1			T17	2		T28	161		T29	3
valid_sources[0x13]	628	1			T17	3		T42	4		T19	2
valid_sources[0x14]	574	1			T17	2		T29	9		T45	27
valid_sources[0x15]	867	1			T53	1		T29	15		T45	18
valid_sources[0x16]	573	1			T17	2		T29	12		T45	25
valid_sources[0x17]	565	1			T1	1		T3	3		T17	3
valid_sources[0x18]	962	1			T17	6		T55	1		T29	5
valid_sources[0x19]	510	1			T17	1		T28	1		T29	12
valid_sources[0x1a]	602	1			T3	2		T17	5		T29	17
valid_sources[0x1b]	590	1			T17	4		T29	6		T45	10
valid_sources[0x1c]	772	1			T17	2		T29	7		T45	17
valid_sources[0x1d]	674	1			T17	5		T7	9		T29	3
valid_sources[0x1e]	679	1			T17	2		T28	3		T56	1
valid_sources[0x1f]	904	1			T17	5		T29	26		T45	21
valid_sources[0x20]	839	1			T17	3		T15	3		T29	2
valid_sources[0x21]	673	1			T17	5		T28	1		T29	4
valid_sources[0x22]	704	1			T17	4		T43	34		T56	1
valid_sources[0x23]	903	1			T55	1		T7	1		T29	3
valid_sources[0x24]	605	1			T17	2		T22	1		T29	3
valid_sources[0x25]	528	1			T17	3		T29	3		T45	21
valid_sources[0x26]	568	1			T5	2		T17	3		T7	1
valid_sources[0x27]	836	1			T3	1		T17	3		T29	6
valid_sources[0x28]	744	1			T17	4		T28	1		T56	4
valid_sources[0x29]	612	1			T17	7		T55	1		T28	1
valid_sources[0x2a]	487	1			T17	5		T29	8		T45	21
valid_sources[0x2b]	530	1			T17	6		T15	1		T28	3
valid_sources[0x2c]	641	1			T17	3		T28	1		T29	3
valid_sources[0x2d]	759	1			T17	4		T29	8		T45	22
valid_sources[0x2e]	590	1			T42	1		T29	14		T45	21
valid_sources[0x2f]	498	1			T3	1		T17	2		T29	7
valid_sources[0x30]	660	1			T17	2		T26	1		T55	1
valid_sources[0x31]	696	1			T17	2		T55	1		T29	12
valid_sources[0x32]	677	1			T3	1		T17	4		T28	2
valid_sources[0x33]	502	1			T13	1		T17	11		T28	1
valid_sources[0x34]	681	1			T12	3		T17	2		T29	5
valid_sources[0x35]	604	1			T17	3		T28	3		T29	2
valid_sources[0x36]	525	1			T17	5		T56	1		T40	2
valid_sources[0x37]	737	1			T17	1		T7	1		T29	10
valid_sources[0x38]	565	1			T17	2		T28	44		T29	5
valid_sources[0x39]	512	1			T17	1		T52	1		T28	1
valid_sources[0x3a]	855	1			T17	3		T29	5		T136	2
valid_sources[0x3b]	760	1			T17	1		T7	1		T90	1
valid_sources[0x3c]	496	1			T3	1		T17	1		T26	1
valid_sources[0x3d]	881	1			T17	3		T55	1		T29	2
valid_sources[0x3e]	530	1			T3	2		T17	6		T29	6
valid_sources[0x3f]	590	1			T17	7		T29	5		T45	20
valid_sources[0x40]	650	1			T3	1		T17	3		T35	26
valid_sources[0x41]	728	1			T17	2		T7	4		T29	1
valid_sources[0x42]	530	1			T17	1		T28	2		T29	7
valid_sources[0x43]	795	1			T17	4		T28	1		T29	2
valid_sources[0x44]	1187	1			T17	2		T26	1		T29	19
valid_sources[0x45]	727	1			T3	1		T17	7		T29	1
valid_sources[0x46]	761	1			T17	3		T28	1		T29	8
valid_sources[0x47]	640	1			T12	2		T17	4		T15	1
valid_sources[0x48]	886	1			T55	2		T28	5		T29	28
valid_sources[0x49]	577	1			T12	1		T17	5		T29	15
valid_sources[0x4a]	988	1			T3	3		T17	6		T22	1
valid_sources[0x4b]	771	1			T17	9		T28	3		T29	11
valid_sources[0x4c]	589	1			T17	2		T55	1		T19	1
valid_sources[0x4d]	918	1			T17	1		T29	20		T45	14
valid_sources[0x4e]	538	1			T3	2		T17	3		T29	4
valid_sources[0x4f]	623	1			T3	2		T17	3		T56	1
valid_sources[0x50]	639	1			T17	4		T28	2		T29	16
valid_sources[0x51]	658	1			T17	6		T53	1		T22	1
valid_sources[0x52]	741	1			T3	1		T17	8		T55	1
valid_sources[0x53]	727	1			T17	2		T28	2		T137	3
valid_sources[0x54]	879	1			T3	1		T17	5		T29	16
valid_sources[0x55]	620	1			T3	1		T12	1		T29	19
valid_sources[0x56]	1312	1			T17	1		T22	1		T28	2
valid_sources[0x57]	693	1			T17	1		T29	15		T45	18
valid_sources[0x58]	999	1			T17	2		T28	103		T29	12
valid_sources[0x59]	868	1			T13	1		T17	6		T28	2
valid_sources[0x5a]	665	1			T3	1		T17	3		T55	1
valid_sources[0x5b]	667	1			T3	2		T28	1		T7	4
valid_sources[0x5c]	1063	1			T3	1		T17	2		T28	4
valid_sources[0x5d]	644	1			T17	4		T19	3		T29	5
valid_sources[0x5e]	521	1			T17	3		T55	1		T29	10
valid_sources[0x5f]	631	1			T17	4		T28	1		T29	6
valid_sources[0x60]	773	1			T12	4		T17	1		T55	2
valid_sources[0x61]	562	1			T2	1		T17	5		T29	14
valid_sources[0x62]	1097	1			T17	1		T19	3		T29	10
valid_sources[0x63]	671	1			T17	3		T55	1		T28	1
valid_sources[0x64]	579	1			T3	3		T17	4		T55	1
valid_sources[0x65]	841	1			T17	3		T37	1		T29	12
valid_sources[0x66]	604	1			T17	2		T25	27		T29	21
valid_sources[0x67]	771	1			T17	2		T29	2		T45	22
valid_sources[0x68]	1025	1			T7	2		T29	5		T45	17
valid_sources[0x69]	653	1			T1	1		T3	5		T17	1
valid_sources[0x6a]	503	1			T17	1		T7	2		T29	8
valid_sources[0x6b]	1018	1			T17	2		T28	164		T137	1
valid_sources[0x6c]	1039	1			T17	1		T28	1		T7	3
valid_sources[0x6d]	639	1			T17	2		T28	1		T29	9
valid_sources[0x6e]	628	1			T17	3		T28	42		T7	1
valid_sources[0x6f]	966	1			T17	6		T55	1		T28	95
valid_sources[0x70]	730	1			T3	1		T17	4		T8	130
valid_sources[0x71]	429	1			T17	4		T28	1		T29	9
valid_sources[0x72]	709	1			T17	3		T18	42		T55	1
valid_sources[0x73]	617	1			T17	5		T28	4		T29	3
valid_sources[0x74]	610	1			T3	1		T17	3		T19	1
valid_sources[0x75]	554	1			T17	4		T28	3		T29	3
valid_sources[0x76]	608	1			T17	4		T55	1		T56	4
valid_sources[0x77]	761	1			T17	6		T29	5		T45	20
valid_sources[0x78]	546	1			T3	1		T17	5		T56	3
valid_sources[0x79]	701	1			T12	1		T17	6		T26	2
valid_sources[0x7a]	862	1			T17	5		T28	13		T7	3
valid_sources[0x7b]	617	1			T12	2		T17	1		T29	23
valid_sources[0x7c]	722	1			T13	2		T17	4		T52	1
valid_sources[0x7d]	688	1			T17	3		T55	1		T28	25
valid_sources[0x7e]	801	1			T17	8		T28	3		T7	2
valid_sources[0x7f]	598	1			T17	2		T28	2		T7	4
valid_sources[0x80]	1070	1			T17	4		T28	1		T29	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41160

1

T3

3

T12

4

T17

189

values[0x0]

all_enables

biggest_size

55262

1

T3

4

T9

4

T12

5

values[0x1]

all_enables

biggest_size

53837

1

T3

3

T10

1

T12

6