Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16007669

1

T1

633

T2

1182

T3

15914

full_word

154744134

1

T1

5766

T2

5232

T3

156554

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	170751523	1			T1	6399		T2	6414		T3	172468
auto[TlIntgErrCmd]	97	1			T98	8		T99	6		T100	3
auto[TlIntgErrData]	100	1			T98	7		T99	9		T100	5
auto[TlIntgErrBoth]	83	1			T98	5		T99	5		T100	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82317642

1

T1

3143

T2

3169

T3

72260

auto[1]

88434161

1

T1

3256

T2

3245

T3

100208

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7832407	1			T1	306		T2	584		T3	6650
auto[TlIntgErrNone]	partial	auto[1]	8175009	1			T1	327		T2	598		T3	9264
auto[TlIntgErrNone]	full_word	auto[0]	74485101	1			T1	2837		T2	2585		T3	65610
auto[TlIntgErrNone]	full_word	auto[1]	80259006	1			T1	2929		T2	2647		T3	90944
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T98	5		T99	4		T120	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T98	3		T99	1		T100	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T100	1		T124	2		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T99	1		T125	2		T121	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T98	5		T99	6		T100	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T98	2		T99	2		T100	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T99	1		T100	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T121	2		T128	2		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T98	3		T99	3		T100	2
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T98	1		T99	2		T124	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T125	1		T123	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T98	1		T129	1		T128	2