Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	812618	1			T11	8403		T14	738		T15	7370
auto[1]	11583976	1			T2	3168		T3	6418		T5	3461
auto[2]	639774	1			T11	5732		T14	540		T15	6622
auto[3]	11286765	1			T2	3244		T3	4697		T5	3475

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15602529	1			T2	4300		T3	9211		T5	5763
auto[1]	2235354	1			T2	931		T3	887		T5	578
auto[2]	2258487	1			T2	969		T3	926		T5	545
auto[3]	4226763	1			T2	212		T3	91		T5	50

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10835476

1

T2

6411

T3

11115

T5

6936

auto[1]

13487657

1

T2

1

T9

3

T11

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	380078	1			T11	1		T14	33		T15	6132
auto[0]	auto[0]	auto[1]	38833	1			T11	74		T14	97		T15	620
auto[0]	auto[0]	auto[2]	38752	1			T11	71		T14	109		T15	558
auto[0]	auto[0]	auto[3]	60570	1			T11	8255		T14	499		T15	60
auto[0]	auto[1]	auto[0]	3719881	1			T2	2130		T3	5331		T5	2862
auto[0]	auto[1]	auto[1]	395802	1			T2	454		T3	491		T5	290
auto[0]	auto[1]	auto[2]	418375	1			T2	493		T3	544		T5	286
auto[0]	auto[1]	auto[3]	544790	1			T2	91		T3	52		T5	23
auto[0]	auto[2]	auto[0]	299201	1			T11	7		T14	23		T15	5500
auto[0]	auto[2]	auto[1]	34604	1			T11	694		T14	103		T15	565
auto[0]	auto[2]	auto[2]	27822	1			T11	51		T14	63		T15	514
auto[0]	auto[2]	auto[3]	41863	1			T11	4980		T14	351		T15	41
auto[0]	auto[3]	auto[0]	3529227	1			T2	2170		T3	3880		T5	2901
auto[0]	auto[3]	auto[1]	394853	1			T2	476		T3	396		T5	288
auto[0]	auto[3]	auto[2]	413294	1			T2	476		T3	382		T5	259
auto[0]	auto[3]	auto[3]	497531	1			T2	121		T3	39		T5	27
auto[1]	auto[0]	auto[0]	9703	1			T94	1132		T133	838		T134	1
auto[1]	auto[0]	auto[1]	43909	1			T94	4929		T133	4025		T135	974
auto[1]	auto[0]	auto[2]	43813	1			T94	5111		T133	3865		T135	952
auto[1]	auto[0]	auto[3]	196960	1			T11	2		T94	23153		T133	17622
auto[1]	auto[1]	auto[0]	3826453	1			T18	2		T52	107919		T53	1
auto[1]	auto[1]	auto[1]	660388	1			T52	9667		T90	9405		T36	7624
auto[1]	auto[1]	auto[2]	632388	1			T9	1		T52	10821		T90	10761
auto[1]	auto[1]	auto[3]	1385899	1			T52	930		T90	989		T36	745
auto[1]	auto[2]	auto[0]	8657	1			T15	2		T94	1006		T133	798
auto[1]	auto[2]	auto[1]	39365	1			T94	4710		T133	3644		T135	538
auto[1]	auto[2]	auto[2]	34496	1			T94	3478		T133	3333		T135	1069
auto[1]	auto[2]	auto[3]	153766	1			T94	15480		T133	14830		T135	4648
auto[1]	auto[3]	auto[0]	3829329	1			T9	2		T18	4		T52	108587
auto[1]	auto[3]	auto[1]	627600	1			T2	1		T18	1		T52	10812
auto[1]	auto[3]	auto[2]	649547	1			T52	9649		T90	9484		T36	7668
auto[1]	auto[3]	auto[3]	1345384	1			T52	954		T90	1013		T36	745