Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1126596966	145234	0	0
ctrl_regwen_rd_A	1126596966	6387	0	0
exec_rd_A	1126596966	6025	0	0
exec_regwen_rd_A	1126596966	6464	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126596966	145234	0	0
T8	337454	0	0	0
T14	75910	0	0	0
T16	54053	0	0	0
T17	22608	795	0	0
T18	175029	0	0	0
T25	167283	0	0	0
T26	279774	0	0	0
T28	0	3258	0	0
T29	0	2381	0	0
T45	0	5755	0	0
T46	0	4302	0	0
T47	0	948	0	0
T48	0	638	0	0
T49	0	4936	0	0
T50	0	1480	0	0
T51	0	3029	0	0
T52	531641	0	0	0
T53	71057	0	0	0
T54	121635	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126596966	6387	0	0
T48	21524	112	0	0
T49	156381	0	0	0
T50	0	466	0	0
T74	166837	0	0	0
T101	0	359	0	0
T102	0	298	0	0
T103	0	726	0	0
T104	0	245	0	0
T105	0	154	0	0
T106	0	263	0	0
T107	0	592	0	0
T108	0	507	0	0
T109	34758	0	0	0
T110	691335	0	0	0
T111	33747	0	0	0
T112	815309	0	0	0
T113	1358	0	0	0
T114	74359	0	0	0
T115	77824	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126596966	6025	0	0
T48	21524	60	0	0
T49	156381	0	0	0
T50	0	416	0	0
T74	166837	0	0	0
T101	0	318	0	0
T102	0	236	0	0
T103	0	774	0	0
T104	0	281	0	0
T105	0	125	0	0
T106	0	351	0	0
T107	0	643	0	0
T108	0	384	0	0
T109	34758	0	0	0
T110	691335	0	0	0
T111	33747	0	0	0
T112	815309	0	0	0
T113	1358	0	0	0
T114	74359	0	0	0
T115	77824	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126596966	6464	0	0
T48	21524	72	0	0
T49	156381	0	0	0
T50	0	459	0	0
T74	166837	0	0	0
T101	0	394	0	0
T102	0	229	0	0
T103	0	775	0	0
T104	0	312	0	0
T105	0	173	0	0
T106	0	311	0	0
T107	0	711	0	0
T108	0	439	0	0
T109	34758	0	0	0
T110	691335	0	0	0
T111	33747	0	0	0
T112	815309	0	0	0
T113	1358	0	0	0
T114	74359	0	0	0
T115	77824	0	0	0