Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15599517

1

T1

59533

T2

5867

T3

16

full_word

162608163

1

T1

3143

T2

1275

T3

190

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	178207380	1			T1	62676		T2	7142		T3	206
auto[TlIntgErrCmd]	92	1			T96	4		T97	4		T98	4
auto[TlIntgErrData]	96	1			T96	10		T97	2		T98	3
auto[TlIntgErrBoth]	112	1			T96	6		T97	4		T98	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86218079

1

T1

31456

T2

3576

T3

94

auto[1]

91989601

1

T1

31220

T2

3566

T3

112

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7640485	1			T1	31173		T2	2903		T3	6
auto[TlIntgErrNone]	partial	auto[1]	7958763	1			T1	28360		T2	2964		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	78577450	1			T1	283		T2	673		T3	88
auto[TlIntgErrNone]	full_word	auto[1]	84030682	1			T1	2860		T2	602		T3	102
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T96	2		T98	3		T116	1
auto[TlIntgErrCmd]	partial	auto[1]	39	1			T96	2		T97	2		T98	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T97	1		T118	2		T121	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T97	1		T122	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T96	6		T97	1		T98	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T96	3		T97	1		T98	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T96	1		T123	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T123	1		T124	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T96	2		T97	2		T98	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T96	4		T97	2		T98	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T119	1		T124	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T118	1		T125	1		T124	1