Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	644260	1			T7	16		T13	319		T14	2
auto[1]	11126079	1			T1	30048		T3	2		T6	14095
auto[2]	510678	1			T7	15		T13	255		T14	3
auto[3]	10879905	1			T1	29791		T3	6		T6	14503

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14489217	1			T1	288		T3	6		T6	128
auto[1]	2127349	1			T1	2842		T3	1		T6	1356
auto[2]	2164255	1			T1	5233		T3	1		T6	2449
auto[3]	4380101	1			T1	51476		T6	24665		T5	32

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10054772

1

T1

59838

T3

8

T6

28597

auto[1]

13106150

1

T1

1

T6

1

T16

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	258054	1			T7	12		T13	261		T14	1
auto[0]	auto[0]	auto[1]	26778	1			T7	4		T13	27		T132	1
auto[0]	auto[0]	auto[2]	26822	1			T13	28		T14	1		T132	1
auto[0]	auto[0]	auto[3]	98565	1			T13	3		T132	11		T133	16
auto[0]	auto[1]	auto[0]	3429174	1			T1	28		T3	2		T6	12
auto[0]	auto[1]	auto[1]	361972	1			T1	242		T6	109		T5	172
auto[0]	auto[1]	auto[2]	389279	1			T1	2756		T6	1344		T5	236
auto[0]	auto[1]	auto[3]	592893	1			T1	27021		T6	12630		T5	20
auto[0]	auto[2]	auto[0]	198302	1			T7	10		T13	211		T14	1
auto[0]	auto[2]	auto[1]	27410	1			T7	4		T13	20		T14	2
auto[0]	auto[2]	auto[2]	18870	1			T7	1		T13	23		T132	1
auto[0]	auto[2]	auto[3]	66111	1			T13	1		T132	2		T133	10
auto[0]	auto[3]	auto[0]	3272250	1			T1	260		T3	4		T6	116
auto[0]	auto[3]	auto[1]	370812	1			T1	2600		T3	1		T6	1247
auto[0]	auto[3]	auto[2]	384581	1			T1	2477		T3	1		T6	1105
auto[0]	auto[3]	auto[3]	532899	1			T1	24454		T6	12034		T5	12
auto[1]	auto[0]	auto[0]	7689	1			T134	1		T130	706		T135	2
auto[1]	auto[0]	auto[1]	34432	1			T130	3309		T136	1		T137	3450
auto[1]	auto[0]	auto[2]	34781	1			T130	3309		T137	3511		T138	2204
auto[1]	auto[0]	auto[3]	157139	1			T77	5		T130	15152		T131	1
auto[1]	auto[1]	auto[0]	3660397	1			T42	3121		T41	1		T68	53999
auto[1]	auto[1]	auto[1]	645132	1			T42	12457		T68	4859		T24	2
auto[1]	auto[1]	auto[2]	638603	1			T42	14033		T68	5254		T69	5197
auto[1]	auto[1]	auto[3]	1408629	1			T1	1		T42	56627		T68	441
auto[1]	auto[2]	auto[0]	6164	1			T134	1		T130	680		T137	671
auto[1]	auto[2]	auto[1]	28372	1			T130	3068		T137	3202		T138	1322
auto[1]	auto[2]	auto[2]	29775	1			T130	2791		T137	2270		T138	2081
auto[1]	auto[2]	auto[3]	135674	1			T77	1		T130	12636		T137	10579
auto[1]	auto[3]	auto[0]	3657187	1			T16	2		T42	3223		T41	2
auto[1]	auto[3]	auto[1]	632441	1			T42	13977		T68	5420		T69	5202
auto[1]	auto[3]	auto[2]	641544	1			T42	12662		T68	4828		T69	4578
auto[1]	auto[3]	auto[3]	1388191	1			T6	1		T42	56420		T68	464