Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1064767782	156910	0	0
ctrl_regwen_rd_A	1064767782	9989	0	0
exec_rd_A	1064767782	8918	0	0
exec_regwen_rd_A	1064767782	10003	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1064767782	156910	0	0
T5	38576	0	0	0
T7	735653	0	0	0
T10	87252	2356	0	0
T11	36770	1028	0	0
T12	72454	0	0	0
T13	519670	0	0	0
T14	0	2370	0	0
T15	72797	0	0	0
T16	401270	0	0	0
T46	0	4614	0	0
T47	0	6383	0	0
T48	0	1530	0	0
T49	0	808	0	0
T50	0	1420	0	0
T51	0	5578	0	0
T52	0	3488	0	0
T53	76279	0	0	0
T54	76835	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1064767782	9989	0	0
T14	85263	464	0	0
T24	215262	0	0	0
T25	335426	0	0	0
T26	277149	0	0	0
T27	33688	0	0	0
T69	402696	0	0	0
T90	630612	0	0	0
T100	0	393	0	0
T101	0	947	0	0
T102	0	487	0	0
T103	0	481	0	0
T104	0	955	0	0
T105	0	792	0	0
T106	0	1266	0	0
T107	0	491	0	0
T108	0	412	0	0
T109	70054	0	0	0
T110	202611	0	0	0
T111	194138	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1064767782	8918	0	0
T14	85263	389	0	0
T24	215262	0	0	0
T25	335426	0	0	0
T26	277149	0	0	0
T27	33688	0	0	0
T69	402696	0	0	0
T90	630612	0	0	0
T100	0	376	0	0
T101	0	913	0	0
T102	0	476	0	0
T103	0	437	0	0
T104	0	735	0	0
T105	0	723	0	0
T106	0	1156	0	0
T107	0	269	0	0
T108	0	298	0	0
T109	70054	0	0	0
T110	202611	0	0	0
T111	194138	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1064767782	10003	0	0
T14	85263	484	0	0
T24	215262	0	0	0
T25	335426	0	0	0
T26	277149	0	0	0
T27	33688	0	0	0
T69	402696	0	0	0
T90	630612	0	0	0
T100	0	383	0	0
T101	0	1032	0	0
T102	0	446	0	0
T103	0	414	0	0
T104	0	880	0	0
T105	0	669	0	0
T106	0	1366	0	0
T107	0	448	0	0
T108	0	420	0	0
T109	70054	0	0	0
T110	202611	0	0	0
T111	194138	0	0	0