Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16074261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

164427556

1

T1

117324

T2

311

T3

1553

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88928908	1			T1	64258		T2	894		T3	392
values[0x0]	44192111	1			T1	31329		T2	295		T3	573
values[0x1]	47380798	1			T1	33533		T2	568		T3	588

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8183854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

172317963

1

T1

123296

T2

1049

T3

1553

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	555876	1			T1	514		T2	6		T3	5
valid_sources[0x01]	2120218	1			T1	547		T2	7		T3	5
valid_sources[0x02]	553079	1			T1	500		T2	12		T3	13
valid_sources[0x03]	568864	1			T1	485		T2	20		T3	2
valid_sources[0x04]	546924	1			T1	546		T2	4		T3	9
valid_sources[0x05]	600845	1			T1	497		T2	10		T3	2
valid_sources[0x06]	572785	1			T1	511		T2	7		T3	15
valid_sources[0x07]	544356	1			T1	504		T2	7		T3	3
valid_sources[0x08]	558015	1			T1	481		T2	5		T3	4
valid_sources[0x09]	1990726	1			T1	519		T2	8		T3	1
valid_sources[0x0a]	660134	1			T1	489		T2	12		T3	3
valid_sources[0x0b]	553389	1			T1	511		T2	5		T3	14
valid_sources[0x0c]	624310	1			T1	486		T2	4		T3	9
valid_sources[0x0d]	554861	1			T1	502		T2	7		T3	8
valid_sources[0x0e]	564218	1			T1	512		T2	1		T3	3
valid_sources[0x0f]	577319	1			T1	478		T2	10		T3	6
valid_sources[0x10]	573722	1			T1	507		T2	5		T3	9
valid_sources[0x11]	560294	1			T1	535		T2	11		T3	5
valid_sources[0x12]	557047	1			T1	469		T2	4		T3	1
valid_sources[0x13]	2039420	1			T1	456		T2	10		T3	6
valid_sources[0x14]	677647	1			T1	575		T2	7		T3	2
valid_sources[0x15]	563589	1			T1	500		T2	10		T3	10
valid_sources[0x16]	566209	1			T1	477		T2	7		T5	366
valid_sources[0x17]	581554	1			T1	523		T2	14		T3	18
valid_sources[0x18]	1524541	1			T1	581		T2	10		T3	2
valid_sources[0x19]	575466	1			T1	451		T2	6		T3	8
valid_sources[0x1a]	600116	1			T1	497		T2	6		T3	10
valid_sources[0x1b]	551813	1			T1	509		T2	2		T3	4
valid_sources[0x1c]	688383	1			T1	543		T2	14		T3	6
valid_sources[0x1d]	663785	1			T1	485		T2	4		T3	7
valid_sources[0x1e]	578365	1			T1	466		T2	4		T3	11
valid_sources[0x1f]	594596	1			T1	500		T2	2		T3	2
valid_sources[0x20]	998154	1			T1	506		T2	4		T3	5
valid_sources[0x21]	535982	1			T1	517		T2	2		T3	2
valid_sources[0x22]	600223	1			T1	511		T2	4		T3	7
valid_sources[0x23]	636781	1			T1	492		T2	10		T3	6
valid_sources[0x24]	618312	1			T1	471		T2	10		T3	5
valid_sources[0x25]	615691	1			T1	535		T2	20		T3	5
valid_sources[0x26]	583402	1			T1	576		T2	13		T3	9
valid_sources[0x27]	534386	1			T1	504		T2	1		T3	4
valid_sources[0x28]	680818	1			T1	535		T2	5		T3	4
valid_sources[0x29]	546585	1			T1	522		T2	6		T3	8
valid_sources[0x2a]	613627	1			T1	551		T2	6		T3	5
valid_sources[0x2b]	581849	1			T1	468		T2	7		T3	1
valid_sources[0x2c]	569336	1			T1	423		T2	16		T3	5
valid_sources[0x2d]	582315	1			T1	515		T2	3		T3	1
valid_sources[0x2e]	541662	1			T1	486		T2	10		T3	1
valid_sources[0x2f]	594494	1			T1	477		T2	5		T3	3
valid_sources[0x30]	634955	1			T1	534		T2	10		T5	266
valid_sources[0x31]	601296	1			T1	560		T2	7		T3	8
valid_sources[0x32]	647127	1			T1	510		T2	5		T3	5
valid_sources[0x33]	1743723	1			T1	528		T2	12		T3	11
valid_sources[0x34]	1958756	1			T1	618		T2	10		T3	1
valid_sources[0x35]	553475	1			T1	536		T2	3		T3	3
valid_sources[0x36]	632499	1			T1	552		T2	3		T3	16
valid_sources[0x37]	557603	1			T1	524		T2	9		T3	4
valid_sources[0x38]	577533	1			T1	543		T2	11		T3	2
valid_sources[0x39]	548582	1			T1	505		T2	4		T3	11
valid_sources[0x3a]	539846	1			T1	469		T2	2		T3	4
valid_sources[0x3b]	704830	1			T1	519		T2	11		T3	5
valid_sources[0x3c]	545434	1			T1	476		T2	5		T3	5
valid_sources[0x3d]	608257	1			T1	504		T2	5		T3	6
valid_sources[0x3e]	560606	1			T1	465		T2	2		T3	11
valid_sources[0x3f]	572925	1			T1	486		T2	7		T3	10
valid_sources[0x40]	607748	1			T1	558		T2	5		T3	5
valid_sources[0x41]	588222	1			T1	492		T2	14		T3	11
valid_sources[0x42]	632089	1			T1	478		T2	7		T3	4
valid_sources[0x43]	564585	1			T1	493		T2	5		T3	1
valid_sources[0x44]	556867	1			T1	503		T2	7		T3	3
valid_sources[0x45]	1638509	1			T1	524		T2	8		T3	13
valid_sources[0x46]	632145	1			T1	525		T2	6		T3	4
valid_sources[0x47]	2024671	1			T1	505		T2	11		T3	5
valid_sources[0x48]	554751	1			T1	538		T2	1		T3	6
valid_sources[0x49]	543475	1			T1	502		T2	4		T3	3
valid_sources[0x4a]	560011	1			T1	515		T2	5		T3	13
valid_sources[0x4b]	550514	1			T1	525		T2	9		T3	4
valid_sources[0x4c]	581432	1			T1	498		T2	2		T3	8
valid_sources[0x4d]	539682	1			T1	490		T2	17		T3	3
valid_sources[0x4e]	1361192	1			T1	496		T2	6		T3	4
valid_sources[0x4f]	599077	1			T1	487		T2	7		T3	8
valid_sources[0x50]	629607	1			T1	472		T2	6		T3	11
valid_sources[0x51]	601234	1			T1	473		T2	5		T3	8
valid_sources[0x52]	606938	1			T1	492		T2	5		T3	10
valid_sources[0x53]	604703	1			T1	533		T2	5		T3	6
valid_sources[0x54]	533201	1			T1	499		T2	5		T3	4
valid_sources[0x55]	640288	1			T1	547		T2	13		T3	7
valid_sources[0x56]	3296021	1			T1	521		T2	13		T3	1
valid_sources[0x57]	630548	1			T1	494		T2	5		T3	7
valid_sources[0x58]	559012	1			T1	521		T2	5		T3	4
valid_sources[0x59]	596666	1			T1	525		T2	3		T3	25
valid_sources[0x5a]	569625	1			T1	542		T2	8		T3	1
valid_sources[0x5b]	817486	1			T1	458		T2	6		T3	13
valid_sources[0x5c]	557579	1			T1	516		T2	2		T3	7
valid_sources[0x5d]	1354626	1			T1	516		T2	5		T3	8
valid_sources[0x5e]	590940	1			T1	538		T2	5		T3	7
valid_sources[0x5f]	586185	1			T1	524		T2	4		T3	3
valid_sources[0x60]	650166	1			T1	493		T2	9		T3	7
valid_sources[0x61]	551801	1			T1	504		T2	4		T3	1
valid_sources[0x62]	549321	1			T1	537		T2	9		T3	6
valid_sources[0x63]	762377	1			T1	522		T2	3		T3	3
valid_sources[0x64]	575535	1			T1	458		T2	6		T5	630
valid_sources[0x65]	549643	1			T1	492		T2	3		T3	7
valid_sources[0x66]	2045902	1			T1	500		T2	8		T3	1
valid_sources[0x67]	537040	1			T1	510		T2	9		T3	4
valid_sources[0x68]	601543	1			T1	480		T2	6		T3	1
valid_sources[0x69]	579157	1			T1	543		T2	6		T3	10
valid_sources[0x6a]	1587682	1			T1	562		T2	7		T3	6
valid_sources[0x6b]	602839	1			T1	469		T2	12		T3	4
valid_sources[0x6c]	582278	1			T1	528		T2	2		T3	5
valid_sources[0x6d]	542505	1			T1	494		T2	9		T3	12
valid_sources[0x6e]	593578	1			T1	477		T2	6		T3	14
valid_sources[0x6f]	552155	1			T1	497		T2	11		T3	10
valid_sources[0x70]	647445	1			T1	462		T2	3		T3	4
valid_sources[0x71]	664786	1			T1	546		T2	6		T3	6
valid_sources[0x72]	556590	1			T1	484		T2	9		T3	6
valid_sources[0x73]	592713	1			T1	511		T2	5		T3	8
valid_sources[0x74]	572198	1			T1	548		T2	22		T3	3
valid_sources[0x75]	587129	1			T1	557		T2	12		T3	6
valid_sources[0x76]	614218	1			T1	460		T2	5		T3	2
valid_sources[0x77]	599987	1			T1	439		T2	12		T3	5
valid_sources[0x78]	546855	1			T1	510		T2	4		T3	11
valid_sources[0x79]	571780	1			T1	478		T2	8		T3	13
valid_sources[0x7a]	556609	1			T1	495		T2	11		T3	3
valid_sources[0x7b]	539125	1			T1	549		T2	6		T3	3
valid_sources[0x7c]	558140	1			T1	492		T2	5		T3	1
valid_sources[0x7d]	599386	1			T1	465		T2	4		T3	10
valid_sources[0x7e]	632842	1			T1	507		T2	5		T3	11
valid_sources[0x7f]	576288	1			T1	501		T2	4		T3	5
valid_sources[0x80]	573440	1			T1	524		T2	8		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80846435

1

T1

58384

T2

168

T3

392

values[0x0]

all_enables

biggest_size

41792899

1

T1

29539

T2

77

T3

573

values[0x1]

all_enables

biggest_size

41788222

1

T1

29401

T2

66

T3

588

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33418	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150021

1

T1

6

T3

1696

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52895	1			T3	458		T4	21		T16	9
values[0x0]	63366	1			T1	11		T2	1		T3	612
values[0x1]	67178	1			T1	8		T3	696		T9	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25259	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158180

1

T1

10

T3

1728

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	955	1			T3	6		T4	1		T8	3
valid_sources[0x01]	445	1			T3	5		T6	2		T135	1
valid_sources[0x02]	767	1			T3	7		T4	4		T140	1
valid_sources[0x03]	790	1			T3	6		T24	3		T8	2
valid_sources[0x04]	1027	1			T3	5		T4	2		T50	5
valid_sources[0x05]	911	1			T3	7		T28	1		T50	9
valid_sources[0x06]	727	1			T3	5		T24	4		T6	1
valid_sources[0x07]	441	1			T3	2		T6	1		T141	1
valid_sources[0x08]	684	1			T3	2		T8	1		T138	9
valid_sources[0x09]	575	1			T3	6		T140	1		T8	6
valid_sources[0x0a]	1118	1			T3	4		T4	7		T8	2
valid_sources[0x0b]	817	1			T3	9		T91	1		T26	1
valid_sources[0x0c]	615	1			T3	6		T24	1		T6	9
valid_sources[0x0d]	535	1			T3	13		T4	1		T17	2
valid_sources[0x0e]	874	1			T3	3		T6	1		T8	1
valid_sources[0x0f]	572	1			T3	12		T28	1		T8	2
valid_sources[0x10]	801	1			T3	9		T8	3		T26	4
valid_sources[0x11]	675	1			T3	6		T4	1		T141	1
valid_sources[0x12]	962	1			T3	6		T8	6		T26	1
valid_sources[0x13]	762	1			T3	7		T26	4		T135	2
valid_sources[0x14]	939	1			T3	9		T6	1		T8	3
valid_sources[0x15]	638	1			T3	6		T8	1		T26	82
valid_sources[0x16]	587	1			T3	7		T12	1		T23	3
valid_sources[0x17]	615	1			T3	8		T142	4		T143	1
valid_sources[0x18]	505	1			T3	10		T52	1		T27	13
valid_sources[0x19]	548	1			T3	8		T28	2		T8	2
valid_sources[0x1a]	636	1			T1	2		T3	15		T26	1
valid_sources[0x1b]	652	1			T3	8		T28	1		T6	1
valid_sources[0x1c]	760	1			T3	8		T26	1		T52	4
valid_sources[0x1d]	663	1			T3	12		T8	3		T51	1
valid_sources[0x1e]	884	1			T3	5		T8	5		T138	3
valid_sources[0x1f]	700	1			T3	5		T4	1		T8	3
valid_sources[0x20]	673	1			T3	10		T6	3		T50	1
valid_sources[0x21]	759	1			T3	6		T4	3		T8	2
valid_sources[0x22]	625	1			T3	13		T140	1		T8	2
valid_sources[0x23]	725	1			T3	4		T4	1		T21	1
valid_sources[0x24]	848	1			T3	7		T6	3		T144	6
valid_sources[0x25]	955	1			T3	5		T50	6		T8	8
valid_sources[0x26]	684	1			T3	8		T4	2		T8	2
valid_sources[0x27]	726	1			T3	7		T4	1		T140	1
valid_sources[0x28]	719	1			T3	5		T6	3		T50	10
valid_sources[0x29]	612	1			T3	6		T8	3		T26	113
valid_sources[0x2a]	604	1			T3	9		T6	1		T8	1
valid_sources[0x2b]	885	1			T3	6		T4	5		T6	3
valid_sources[0x2c]	533	1			T3	3		T8	1		T135	1
valid_sources[0x2d]	795	1			T3	7		T8	1		T26	1
valid_sources[0x2e]	1183	1			T3	19		T8	1		T141	1
valid_sources[0x2f]	558	1			T3	7		T50	5		T135	2
valid_sources[0x30]	577	1			T3	5		T6	6		T135	1
valid_sources[0x31]	695	1			T3	3		T9	1		T8	7
valid_sources[0x32]	657	1			T3	6		T9	1		T50	1
valid_sources[0x33]	717	1			T1	4		T3	3		T50	1
valid_sources[0x34]	488	1			T3	11		T8	4		T138	1
valid_sources[0x35]	573	1			T3	3		T4	2		T6	2
valid_sources[0x36]	908	1			T3	4		T25	1		T135	4
valid_sources[0x37]	632	1			T3	6		T28	1		T26	6
valid_sources[0x38]	540	1			T3	7		T8	2		T26	3
valid_sources[0x39]	712	1			T3	6		T26	143		T138	2
valid_sources[0x3a]	851	1			T3	6		T4	2		T6	1
valid_sources[0x3b]	1265	1			T3	4		T4	2		T6	1
valid_sources[0x3c]	553	1			T3	6		T8	4		T26	14
valid_sources[0x3d]	535	1			T3	8		T21	1		T50	6
valid_sources[0x3e]	624	1			T3	14		T28	2		T8	1
valid_sources[0x3f]	518	1			T3	6		T50	1		T25	2
valid_sources[0x40]	595	1			T3	10		T4	7		T93	1
valid_sources[0x41]	617	1			T3	7		T8	1		T26	4
valid_sources[0x42]	597	1			T3	7		T26	2		T135	1
valid_sources[0x43]	576	1			T3	5		T5	1		T28	1
valid_sources[0x44]	671	1			T3	11		T145	1		T6	2
valid_sources[0x45]	725	1			T3	6		T28	1		T6	14
valid_sources[0x46]	566	1			T3	7		T6	1		T8	1
valid_sources[0x47]	1032	1			T3	3		T4	1		T26	61
valid_sources[0x48]	539	1			T3	8		T8	2		T26	1
valid_sources[0x49]	605	1			T3	1		T4	1		T8	1
valid_sources[0x4a]	523	1			T3	4		T8	3		T146	3
valid_sources[0x4b]	1020	1			T3	8		T28	1		T50	2
valid_sources[0x4c]	742	1			T3	6		T28	1		T8	1
valid_sources[0x4d]	643	1			T3	4		T8	6		T141	1
valid_sources[0x4e]	642	1			T3	6		T6	2		T8	1
valid_sources[0x4f]	529	1			T3	9		T8	1		T147	1
valid_sources[0x50]	659	1			T3	10		T8	5		T53	1
valid_sources[0x51]	527	1			T3	10		T6	1		T8	2
valid_sources[0x52]	1155	1			T3	3		T50	1		T8	1
valid_sources[0x53]	732	1			T3	7		T28	1		T8	1
valid_sources[0x54]	766	1			T3	3		T4	3		T148	1
valid_sources[0x55]	754	1			T3	7		T21	1		T6	2
valid_sources[0x56]	736	1			T3	6		T6	1		T141	2
valid_sources[0x57]	914	1			T1	3		T3	14		T9	1
valid_sources[0x58]	713	1			T3	10		T9	2		T140	1
valid_sources[0x59]	614	1			T3	3		T28	1		T8	1
valid_sources[0x5a]	777	1			T3	16		T6	2		T26	135
valid_sources[0x5b]	587	1			T3	9		T93	1		T8	2
valid_sources[0x5c]	590	1			T3	4		T4	2		T8	2
valid_sources[0x5d]	772	1			T3	7		T13	1		T6	4
valid_sources[0x5e]	825	1			T3	5		T50	1		T8	1
valid_sources[0x5f]	701	1			T2	1		T3	14		T50	1
valid_sources[0x60]	681	1			T3	7		T8	1		T27	8
valid_sources[0x61]	617	1			T3	2		T6	2		T8	2
valid_sources[0x62]	567	1			T3	13		T91	3		T8	4
valid_sources[0x63]	758	1			T3	2		T8	2		T138	7
valid_sources[0x64]	476	1			T3	9		T6	1		T8	2
valid_sources[0x65]	1003	1			T3	6		T22	3		T149	1
valid_sources[0x66]	622	1			T3	8		T6	1		T140	1
valid_sources[0x67]	735	1			T3	7		T8	2		T150	2
valid_sources[0x68]	571	1			T3	1		T8	3		T53	1
valid_sources[0x69]	931	1			T3	5		T28	2		T6	1
valid_sources[0x6a]	623	1			T3	8		T8	1		T27	7
valid_sources[0x6b]	544	1			T3	8		T8	2		T51	2
valid_sources[0x6c]	939	1			T3	7		T4	1		T15	3
valid_sources[0x6d]	748	1			T3	5		T13	1		T148	1
valid_sources[0x6e]	947	1			T3	6		T26	176		T25	3
valid_sources[0x6f]	591	1			T3	11		T4	1		T24	1
valid_sources[0x70]	534	1			T3	7		T26	3		T135	1
valid_sources[0x71]	533	1			T3	8		T151	9		T50	1
valid_sources[0x72]	513	1			T3	9		T4	1		T149	1
valid_sources[0x73]	624	1			T3	6		T140	1		T8	2
valid_sources[0x74]	747	1			T3	4		T28	1		T8	1
valid_sources[0x75]	815	1			T3	14		T6	1		T25	1
valid_sources[0x76]	678	1			T3	2		T4	2		T8	2
valid_sources[0x77]	535	1			T3	7		T143	1		T27	10
valid_sources[0x78]	1134	1			T3	2		T4	1		T6	1
valid_sources[0x79]	570	1			T3	12		T28	1		T8	2
valid_sources[0x7a]	663	1			T3	1		T6	12		T8	3
valid_sources[0x7b]	516	1			T1	1		T3	13		T8	1
valid_sources[0x7c]	854	1			T3	9		T50	1		T8	2
valid_sources[0x7d]	679	1			T3	8		T140	2		T142	1
valid_sources[0x7e]	762	1			T3	10		T8	4		T26	8
valid_sources[0x7f]	1376	1			T3	9		T8	3		T26	64
valid_sources[0x80]	602	1			T3	4		T8	1		T26	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40618

1

T3

420

T4

8

T16

5

values[0x0]

all_enables

biggest_size

55702

1

T1

5

T3

609

T5

2

values[0x1]

all_enables

biggest_size

53701

1

T1

1

T3

667

T4

4