Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15956502

1

T1

11796

T2

1446

T3

1554

full_word

161286862

1

T1

117324

T2

311

T3

1728

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	177243034	1			T1	129120		T2	1757		T3	3282
auto[TlIntgErrCmd]	95	1			T101	5		T102	5		T103	8
auto[TlIntgErrData]	116	1			T101	7		T102	1		T103	6
auto[TlIntgErrBoth]	119	1			T101	8		T102	4		T103	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85610430

1

T1

64258

T2

894

T3

718

auto[1]

91632934

1

T1

64862

T2

863

T3

2564

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7816519	1			T1	5874		T2	726		T3	284
auto[TlIntgErrNone]	partial	auto[1]	8139679	1			T1	5922		T2	720		T3	1270
auto[TlIntgErrNone]	full_word	auto[0]	77793755	1			T1	58384		T2	168		T3	434
auto[TlIntgErrNone]	full_word	auto[1]	83493081	1			T1	58940		T2	143		T3	1294
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T101	3		T102	3		T103	4
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T101	2		T102	2		T103	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T124	1		T130	2		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T131	1		T132	2		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T101	5		T103	1		T124	1
auto[TlIntgErrData]	partial	auto[1]	53	1			T101	2		T103	5		T124	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T102	1		T124	1		T127	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T127	3		T131	1		T133	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T101	1		T102	2		T103	4
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T101	6		T102	2		T103	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T101	1		T124	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T129	1		T130	1		-	-