Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	767455	1			T4	1453		T14	5758		T15	24121
auto[1]	10680474	1			T1	35259		T5	42456		T9	9747
auto[2]	592327	1			T4	748		T14	5216		T15	20542
auto[3]	10431559	1			T1	35461		T5	42913		T9	9727

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13937953	1			T1	58236		T5	71413		T9	16214
auto[1]	2087113	1			T1	6035		T5	6661		T9	1519
auto[2]	2114390	1			T1	5850		T5	6664		T9	1583
auto[3]	4332359	1			T1	599		T5	631		T9	158

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8745399

1

T1

70718

T5

32

T9

19473

auto[1]

13726416

1

T1

2

T5

85337

T9

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	267063	1			T4	1219		T14	4755		T15	1
auto[0]	auto[0]	auto[1]	28220	1			T4	106		T14	487		T66	75
auto[0]	auto[0]	auto[2]	28341	1			T4	111		T14	472		T15	2
auto[0]	auto[0]	auto[3]	107622	1			T4	17		T14	44		T15	1
auto[0]	auto[1]	auto[0]	2960011	1			T1	28943		T5	11		T9	8110
auto[0]	auto[1]	auto[1]	320013	1			T1	3091		T5	2		T9	716
auto[0]	auto[1]	auto[2]	334142	1			T1	2905		T5	2		T9	845
auto[0]	auto[1]	auto[3]	486337	1			T1	320		T9	75		T10	172
auto[0]	auto[2]	auto[0]	187566	1			T4	593		T14	4343		T66	11
auto[0]	auto[2]	auto[1]	26525	1			T4	58		T14	435		T66	36
auto[0]	auto[2]	auto[2]	19046	1			T4	90		T14	394		T15	2
auto[0]	auto[2]	auto[3]	77852	1			T4	7		T14	44		T15	4
auto[0]	auto[3]	auto[0]	2815608	1			T1	29291		T5	10		T9	8104
auto[0]	auto[3]	auto[1]	314687	1			T1	2944		T5	3		T9	802
auto[0]	auto[3]	auto[2]	335688	1			T1	2945		T5	3		T9	738
auto[0]	auto[3]	auto[3]	436678	1			T1	279		T5	1		T9	83
auto[1]	auto[0]	auto[0]	11211	1			T15	818		T28	1		T136	799
auto[1]	auto[0]	auto[1]	50093	1			T15	3705		T136	3744		T137	5607
auto[1]	auto[0]	auto[2]	50469	1			T15	3578		T136	3754		T137	5573
auto[1]	auto[0]	auto[3]	224436	1			T15	16016		T71	4		T84	1
auto[1]	auto[1]	auto[0]	3842443	1			T5	35489		T15	133		T65	1
auto[1]	auto[1]	auto[1]	668945	1			T5	3134		T9	1		T15	3544
auto[1]	auto[1]	auto[2]	644284	1			T5	3498		T15	571		T91	8695
auto[1]	auto[1]	auto[3]	1424299	1			T5	320		T15	16167		T71	1
auto[1]	auto[2]	auto[0]	9620	1			T15	721		T28	1		T136	745
auto[1]	auto[2]	auto[1]	42810	1			T15	3210		T136	3393		T137	5054
auto[1]	auto[2]	auto[2]	41794	1			T15	3137		T8	1		T136	3148
auto[1]	auto[2]	auto[3]	187114	1			T15	13468		T136	13985		T137	20677
auto[1]	auto[3]	auto[0]	3844431	1			T1	2		T5	35903		T15	59
auto[1]	auto[3]	auto[1]	635820	1			T5	3522		T15	292		T91	8697
auto[1]	auto[3]	auto[2]	660626	1			T5	3161		T15	2974		T91	7887
auto[1]	auto[3]	auto[3]	1388021	1			T5	310		T15	13861		T91	35160