Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.22	100.00	68.87			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram.u_sramreqfifo	97.50	100.00	90.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	90.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.11	100.00	90.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.39			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.73	95.00	86.67			81.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00	100.00	u_sram_byte

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00	100.00	u_sram_byte

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.39			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.39			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=2,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

SCORE	LINE
97.50	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=104,Pass=0,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T13
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=2,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=104,Pass=0,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
97.50	90.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=104,Pass=0,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=2,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

SCORE	BRANCH
97.50	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	995577294	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	995577294	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	995577294	0	0
T1	4119790	428210	0	0
T2	268390	25414	0	0
T3	221165	34210	0	0
T4	770550	1326014	0	0
T5	1099095	339920	0	0
T9	1326745	137792	0	0
T10	393850	36310	0	0
T11	173790	0	0	0
T12	386120	16250	0	0
T13	332745	366	0	0
T14	0	16005	0	0
T16	0	427452	0	0
T17	0	5552	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4119790	4119505	0	0
T2	268390	267995	0	0
T3	221165	220480	0	0
T4	770550	770515	0	0
T5	1099095	1098745	0	0
T9	1326745	1326450	0	0
T10	393850	393530	0	0
T11	173790	173375	0	0
T12	386120	385835	0	0
T13	332745	332340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4119790	4119505	0	0
T2	268390	267995	0	0
T3	221165	220480	0	0
T4	770550	770515	0	0
T5	1099095	1098745	0	0
T9	1326745	1326450	0	0
T10	393850	393530	0	0
T11	173790	173375	0	0
T12	386120	385835	0	0
T13	332745	332340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4119790	4119505	0	0
T2	268390	267995	0	0
T3	221165	220480	0	0
T4	770550	770515	0	0
T5	1099095	1098745	0	0
T9	1326745	1326450	0	0
T10	393850	393530	0	0
T11	173790	173375	0	0
T12	386120	385835	0	0
T13	332745	332340	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	995577294	0	0
T1	4119790	428210	0	0
T2	268390	25414	0	0
T3	221165	34210	0	0
T4	770550	1326014	0	0
T5	1099095	339920	0	0
T9	1326745	137792	0	0
T10	393850	36310	0	0
T11	173790	0	0	0
T12	386120	16250	0	0
T13	332745	366	0	0
T14	0	16005	0	0
T16	0	427452	0	0
T17	0	5552	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		[UNR] this fifo can never be full, because transactions can drain into u_rspfifo
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1199836091	90102897	0	0
DepthKnown_A	1199836091	1199723334	0	0
RvalidKnown_A	1199836091	1199723334	0	0
WreadyKnown_A	1199836091	1199723334	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1199836091	90102897	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	90102897	0	0
T1	823958	70180	0	0
T2	53678	1614	0	0
T3	44233	0	0	0
T4	154110	44605	0	0
T5	219819	55749	0	0
T9	265349	22699	0	0
T10	78770	5890	0	0
T11	34758	0	0	0
T12	77224	2649	0	0
T13	66549	64	0	0
T16	0	54191	0	0
T17	0	2574	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	90102897	0	0
T1	823958	70180	0	0
T2	53678	1614	0	0
T3	44233	0	0	0
T4	154110	44605	0	0
T5	219819	55749	0	0
T9	265349	22699	0	0
T10	78770	5890	0	0
T11	34758	0	0	0
T12	77224	2649	0	0
T13	66549	64	0	0
T16	0	54191	0	0
T17	0	2574	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1199836091	17812422	0	0
DepthKnown_A	1199836091	1199723334	0	0
RvalidKnown_A	1199836091	1199723334	0	0
WreadyKnown_A	1199836091	1199723334	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1199836091	17812422	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	17812422	0	0
T1	823958	11844	0	0
T2	53678	1440	0	0
T3	44233	0	0	0
T4	154110	7742	0	0
T5	219819	9256	0	0
T9	265349	3772	0	0
T10	78770	1812	0	0
T11	34758	0	0	0
T12	77224	468	0	0
T13	66549	0	0	0
T14	0	16005	0	0
T16	0	5212	0	0
T17	0	404	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	17812422	0	0
T1	823958	11844	0	0
T2	53678	1440	0	0
T3	44233	0	0	0
T4	154110	7742	0	0
T5	219819	9256	0	0
T9	265349	3772	0	0
T10	78770	1812	0	0
T11	34758	0	0	0
T12	77224	468	0	0
T13	66549	0	0	0
T14	0	16005	0	0
T16	0	5212	0	0
T17	0	404	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_sync_fifo_a_size

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1199836091	362736259	0	0
DepthKnown_A	1199836091	1199723334	0	0
RvalidKnown_A	1199836091	1199723334	0	0
WreadyKnown_A	1199836091	1199723334	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1199836091	362736259	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	362736259	0	0
T1	823958	140964	0	0
T2	53678	9168	0	0
T3	44233	17105	0	0
T4	154110	567664	0	0
T5	219819	111897	0	0
T9	265349	45254	0	0
T10	78770	11812	0	0
T11	34758	0	0	0
T12	77224	5359	0	0
T13	66549	119	0	0
T16	0	158232	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	362736259	0	0
T1	823958	140964	0	0
T2	53678	9168	0	0
T3	44233	17105	0	0
T4	154110	567664	0	0
T5	219819	111897	0	0
T9	265349	45254	0	0
T10	78770	11812	0	0
T11	34758	0	0	0
T12	77224	5359	0	0
T13	66549	119	0	0
T16	0	158232	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T2,T3,T4
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1199836091	355479177	0	0
DepthKnown_A	1199836091	1199723334	0	0
RvalidKnown_A	1199836091	1199723334	0	0
WreadyKnown_A	1199836091	1199723334	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1199836091	355479177	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	355479177	0	0
T1	823958	135042	0	0
T2	53678	8448	0	0
T3	44233	17105	0	0
T4	154110	564372	0	0
T5	219819	107269	0	0
T9	265349	43368	0	0
T10	78770	10906	0	0
T11	34758	0	0	0
T12	77224	5125	0	0
T13	66549	119	0	0
T16	0	155626	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	1199723334	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199836091	355479177	0	0
T1	823958	135042	0	0
T2	53678	8448	0	0
T3	44233	17105	0	0
T4	154110	564372	0	0
T5	219819	107269	0	0
T9	265349	43368	0	0
T10	78770	10906	0	0
T11	34758	0	0	0
T12	77224	5125	0	0
T13	66549	119	0	0
T16	0	155626	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		[LOWRISK] we don't issue a req when it's under reset
1	1	Covered	T1,T2,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[UNR] when rspfifo is full, we don't expect to receive a request, as it's blocked at the req phase
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T2,T4,T13
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T14
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1199824663	169446539	0	0
DepthKnown_A	1199824663	1199711906	0	0
RvalidKnown_A	1199824663	1199711906	0	0
WreadyKnown_A	1199824663	1199711906	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1199824663	169446539	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199824663	169446539	0	0
T1	823958	70180	0	0
T2	53678	4744	0	0
T3	44233	0	0	0
T4	154110	141631	0	0
T5	219819	55749	0	0
T9	265349	22699	0	0
T10	78770	5890	0	0
T11	34758	0	0	0
T12	77224	2649	0	0
T13	66549	64	0	0
T16	0	54191	0	0
T17	0	2574	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199824663	1199711906	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199824663	1199711906	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199824663	1199711906	0	0
T1	823958	823901	0	0
T2	53678	53599	0	0
T3	44233	44096	0	0
T4	154110	154103	0	0
T5	219819	219749	0	0
T9	265349	265290	0	0
T10	78770	78706	0	0
T11	34758	34675	0	0
T12	77224	77167	0	0
T13	66549	66468	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1199824663	169446539	0	0
T1	823958	70180	0	0
T2	53678	4744	0	0
T3	44233	0	0	0
T4	154110	141631	0	0
T5	219819	55749	0	0
T9	265349	22699	0	0
T10	78770	5890	0	0
T11	34758	0	0	0
T12	77224	2649	0	0
T13	66549	64	0	0
T16	0	54191	0	0
T17	0	2574	0	0