Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1211585623	138668	0	0
ctrl_regwen_rd_A	1211585623	6663	0	0
exec_rd_A	1211585623	6188	0	0
exec_regwen_rd_A	1211585623	6083	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1211585623	138668	0	0
T3	44233	1455	0	0
T4	154110	0	0	0
T5	219819	0	0	0
T9	265349	0	0	0
T10	78770	0	0	0
T11	34758	0	0	0
T12	77224	0	0	0
T13	66549	0	0	0
T16	100495	0	0	0
T17	100898	0	0	0
T26	0	3648	0	0
T27	0	2775	0	0
T38	0	3185	0	0
T44	0	1647	0	0
T45	0	5662	0	0
T46	0	4867	0	0
T47	0	1406	0	0
T48	0	2131	0	0
T49	0	3941	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1211585623	6663	0	0
T104	49193	325	0	0
T105	48096	274	0	0
T106	0	437	0	0
T107	0	135	0	0
T108	0	191	0	0
T109	0	310	0	0
T110	0	166	0	0
T111	0	897	0	0
T112	0	425	0	0
T113	0	777	0	0
T114	377702	0	0	0
T115	33613	0	0	0
T116	235424	0	0	0
T117	735552	0	0	0
T118	676987	0	0	0
T119	68533	0	0	0
T120	227786	0	0	0
T121	949212	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1211585623	6188	0	0
T104	49193	356	0	0
T105	48096	296	0	0
T106	0	387	0	0
T107	0	114	0	0
T108	0	189	0	0
T109	0	343	0	0
T110	0	138	0	0
T111	0	712	0	0
T112	0	429	0	0
T113	0	664	0	0
T114	377702	0	0	0
T115	33613	0	0	0
T116	235424	0	0	0
T117	735552	0	0	0
T118	676987	0	0	0
T119	68533	0	0	0
T120	227786	0	0	0
T121	949212	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1211585623	6083	0	0
T104	49193	316	0	0
T105	48096	297	0	0
T106	0	403	0	0
T107	0	145	0	0
T108	0	162	0	0
T109	0	292	0	0
T110	0	216	0	0
T111	0	844	0	0
T112	0	352	0	0
T113	0	591	0	0
T114	377702	0	0	0
T115	33613	0	0	0
T116	235424	0	0	0
T117	735552	0	0	0
T118	676987	0	0	0
T119	68533	0	0	0
T120	227786	0	0	0
T121	949212	0	0	0