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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52


Total test records in report: 1036
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T794 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1388894328 Apr 28 03:05:52 PM PDT 24 Apr 28 03:09:53 PM PDT 24 9608662044 ps
T795 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3861247101 Apr 28 03:00:06 PM PDT 24 Apr 28 03:05:44 PM PDT 24 5556643837 ps
T796 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.903308546 Apr 28 03:03:32 PM PDT 24 Apr 28 03:03:50 PM PDT 24 1084239627 ps
T797 /workspace/coverage/default/44.sram_ctrl_alert_test.3572519980 Apr 28 03:06:12 PM PDT 24 Apr 28 03:06:13 PM PDT 24 16154335 ps
T798 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.94814470 Apr 28 03:04:21 PM PDT 24 Apr 28 03:04:45 PM PDT 24 2090542627 ps
T799 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2707765652 Apr 28 03:04:01 PM PDT 24 Apr 28 03:08:59 PM PDT 24 66535066463 ps
T800 /workspace/coverage/default/36.sram_ctrl_partial_access.2759944163 Apr 28 03:04:22 PM PDT 24 Apr 28 03:04:32 PM PDT 24 752360526 ps
T801 /workspace/coverage/default/37.sram_ctrl_executable.3962520499 Apr 28 03:04:31 PM PDT 24 Apr 28 03:23:38 PM PDT 24 51749761192 ps
T802 /workspace/coverage/default/6.sram_ctrl_max_throughput.3620899898 Apr 28 03:00:17 PM PDT 24 Apr 28 03:00:42 PM PDT 24 4973002884 ps
T803 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2387980727 Apr 28 03:06:16 PM PDT 24 Apr 28 03:10:04 PM PDT 24 35938746232 ps
T804 /workspace/coverage/default/18.sram_ctrl_lc_escalation.4156601116 Apr 28 03:01:15 PM PDT 24 Apr 28 03:01:23 PM PDT 24 1369650586 ps
T805 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2132666623 Apr 28 03:06:07 PM PDT 24 Apr 28 03:14:38 PM PDT 24 105841051020 ps
T806 /workspace/coverage/default/19.sram_ctrl_ram_cfg.2956940305 Apr 28 03:01:26 PM PDT 24 Apr 28 03:01:30 PM PDT 24 1418522074 ps
T807 /workspace/coverage/default/16.sram_ctrl_max_throughput.1602526567 Apr 28 03:01:02 PM PDT 24 Apr 28 03:01:12 PM PDT 24 2796873371 ps
T808 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4100491053 Apr 28 03:01:12 PM PDT 24 Apr 28 03:02:07 PM PDT 24 770057199 ps
T809 /workspace/coverage/default/32.sram_ctrl_smoke.38691684 Apr 28 03:03:21 PM PDT 24 Apr 28 03:04:16 PM PDT 24 791383843 ps
T810 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.938481852 Apr 28 03:00:20 PM PDT 24 Apr 28 03:02:50 PM PDT 24 16102977673 ps
T811 /workspace/coverage/default/41.sram_ctrl_lc_escalation.1572332465 Apr 28 03:05:30 PM PDT 24 Apr 28 03:06:09 PM PDT 24 7039093377 ps
T812 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3706851565 Apr 28 03:02:13 PM PDT 24 Apr 28 03:03:37 PM PDT 24 34560783340 ps
T813 /workspace/coverage/default/46.sram_ctrl_lc_escalation.3461267690 Apr 28 03:06:35 PM PDT 24 Apr 28 03:07:03 PM PDT 24 16444542916 ps
T814 /workspace/coverage/default/34.sram_ctrl_executable.2654568400 Apr 28 03:04:01 PM PDT 24 Apr 28 03:16:27 PM PDT 24 28394752382 ps
T815 /workspace/coverage/default/45.sram_ctrl_regwen.2079742737 Apr 28 03:06:21 PM PDT 24 Apr 28 03:21:33 PM PDT 24 19860462355 ps
T816 /workspace/coverage/default/12.sram_ctrl_max_throughput.132778133 Apr 28 03:00:24 PM PDT 24 Apr 28 03:00:37 PM PDT 24 676996270 ps
T817 /workspace/coverage/default/18.sram_ctrl_mem_partial_access.4117556095 Apr 28 03:01:13 PM PDT 24 Apr 28 03:02:27 PM PDT 24 2556382426 ps
T818 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2306550703 Apr 28 03:02:14 PM PDT 24 Apr 28 03:07:30 PM PDT 24 5163872975 ps
T819 /workspace/coverage/default/35.sram_ctrl_executable.172349447 Apr 28 03:04:10 PM PDT 24 Apr 28 03:15:03 PM PDT 24 12756209283 ps
T820 /workspace/coverage/default/24.sram_ctrl_partial_access.4016774217 Apr 28 03:02:10 PM PDT 24 Apr 28 03:02:17 PM PDT 24 2929983340 ps
T821 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1794573625 Apr 28 03:07:00 PM PDT 24 Apr 28 03:09:00 PM PDT 24 1628664016 ps
T822 /workspace/coverage/default/31.sram_ctrl_stress_all.2327772001 Apr 28 03:03:23 PM PDT 24 Apr 28 03:59:46 PM PDT 24 261207729558 ps
T823 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1011327277 Apr 28 03:07:13 PM PDT 24 Apr 28 03:14:34 PM PDT 24 38479967244 ps
T824 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2474976685 Apr 28 03:00:20 PM PDT 24 Apr 28 03:01:00 PM PDT 24 10285207887 ps
T825 /workspace/coverage/default/7.sram_ctrl_multiple_keys.1483508120 Apr 28 03:00:18 PM PDT 24 Apr 28 03:12:13 PM PDT 24 20913766191 ps
T826 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2269596584 Apr 28 03:00:20 PM PDT 24 Apr 28 03:00:41 PM PDT 24 2799276431 ps
T827 /workspace/coverage/default/38.sram_ctrl_alert_test.864475751 Apr 28 03:04:52 PM PDT 24 Apr 28 03:04:53 PM PDT 24 34442808 ps
T828 /workspace/coverage/default/40.sram_ctrl_partial_access.4094522344 Apr 28 03:05:15 PM PDT 24 Apr 28 03:05:31 PM PDT 24 3332283549 ps
T829 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.4096423820 Apr 28 03:01:56 PM PDT 24 Apr 28 03:05:58 PM PDT 24 10783502199 ps
T830 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.4100722747 Apr 28 03:00:02 PM PDT 24 Apr 28 03:05:08 PM PDT 24 22579922560 ps
T831 /workspace/coverage/default/29.sram_ctrl_max_throughput.2768291741 Apr 28 03:02:58 PM PDT 24 Apr 28 03:03:40 PM PDT 24 2573040398 ps
T832 /workspace/coverage/default/28.sram_ctrl_regwen.5684966 Apr 28 03:02:52 PM PDT 24 Apr 28 03:03:46 PM PDT 24 14630146872 ps
T833 /workspace/coverage/default/12.sram_ctrl_mem_walk.1812857399 Apr 28 03:00:30 PM PDT 24 Apr 28 03:02:34 PM PDT 24 2081745038 ps
T834 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.521723936 Apr 28 03:01:42 PM PDT 24 Apr 28 03:02:14 PM PDT 24 760804275 ps
T835 /workspace/coverage/default/3.sram_ctrl_alert_test.4141291419 Apr 28 03:00:07 PM PDT 24 Apr 28 03:00:10 PM PDT 24 17494196 ps
T836 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1013751837 Apr 28 03:01:06 PM PDT 24 Apr 28 03:01:17 PM PDT 24 344748468 ps
T837 /workspace/coverage/default/6.sram_ctrl_smoke.3840839144 Apr 28 03:00:13 PM PDT 24 Apr 28 03:00:20 PM PDT 24 416101682 ps
T838 /workspace/coverage/default/18.sram_ctrl_executable.131703887 Apr 28 03:01:14 PM PDT 24 Apr 28 03:18:33 PM PDT 24 16964497349 ps
T839 /workspace/coverage/default/36.sram_ctrl_smoke.1259745752 Apr 28 03:04:15 PM PDT 24 Apr 28 03:04:22 PM PDT 24 2235177424 ps
T840 /workspace/coverage/default/27.sram_ctrl_executable.3205068419 Apr 28 03:02:38 PM PDT 24 Apr 28 03:15:11 PM PDT 24 12110421614 ps
T841 /workspace/coverage/default/35.sram_ctrl_mem_walk.565287031 Apr 28 03:04:11 PM PDT 24 Apr 28 03:09:05 PM PDT 24 20662328713 ps
T842 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2238259382 Apr 28 03:04:27 PM PDT 24 Apr 28 03:11:33 PM PDT 24 8156107379 ps
T843 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1193957542 Apr 28 03:00:17 PM PDT 24 Apr 28 03:02:16 PM PDT 24 3678283922 ps
T844 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.3462194053 Apr 28 03:02:10 PM PDT 24 Apr 28 03:07:06 PM PDT 24 2146251790 ps
T845 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3989860925 Apr 28 03:04:13 PM PDT 24 Apr 28 03:08:38 PM PDT 24 15472015592 ps
T846 /workspace/coverage/default/13.sram_ctrl_multiple_keys.505006303 Apr 28 03:00:33 PM PDT 24 Apr 28 03:11:25 PM PDT 24 8925998836 ps
T847 /workspace/coverage/default/15.sram_ctrl_stress_all.2287124480 Apr 28 03:00:58 PM PDT 24 Apr 28 04:22:12 PM PDT 24 229706287736 ps
T848 /workspace/coverage/default/14.sram_ctrl_bijection.3685828770 Apr 28 03:00:46 PM PDT 24 Apr 28 03:35:35 PM PDT 24 160462600476 ps
T849 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2328509858 Apr 28 03:04:21 PM PDT 24 Apr 28 03:14:21 PM PDT 24 18048602609 ps
T850 /workspace/coverage/default/36.sram_ctrl_multiple_keys.2611675479 Apr 28 03:04:16 PM PDT 24 Apr 28 03:06:57 PM PDT 24 4487175976 ps
T851 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2041452581 Apr 28 03:02:11 PM PDT 24 Apr 28 03:02:55 PM PDT 24 746881882 ps
T852 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3148349692 Apr 28 03:00:07 PM PDT 24 Apr 28 03:05:34 PM PDT 24 6480141471 ps
T853 /workspace/coverage/default/15.sram_ctrl_mem_walk.105440843 Apr 28 03:00:58 PM PDT 24 Apr 28 03:03:42 PM PDT 24 49294908382 ps
T854 /workspace/coverage/default/46.sram_ctrl_alert_test.1934271782 Apr 28 03:06:39 PM PDT 24 Apr 28 03:06:41 PM PDT 24 16630790 ps
T855 /workspace/coverage/default/14.sram_ctrl_multiple_keys.1091757996 Apr 28 03:00:46 PM PDT 24 Apr 28 03:04:26 PM PDT 24 4472243171 ps
T856 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1620011749 Apr 28 03:04:13 PM PDT 24 Apr 28 03:19:51 PM PDT 24 46104378410 ps
T857 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2294557784 Apr 28 03:00:28 PM PDT 24 Apr 28 03:01:45 PM PDT 24 2970790922 ps
T858 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1920300896 Apr 28 03:06:05 PM PDT 24 Apr 28 03:06:49 PM PDT 24 14465446781 ps
T859 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.647422633 Apr 28 03:02:44 PM PDT 24 Apr 28 03:03:15 PM PDT 24 4765353674 ps
T860 /workspace/coverage/default/5.sram_ctrl_bijection.3850934430 Apr 28 03:00:07 PM PDT 24 Apr 28 03:24:01 PM PDT 24 507066779026 ps
T861 /workspace/coverage/default/34.sram_ctrl_bijection.4251900081 Apr 28 03:03:55 PM PDT 24 Apr 28 03:16:07 PM PDT 24 43292552142 ps
T862 /workspace/coverage/default/42.sram_ctrl_stress_all.2590934653 Apr 28 03:05:51 PM PDT 24 Apr 28 03:08:31 PM PDT 24 20113701529 ps
T863 /workspace/coverage/default/48.sram_ctrl_lc_escalation.1086415470 Apr 28 03:07:00 PM PDT 24 Apr 28 03:08:57 PM PDT 24 124402264627 ps
T864 /workspace/coverage/default/34.sram_ctrl_regwen.2256542309 Apr 28 03:04:06 PM PDT 24 Apr 28 03:33:11 PM PDT 24 5962331934 ps
T865 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.520261272 Apr 28 03:00:10 PM PDT 24 Apr 28 03:00:55 PM PDT 24 1748981110 ps
T866 /workspace/coverage/default/28.sram_ctrl_partial_access.1430034889 Apr 28 03:02:52 PM PDT 24 Apr 28 03:03:16 PM PDT 24 1530507580 ps
T867 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2010979082 Apr 28 03:07:12 PM PDT 24 Apr 28 03:17:29 PM PDT 24 128250105711 ps
T868 /workspace/coverage/default/40.sram_ctrl_stress_all.4071576501 Apr 28 03:05:28 PM PDT 24 Apr 28 04:21:22 PM PDT 24 277171937028 ps
T869 /workspace/coverage/default/5.sram_ctrl_regwen.208230846 Apr 28 03:00:10 PM PDT 24 Apr 28 03:10:50 PM PDT 24 23360494405 ps
T870 /workspace/coverage/default/37.sram_ctrl_smoke.2740635252 Apr 28 03:04:25 PM PDT 24 Apr 28 03:04:30 PM PDT 24 1379551107 ps
T871 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3038422010 Apr 28 03:00:13 PM PDT 24 Apr 28 03:00:40 PM PDT 24 3396000948 ps
T872 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2454147674 Apr 28 03:06:34 PM PDT 24 Apr 28 03:16:54 PM PDT 24 15054869275 ps
T873 /workspace/coverage/default/46.sram_ctrl_multiple_keys.2830362244 Apr 28 03:06:26 PM PDT 24 Apr 28 03:10:22 PM PDT 24 4267253308 ps
T874 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2713674822 Apr 28 03:00:10 PM PDT 24 Apr 28 03:08:35 PM PDT 24 66532278560 ps
T875 /workspace/coverage/default/38.sram_ctrl_lc_escalation.988075066 Apr 28 03:04:51 PM PDT 24 Apr 28 03:05:37 PM PDT 24 28415818377 ps
T876 /workspace/coverage/default/44.sram_ctrl_regwen.393793366 Apr 28 03:06:08 PM PDT 24 Apr 28 03:22:50 PM PDT 24 52203303809 ps
T877 /workspace/coverage/default/25.sram_ctrl_bijection.3361119265 Apr 28 03:02:14 PM PDT 24 Apr 28 03:31:54 PM PDT 24 106231391839 ps
T878 /workspace/coverage/default/18.sram_ctrl_max_throughput.2498968305 Apr 28 03:01:13 PM PDT 24 Apr 28 03:02:06 PM PDT 24 764545789 ps
T879 /workspace/coverage/default/35.sram_ctrl_ram_cfg.3611873738 Apr 28 03:04:13 PM PDT 24 Apr 28 03:04:16 PM PDT 24 359442140 ps
T880 /workspace/coverage/default/23.sram_ctrl_mem_walk.2320739360 Apr 28 03:02:13 PM PDT 24 Apr 28 03:06:29 PM PDT 24 43752321465 ps
T881 /workspace/coverage/default/43.sram_ctrl_ram_cfg.1986487284 Apr 28 03:05:57 PM PDT 24 Apr 28 03:06:01 PM PDT 24 681474051 ps
T882 /workspace/coverage/default/45.sram_ctrl_partial_access.792304695 Apr 28 03:06:16 PM PDT 24 Apr 28 03:08:36 PM PDT 24 3449167778 ps
T883 /workspace/coverage/default/38.sram_ctrl_partial_access.4202326780 Apr 28 03:04:42 PM PDT 24 Apr 28 03:04:54 PM PDT 24 1493425226 ps
T884 /workspace/coverage/default/4.sram_ctrl_ram_cfg.904666215 Apr 28 03:00:07 PM PDT 24 Apr 28 03:00:12 PM PDT 24 354357163 ps
T885 /workspace/coverage/default/45.sram_ctrl_bijection.408416445 Apr 28 03:06:12 PM PDT 24 Apr 28 03:39:18 PM PDT 24 838387538308 ps
T886 /workspace/coverage/default/29.sram_ctrl_ram_cfg.3340414127 Apr 28 03:03:04 PM PDT 24 Apr 28 03:03:08 PM PDT 24 1356613506 ps
T887 /workspace/coverage/default/13.sram_ctrl_ram_cfg.2820666830 Apr 28 03:00:44 PM PDT 24 Apr 28 03:00:53 PM PDT 24 2403839602 ps
T888 /workspace/coverage/default/31.sram_ctrl_bijection.2211133534 Apr 28 03:03:16 PM PDT 24 Apr 28 03:40:22 PM PDT 24 30499991083 ps
T889 /workspace/coverage/default/18.sram_ctrl_ram_cfg.485975088 Apr 28 03:01:17 PM PDT 24 Apr 28 03:01:21 PM PDT 24 364008344 ps
T890 /workspace/coverage/default/41.sram_ctrl_smoke.544825366 Apr 28 03:05:31 PM PDT 24 Apr 28 03:05:53 PM PDT 24 6171844248 ps
T891 /workspace/coverage/default/37.sram_ctrl_ram_cfg.358286165 Apr 28 03:04:31 PM PDT 24 Apr 28 03:04:35 PM PDT 24 692287341 ps
T892 /workspace/coverage/default/16.sram_ctrl_partial_access.925144003 Apr 28 03:01:00 PM PDT 24 Apr 28 03:01:27 PM PDT 24 1729104575 ps
T893 /workspace/coverage/default/27.sram_ctrl_max_throughput.3515845371 Apr 28 03:02:39 PM PDT 24 Apr 28 03:02:46 PM PDT 24 3167911480 ps
T894 /workspace/coverage/default/32.sram_ctrl_lc_escalation.3580702722 Apr 28 03:03:28 PM PDT 24 Apr 28 03:04:01 PM PDT 24 25490570246 ps
T895 /workspace/coverage/default/13.sram_ctrl_alert_test.1198738363 Apr 28 03:00:45 PM PDT 24 Apr 28 03:00:49 PM PDT 24 23758552 ps
T896 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.714146485 Apr 28 03:00:44 PM PDT 24 Apr 28 03:03:22 PM PDT 24 9501228029 ps
T897 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.40039902 Apr 28 03:03:43 PM PDT 24 Apr 28 03:04:00 PM PDT 24 1499411877 ps
T898 /workspace/coverage/default/25.sram_ctrl_alert_test.785627232 Apr 28 03:02:20 PM PDT 24 Apr 28 03:02:21 PM PDT 24 34703249 ps
T899 /workspace/coverage/default/5.sram_ctrl_ram_cfg.387639586 Apr 28 03:00:20 PM PDT 24 Apr 28 03:00:29 PM PDT 24 757815650 ps
T900 /workspace/coverage/default/34.sram_ctrl_lc_escalation.1154602913 Apr 28 03:04:02 PM PDT 24 Apr 28 03:04:54 PM PDT 24 29067227031 ps
T901 /workspace/coverage/default/20.sram_ctrl_mem_walk.1847324108 Apr 28 03:01:37 PM PDT 24 Apr 28 03:03:35 PM PDT 24 2063195010 ps
T902 /workspace/coverage/default/25.sram_ctrl_mem_walk.2865009414 Apr 28 03:02:23 PM PDT 24 Apr 28 03:04:54 PM PDT 24 21480474051 ps
T903 /workspace/coverage/default/15.sram_ctrl_multiple_keys.241263070 Apr 28 03:00:55 PM PDT 24 Apr 28 03:06:52 PM PDT 24 8554567563 ps
T904 /workspace/coverage/default/3.sram_ctrl_executable.2713877956 Apr 28 03:00:07 PM PDT 24 Apr 28 03:31:18 PM PDT 24 17909061430 ps
T905 /workspace/coverage/default/45.sram_ctrl_executable.1822896628 Apr 28 03:06:23 PM PDT 24 Apr 28 03:11:12 PM PDT 24 8217712802 ps
T906 /workspace/coverage/default/43.sram_ctrl_multiple_keys.103010927 Apr 28 03:05:54 PM PDT 24 Apr 28 03:20:47 PM PDT 24 7260301563 ps
T907 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3528102158 Apr 28 03:06:40 PM PDT 24 Apr 28 03:10:35 PM PDT 24 14883903559 ps
T32 /workspace/coverage/default/1.sram_ctrl_sec_cm.3540947334 Apr 28 03:00:10 PM PDT 24 Apr 28 03:00:13 PM PDT 24 860587656 ps
T908 /workspace/coverage/default/39.sram_ctrl_stress_all.521888077 Apr 28 03:05:09 PM PDT 24 Apr 28 04:17:02 PM PDT 24 196699494429 ps
T909 /workspace/coverage/default/8.sram_ctrl_alert_test.4122794382 Apr 28 03:00:17 PM PDT 24 Apr 28 03:00:24 PM PDT 24 13323232 ps
T910 /workspace/coverage/default/48.sram_ctrl_stress_all.1881811543 Apr 28 03:07:04 PM PDT 24 Apr 28 05:16:43 PM PDT 24 108376820302 ps
T911 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.4201636163 Apr 28 03:05:37 PM PDT 24 Apr 28 03:07:59 PM PDT 24 4453117202 ps
T912 /workspace/coverage/default/44.sram_ctrl_stress_all.2357180141 Apr 28 03:06:12 PM PDT 24 Apr 28 03:07:11 PM PDT 24 17884069662 ps
T913 /workspace/coverage/default/43.sram_ctrl_stress_all.3948438075 Apr 28 03:06:03 PM PDT 24 Apr 28 05:21:28 PM PDT 24 116797967222 ps
T914 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.384451447 Apr 28 03:00:59 PM PDT 24 Apr 28 03:08:56 PM PDT 24 90196813143 ps
T915 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.241207710 Apr 28 03:00:07 PM PDT 24 Apr 28 03:04:01 PM PDT 24 8023632435 ps
T916 /workspace/coverage/default/42.sram_ctrl_mem_walk.2217622138 Apr 28 03:05:55 PM PDT 24 Apr 28 03:11:21 PM PDT 24 21308132765 ps
T917 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2647073938 Apr 28 03:01:07 PM PDT 24 Apr 28 03:02:14 PM PDT 24 1574009190 ps
T918 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3228794466 Apr 28 03:06:51 PM PDT 24 Apr 28 03:09:27 PM PDT 24 48327138195 ps
T919 /workspace/coverage/default/32.sram_ctrl_multiple_keys.2072230787 Apr 28 03:03:32 PM PDT 24 Apr 28 03:19:19 PM PDT 24 32388191599 ps
T920 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.325961961 Apr 28 03:04:05 PM PDT 24 Apr 28 03:05:25 PM PDT 24 10450850533 ps
T921 /workspace/coverage/default/33.sram_ctrl_partial_access.276907625 Apr 28 03:03:39 PM PDT 24 Apr 28 03:05:25 PM PDT 24 1009175712 ps
T922 /workspace/coverage/default/42.sram_ctrl_lc_escalation.2624012481 Apr 28 03:05:42 PM PDT 24 Apr 28 03:06:27 PM PDT 24 33423605345 ps
T923 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2374827887 Apr 28 03:04:01 PM PDT 24 Apr 28 03:07:09 PM PDT 24 6771302223 ps
T924 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.969405403 Apr 28 03:06:59 PM PDT 24 Apr 28 03:13:15 PM PDT 24 14950395364 ps
T925 /workspace/coverage/default/27.sram_ctrl_stress_all.714777669 Apr 28 03:02:40 PM PDT 24 Apr 28 03:54:35 PM PDT 24 57985966077 ps
T926 /workspace/coverage/default/1.sram_ctrl_multiple_keys.2444578436 Apr 28 02:59:59 PM PDT 24 Apr 28 03:14:45 PM PDT 24 16680306957 ps
T927 /workspace/coverage/default/35.sram_ctrl_smoke.2928568040 Apr 28 03:04:11 PM PDT 24 Apr 28 03:05:04 PM PDT 24 5775509420 ps
T928 /workspace/coverage/default/14.sram_ctrl_executable.1995669743 Apr 28 03:00:47 PM PDT 24 Apr 28 03:16:24 PM PDT 24 93184780700 ps
T929 /workspace/coverage/default/27.sram_ctrl_alert_test.3311363831 Apr 28 03:02:44 PM PDT 24 Apr 28 03:02:46 PM PDT 24 26399394 ps
T930 /workspace/coverage/default/19.sram_ctrl_mem_walk.3238048378 Apr 28 03:01:26 PM PDT 24 Apr 28 03:03:54 PM PDT 24 40503310724 ps
T931 /workspace/coverage/default/28.sram_ctrl_mem_walk.2016556819 Apr 28 03:02:52 PM PDT 24 Apr 28 03:08:10 PM PDT 24 93830801942 ps
T932 /workspace/coverage/default/41.sram_ctrl_regwen.2606799346 Apr 28 03:05:29 PM PDT 24 Apr 28 03:22:57 PM PDT 24 45551506789 ps
T933 /workspace/coverage/default/38.sram_ctrl_stress_all.2529053696 Apr 28 03:04:52 PM PDT 24 Apr 28 05:02:16 PM PDT 24 342623177456 ps
T934 /workspace/coverage/default/38.sram_ctrl_max_throughput.203654429 Apr 28 03:04:48 PM PDT 24 Apr 28 03:05:49 PM PDT 24 745048493 ps
T935 /workspace/coverage/default/25.sram_ctrl_ram_cfg.72592219 Apr 28 03:02:21 PM PDT 24 Apr 28 03:02:24 PM PDT 24 911890013 ps
T936 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3688408851 Apr 28 03:02:57 PM PDT 24 Apr 28 03:09:12 PM PDT 24 118697169092 ps
T937 /workspace/coverage/default/47.sram_ctrl_executable.3035468757 Apr 28 03:06:44 PM PDT 24 Apr 28 03:45:01 PM PDT 24 186964070468 ps
T938 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2661262913 Apr 28 03:06:02 PM PDT 24 Apr 28 03:09:43 PM PDT 24 21092328930 ps
T939 /workspace/coverage/default/48.sram_ctrl_bijection.2422123365 Apr 28 03:06:54 PM PDT 24 Apr 28 03:24:59 PM PDT 24 42352853811 ps
T940 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1602187282 Apr 28 03:07:00 PM PDT 24 Apr 28 03:26:47 PM PDT 24 25895265040 ps
T941 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3869874963 Apr 28 03:03:28 PM PDT 24 Apr 28 03:03:39 PM PDT 24 693483896 ps
T942 /workspace/coverage/default/32.sram_ctrl_partial_access.735757763 Apr 28 03:03:27 PM PDT 24 Apr 28 03:05:08 PM PDT 24 839970917 ps
T943 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3684897600 Apr 28 03:07:04 PM PDT 24 Apr 28 03:09:37 PM PDT 24 7639418468 ps
T85 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3561917138 Apr 28 12:46:39 PM PDT 24 Apr 28 12:46:41 PM PDT 24 18007956 ps
T944 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3977154630 Apr 28 12:46:26 PM PDT 24 Apr 28 12:46:31 PM PDT 24 361308431 ps
T86 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.338931918 Apr 28 12:46:40 PM PDT 24 Apr 28 12:46:42 PM PDT 24 19037046 ps
T98 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.360850629 Apr 28 12:46:38 PM PDT 24 Apr 28 12:46:40 PM PDT 24 25259407 ps
T99 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2957186661 Apr 28 12:46:25 PM PDT 24 Apr 28 12:46:28 PM PDT 24 28206613 ps
T945 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1350600355 Apr 28 12:46:42 PM PDT 24 Apr 28 12:46:48 PM PDT 24 6895060776 ps
T54 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2819729894 Apr 28 12:46:29 PM PDT 24 Apr 28 12:47:24 PM PDT 24 32128234138 ps
T946 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3033724400 Apr 28 12:46:52 PM PDT 24 Apr 28 12:46:57 PM PDT 24 3138065512 ps
T947 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3952808926 Apr 28 12:46:42 PM PDT 24 Apr 28 12:46:47 PM PDT 24 1428273649 ps
T948 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2526610625 Apr 28 12:46:30 PM PDT 24 Apr 28 12:46:33 PM PDT 24 111932274 ps
T55 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3579986399 Apr 28 12:46:30 PM PDT 24 Apr 28 12:46:31 PM PDT 24 19988057 ps
T87 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2057851237 Apr 28 12:46:43 PM PDT 24 Apr 28 12:46:44 PM PDT 24 14587933 ps
T88 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.628848148 Apr 28 12:46:31 PM PDT 24 Apr 28 12:46:32 PM PDT 24 75215304 ps
T101 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3334743476 Apr 28 12:47:01 PM PDT 24 Apr 28 12:47:05 PM PDT 24 199719404 ps
T56 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2117079868 Apr 28 12:46:28 PM PDT 24 Apr 28 12:46:56 PM PDT 24 4125780831 ps
T102 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.329527761 Apr 28 12:46:30 PM PDT 24 Apr 28 12:46:32 PM PDT 24 235844258 ps
T103 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1024678426 Apr 28 12:46:27 PM PDT 24 Apr 28 12:46:30 PM PDT 24 345353694 ps
T949 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3739967066 Apr 28 12:46:29 PM PDT 24 Apr 28 12:46:34 PM PDT 24 242767236 ps
T950 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3822205536 Apr 28 12:46:58 PM PDT 24 Apr 28 12:47:02 PM PDT 24 49057707 ps
T100 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3569362380 Apr 28 12:46:19 PM PDT 24 Apr 28 12:46:21 PM PDT 24 41920410 ps
T124 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1596986449 Apr 28 12:46:39 PM PDT 24 Apr 28 12:46:42 PM PDT 24 396506977 ps
T89 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.95446531 Apr 28 12:46:25 PM PDT 24 Apr 28 12:47:19 PM PDT 24 11790387881 ps
T951 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2186761620 Apr 28 12:46:25 PM PDT 24 Apr 28 12:46:30 PM PDT 24 544913171 ps
T952 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.856125688 Apr 28 12:46:28 PM PDT 24 Apr 28 12:46:32 PM PDT 24 355903426 ps
T953 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.721000290 Apr 28 12:46:24 PM PDT 24 Apr 28 12:46:27 PM PDT 24 831383119 ps
T954 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1792990981 Apr 28 12:46:40 PM PDT 24 Apr 28 12:46:44 PM PDT 24 679122817 ps
T57 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4203046083 Apr 28 12:46:39 PM PDT 24 Apr 28 12:47:07 PM PDT 24 3709645632 ps
T90 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2783857723 Apr 28 12:46:30 PM PDT 24 Apr 28 12:46:31 PM PDT 24 41244250 ps
T127 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2854597590 Apr 28 12:46:31 PM PDT 24 Apr 28 12:46:34 PM PDT 24 688623349 ps
T58 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1215164092 Apr 28 12:46:42 PM PDT 24 Apr 28 12:46:44 PM PDT 24 136327153 ps
T59 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.205421378 Apr 28 12:46:58 PM PDT 24 Apr 28 12:46:59 PM PDT 24 16141460 ps
T60 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2299684225 Apr 28 12:46:34 PM PDT 24 Apr 28 12:47:06 PM PDT 24 17514967171 ps
T61 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.59336602 Apr 28 12:46:28 PM PDT 24 Apr 28 12:46:29 PM PDT 24 31761857 ps
T955 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2296050934 Apr 28 12:46:59 PM PDT 24 Apr 28 12:47:01 PM PDT 24 473092265 ps
T956 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1134370801 Apr 28 12:46:51 PM PDT 24 Apr 28 12:46:55 PM PDT 24 361621773 ps
T62 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.426772305 Apr 28 12:46:56 PM PDT 24 Apr 28 12:46:57 PM PDT 24 12582505 ps
T957 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2028098217 Apr 28 12:46:57 PM PDT 24 Apr 28 12:47:02 PM PDT 24 369024065 ps
T63 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4072090255 Apr 28 12:46:28 PM PDT 24 Apr 28 12:46:30 PM PDT 24 27045071 ps
T958 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.666929546 Apr 28 12:46:42 PM PDT 24 Apr 28 12:46:48 PM PDT 24 5835662707 ps
T959 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.88778474 Apr 28 12:46:28 PM PDT 24 Apr 28 12:46:29 PM PDT 24 17125844 ps
T125 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2498941600 Apr 28 12:46:58 PM PDT 24 Apr 28 12:47:00 PM PDT 24 363895125 ps
T78 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.363409368 Apr 28 12:46:32 PM PDT 24 Apr 28 12:47:25 PM PDT 24 41446721951 ps
T129 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3184293469 Apr 28 12:46:36 PM PDT 24 Apr 28 12:46:39 PM PDT 24 1031892939 ps
T960 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3265554285 Apr 28 12:46:52 PM PDT 24 Apr 28 12:46:54 PM PDT 24 25519198 ps
T961 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3235941777 Apr 28 12:46:27 PM PDT 24 Apr 28 12:46:30 PM PDT 24 30688978 ps
T962 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1290413419 Apr 28 12:46:49 PM PDT 24 Apr 28 12:46:51 PM PDT 24 40182892 ps
T67 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2699290123 Apr 28 12:46:25 PM PDT 24 Apr 28 12:46:27 PM PDT 24 20756913 ps
T963 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3858015187 Apr 28 12:46:32 PM PDT 24 Apr 28 12:46:33 PM PDT 24 16712059 ps
T68 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2060675352 Apr 28 12:46:33 PM PDT 24 Apr 28 12:46:34 PM PDT 24 23263593 ps
T964 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3439686315 Apr 28 12:46:32 PM PDT 24 Apr 28 12:46:36 PM PDT 24 348008009 ps
T126 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.171511194 Apr 28 12:46:28 PM PDT 24 Apr 28 12:46:30 PM PDT 24 129629965 ps
T69 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2058530606 Apr 28 12:46:40 PM PDT 24 Apr 28 12:46:41 PM PDT 24 15811001 ps
T965 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2599664782 Apr 28 12:46:40 PM PDT 24 Apr 28 12:46:43 PM PDT 24 85519711 ps
T966 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.393945923 Apr 28 12:46:53 PM PDT 24 Apr 28 12:46:55 PM PDT 24 19902546 ps
T967 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4174419405 Apr 28 12:46:27 PM PDT 24 Apr 28 12:46:30 PM PDT 24 187707085 ps
T968 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4147229541 Apr 28 12:46:38 PM PDT 24 Apr 28 12:46:39 PM PDT 24 38496037 ps
T70 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2946192871 Apr 28 12:46:28 PM PDT 24 Apr 28 12:46:30 PM PDT 24 26823987 ps
T131 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2038802758 Apr 28 12:46:58 PM PDT 24 Apr 28 12:47:01 PM PDT 24 261865677 ps
T79 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.177146141 Apr 28 12:46:46 PM PDT 24 Apr 28 12:47:36 PM PDT 24 7423182748 ps
T969 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2523221492 Apr 28 12:46:39 PM PDT 24 Apr 28 12:46:43 PM PDT 24 138904774 ps
T80 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.956505346 Apr 28 12:46:37 PM PDT 24 Apr 28 12:47:50 PM PDT 24 100768992944 ps
T970 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.791136347 Apr 28 12:46:32 PM PDT 24 Apr 28 12:46:36 PM PDT 24 41130377 ps
T81 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2749437598 Apr 28 12:46:19 PM PDT 24 Apr 28 12:47:12 PM PDT 24 7074077752 ps
T971 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1054567997 Apr 28 12:47:00 PM PDT 24 Apr 28 12:47:03 PM PDT 24 301121274 ps
T972 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3349880666 Apr 28 12:46:36 PM PDT 24 Apr 28 12:46:38 PM PDT 24 19401532 ps
T973 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3682619248 Apr 28 12:46:32 PM PDT 24 Apr 28 12:46:36 PM PDT 24 372556834 ps
T974 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1452046368 Apr 28 12:46:34 PM PDT 24 Apr 28 12:46:37 PM PDT 24 106322769 ps
T975 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1103697274 Apr 28 12:47:00 PM PDT 24 Apr 28 12:47:03 PM PDT 24 2005279206 ps
T82 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1360276501 Apr 28 12:46:25 PM PDT 24 Apr 28 12:46:56 PM PDT 24 7409725137 ps
T976 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1200752021 Apr 28 12:46:49 PM PDT 24 Apr 28 12:46:51 PM PDT 24 87013612 ps
T977 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2927105600 Apr 28 12:46:57 PM PDT 24 Apr 28 12:47:01 PM PDT 24 375292760 ps
T978 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2243261363 Apr 28 12:46:24 PM PDT 24 Apr 28 12:46:25 PM PDT 24 140495960 ps
T979 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1861819305 Apr 28 12:46:30 PM PDT 24 Apr 28 12:46:33 PM PDT 24 178468779 ps
T980 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2128336103 Apr 28 12:46:57 PM PDT 24 Apr 28 12:46:58 PM PDT 24 53328353 ps
T981 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2568573746 Apr 28 12:46:38 PM PDT 24 Apr 28 12:46:41 PM PDT 24 62471995 ps
T83 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2202496726 Apr 28 12:46:28 PM PDT 24 Apr 28 12:46:29 PM PDT 24 11886934 ps
T982 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3580557785 Apr 28 12:46:34 PM PDT 24 Apr 28 12:47:06 PM PDT 24 14765459155 ps
T983 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2373902122 Apr 28 12:46:31 PM PDT 24 Apr 28 12:46:32 PM PDT 24 122346550 ps
T984 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1844703252 Apr 28 12:46:37 PM PDT 24 Apr 28 12:46:40 PM PDT 24 271844191 ps
T985 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3359656045 Apr 28 12:46:24 PM PDT 24 Apr 28 12:46:26 PM PDT 24 40678523 ps
T986 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4131922297 Apr 28 12:46:44 PM PDT 24 Apr 28 12:46:46 PM PDT 24 188754601 ps
T987 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.690862636 Apr 28 12:46:30 PM PDT 24 Apr 28 12:46:31 PM PDT 24 32134397 ps
T130 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2612575433 Apr 28 12:46:39 PM PDT 24 Apr 28 12:46:42 PM PDT 24 391124015 ps
T988 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3707766155 Apr 28 12:46:42 PM PDT 24 Apr 28 12:46:46 PM PDT 24 2685261110 ps
T989 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.61428871 Apr 28 12:46:26 PM PDT 24 Apr 28 12:46:31 PM PDT 24 947519194 ps
T990 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2774441132 Apr 28 12:46:29 PM PDT 24 Apr 28 12:46:35 PM PDT 24 538600816 ps
T991 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1780226674 Apr 28 12:47:01 PM PDT 24 Apr 28 12:47:02 PM PDT 24 26947500 ps
T992 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2968581872 Apr 28 12:46:49 PM PDT 24 Apr 28 12:47:16 PM PDT 24 6482554010 ps
T993 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1517447581 Apr 28 12:46:50 PM PDT 24 Apr 28 12:46:52 PM PDT 24 11881577 ps
T994 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2470216931 Apr 28 12:46:39 PM PDT 24 Apr 28 12:46:44 PM PDT 24 347069556 ps
T995 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.153457884 Apr 28 12:46:52 PM PDT 24 Apr 28 12:46:57 PM PDT 24 369747953 ps
T996 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3068393446 Apr 28 12:46:40 PM PDT 24 Apr 28 12:46:42 PM PDT 24 33514246 ps
T997 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1273317593 Apr 28 12:47:01 PM PDT 24 Apr 28 12:47:29 PM PDT 24 7718491340 ps
T998 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.378978897 Apr 28 12:47:00 PM PDT 24 Apr 28 12:47:04 PM PDT 24 76510020 ps
T999 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3582106636 Apr 28 12:46:35 PM PDT 24 Apr 28 12:47:32 PM PDT 24 29383119033 ps
T128 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2358074927 Apr 28 12:46:50 PM PDT 24 Apr 28 12:46:53 PM PDT 24 1147494145 ps
T1000 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2782844528 Apr 28 12:46:28 PM PDT 24 Apr 28 12:47:20 PM PDT 24 14707938781 ps
T1001 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.37733744 Apr 28 12:46:37 PM PDT 24 Apr 28 12:47:31 PM PDT 24 32127531378 ps
T1002 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.368584602 Apr 28 12:46:48 PM PDT 24 Apr 28 12:46:51 PM PDT 24 157870462 ps
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