Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16020222	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

155846091

1

T2

142179

T4

1065

T6

5202

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	84566253	1			T2	77999		T4	2977		T6	2626
values[0x0]	42045430	1			T2	37821		T4	1018		T6	1292
values[0x1]	45254630	1			T2	40611		T4	1991		T6	1284

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8146499	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

163719814

1

T2

149221

T4

3507

T6

5202

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1021916	1			T2	625		T4	31		T6	3
valid_sources[0x01]	539474	1			T2	661		T4	20		T6	10
valid_sources[0x02]	530532	1			T2	654		T4	34		T6	11
valid_sources[0x03]	554692	1			T2	569		T4	32		T6	15
valid_sources[0x04]	594701	1			T2	600		T4	25		T6	19
valid_sources[0x05]	608083	1			T2	623		T4	22		T6	13
valid_sources[0x06]	540141	1			T2	579		T4	31		T6	29
valid_sources[0x07]	573258	1			T2	595		T4	14		T6	3
valid_sources[0x08]	1026925	1			T2	666		T4	19		T6	20
valid_sources[0x09]	559516	1			T2	560		T4	25		T6	22
valid_sources[0x0a]	658365	1			T2	594		T4	23		T6	6
valid_sources[0x0b]	530214	1			T2	599		T4	19		T6	14
valid_sources[0x0c]	604174	1			T2	562		T4	39		T6	10
valid_sources[0x0d]	1501193	1			T2	603		T4	28		T6	15
valid_sources[0x0e]	582344	1			T2	600		T4	22		T6	23
valid_sources[0x0f]	557817	1			T2	601		T4	24		T6	20
valid_sources[0x10]	573603	1			T2	638		T4	22		T6	21
valid_sources[0x11]	568218	1			T2	631		T4	26		T6	17
valid_sources[0x12]	579115	1			T2	603		T4	16		T6	16
valid_sources[0x13]	1846030	1			T2	627		T4	23		T6	12
valid_sources[0x14]	2047953	1			T2	569		T4	19		T6	31
valid_sources[0x15]	552716	1			T2	585		T4	27		T6	30
valid_sources[0x16]	607887	1			T2	657		T4	27		T6	13
valid_sources[0x17]	588205	1			T2	540		T4	25		T6	44
valid_sources[0x18]	609260	1			T2	648		T4	24		T6	10
valid_sources[0x19]	535214	1			T2	627		T4	21		T6	12
valid_sources[0x1a]	594875	1			T2	580		T4	17		T6	9
valid_sources[0x1b]	543748	1			T2	580		T4	22		T6	24
valid_sources[0x1c]	576179	1			T2	659		T4	21		T6	25
valid_sources[0x1d]	584313	1			T2	604		T4	26		T6	29
valid_sources[0x1e]	847976	1			T2	602		T4	30		T6	26
valid_sources[0x1f]	550857	1			T2	594		T4	21		T6	27
valid_sources[0x20]	621890	1			T2	559		T4	27		T6	26
valid_sources[0x21]	558136	1			T2	586		T4	18		T6	14
valid_sources[0x22]	608456	1			T2	630		T4	16		T6	19
valid_sources[0x23]	558767	1			T2	577		T4	23		T6	21
valid_sources[0x24]	681241	1			T2	664		T4	20		T6	4
valid_sources[0x25]	568817	1			T2	691		T4	32		T6	4
valid_sources[0x26]	562914	1			T2	600		T4	20		T6	14
valid_sources[0x27]	536473	1			T2	617		T4	17		T6	23
valid_sources[0x28]	537425	1			T2	653		T4	25		T6	15
valid_sources[0x29]	535456	1			T2	620		T4	18		T6	20
valid_sources[0x2a]	665952	1			T2	623		T4	26		T6	22
valid_sources[0x2b]	573312	1			T2	598		T4	30		T6	43
valid_sources[0x2c]	580565	1			T2	517		T4	32		T6	6
valid_sources[0x2d]	559297	1			T2	617		T4	23		T6	20
valid_sources[0x2e]	569033	1			T2	595		T4	16		T6	15
valid_sources[0x2f]	576584	1			T2	640		T4	27		T6	17
valid_sources[0x30]	556839	1			T2	579		T4	18		T6	34
valid_sources[0x31]	567880	1			T2	715		T4	21		T6	11
valid_sources[0x32]	674631	1			T2	634		T4	34		T6	19
valid_sources[0x33]	574544	1			T2	581		T4	23		T6	10
valid_sources[0x34]	618614	1			T2	642		T4	23		T6	9
valid_sources[0x35]	566462	1			T2	590		T4	28		T6	35
valid_sources[0x36]	540709	1			T2	648		T4	23		T6	24
valid_sources[0x37]	556317	1			T2	599		T4	18		T6	3
valid_sources[0x38]	540521	1			T2	620		T4	19		T6	34
valid_sources[0x39]	3285571	1			T2	600		T4	19		T6	20
valid_sources[0x3a]	595238	1			T2	583		T4	25		T6	9
valid_sources[0x3b]	569072	1			T2	656		T4	24		T6	8
valid_sources[0x3c]	548549	1			T2	665		T4	22		T6	15
valid_sources[0x3d]	2488753	1			T2	607		T4	17		T6	16
valid_sources[0x3e]	570539	1			T2	637		T4	15		T6	39
valid_sources[0x3f]	541671	1			T2	626		T4	25		T6	32
valid_sources[0x40]	569402	1			T2	551		T4	21		T6	10
valid_sources[0x41]	612911	1			T2	585		T4	37		T6	25
valid_sources[0x42]	589020	1			T2	625		T4	31		T6	10
valid_sources[0x43]	586062	1			T2	605		T4	19		T6	20
valid_sources[0x44]	616266	1			T2	630		T4	23		T6	18
valid_sources[0x45]	1673013	1			T2	662		T4	32		T6	10
valid_sources[0x46]	627889	1			T2	613		T4	23		T6	8
valid_sources[0x47]	589785	1			T2	628		T4	23		T6	20
valid_sources[0x48]	588200	1			T2	665		T4	37		T6	27
valid_sources[0x49]	555251	1			T2	608		T4	11		T6	10
valid_sources[0x4a]	534626	1			T2	615		T4	40		T6	19
valid_sources[0x4b]	528259	1			T2	636		T4	18		T6	11
valid_sources[0x4c]	533605	1			T2	614		T4	19		T6	20
valid_sources[0x4d]	1989028	1			T2	618		T4	22		T6	7
valid_sources[0x4e]	568345	1			T2	638		T4	15		T6	19
valid_sources[0x4f]	537301	1			T2	629		T4	31		T6	37
valid_sources[0x50]	1406244	1			T2	663		T4	21		T6	18
valid_sources[0x51]	580608	1			T2	622		T4	22		T6	34
valid_sources[0x52]	558999	1			T2	663		T4	25		T6	6
valid_sources[0x53]	559718	1			T2	579		T4	25		T6	24
valid_sources[0x54]	545650	1			T2	656		T4	10		T6	10
valid_sources[0x55]	568684	1			T2	653		T4	22		T6	24
valid_sources[0x56]	562290	1			T2	606		T4	24		T6	14
valid_sources[0x57]	588390	1			T2	648		T4	33		T6	17
valid_sources[0x58]	618719	1			T2	579		T4	29		T6	29
valid_sources[0x59]	609910	1			T2	612		T4	32		T6	41
valid_sources[0x5a]	531538	1			T2	584		T4	25		T6	10
valid_sources[0x5b]	570753	1			T2	594		T4	18		T6	11
valid_sources[0x5c]	537504	1			T2	599		T4	35		T6	18
valid_sources[0x5d]	539352	1			T2	570		T4	30		T6	11
valid_sources[0x5e]	556278	1			T2	582		T4	25		T6	34
valid_sources[0x5f]	540336	1			T2	570		T4	24		T6	27
valid_sources[0x60]	552924	1			T2	606		T4	23		T6	20
valid_sources[0x61]	571627	1			T2	579		T4	30		T6	11
valid_sources[0x62]	526461	1			T2	584		T4	28		T6	17
valid_sources[0x63]	609732	1			T2	647		T4	26		T6	28
valid_sources[0x64]	536093	1			T2	611		T4	24		T6	22
valid_sources[0x65]	589665	1			T2	578		T4	20		T6	22
valid_sources[0x66]	551097	1			T2	633		T4	30		T6	20
valid_sources[0x67]	538113	1			T2	608		T4	16		T6	25
valid_sources[0x68]	618984	1			T2	628		T4	19		T6	30
valid_sources[0x69]	552847	1			T2	608		T4	14		T6	37
valid_sources[0x6a]	586879	1			T2	605		T4	33		T6	37
valid_sources[0x6b]	562158	1			T2	609		T4	21		T6	25
valid_sources[0x6c]	533252	1			T2	608		T4	18		T6	45
valid_sources[0x6d]	536169	1			T2	644		T4	35		T6	37
valid_sources[0x6e]	561004	1			T2	671		T4	18		T6	13
valid_sources[0x6f]	562929	1			T2	606		T4	28		T6	20
valid_sources[0x70]	537048	1			T2	604		T4	23		T6	32
valid_sources[0x71]	538299	1			T2	600		T4	17		T6	13
valid_sources[0x72]	1940666	1			T2	627		T4	23		T6	8
valid_sources[0x73]	574604	1			T2	633		T4	29		T6	11
valid_sources[0x74]	536679	1			T2	645		T4	18		T6	23
valid_sources[0x75]	538945	1			T2	604		T4	23		T6	4
valid_sources[0x76]	554331	1			T2	651		T4	20		T6	11
valid_sources[0x77]	540008	1			T2	550		T4	17		T6	22
valid_sources[0x78]	545036	1			T2	608		T4	26		T6	24
valid_sources[0x79]	593742	1			T2	651		T4	27		T6	35
valid_sources[0x7a]	548538	1			T2	654		T4	20		T6	14
valid_sources[0x7b]	2462526	1			T2	624		T4	19		T6	18
valid_sources[0x7c]	540198	1			T2	587		T4	34		T6	29
valid_sources[0x7d]	574851	1			T2	606		T4	10		T6	18
valid_sources[0x7e]	567345	1			T2	567		T4	32		T6	23
valid_sources[0x7f]	553556	1			T2	623		T4	23		T6	15
valid_sources[0x80]	586935	1			T2	650		T4	18		T6	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

76514480

1

T2

70967

T4

531

T6

2626

values[0x0]

all_enables

biggest_size

39654911

1

T2

35589

T4

263

T6

1292

values[0x1]

all_enables

biggest_size

39676700

1

T2

35623

T4

271

T6

1284

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35918	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

163744

1

T1

2

T2

2

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57923	1			T7	30		T11	5		T8	25
values[0x0]	68662	1			T1	5		T2	9		T3	1
values[0x1]	73077	1			T2	5		T4	1		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26900	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

172762

1

T1

2

T2

2

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	527	1			T17	1		T49	1		T31	10
valid_sources[0x01]	620	1			T119	1		T31	4		T32	10
valid_sources[0x02]	631	1			T7	2		T8	1		T34	1
valid_sources[0x03]	816	1			T21	1		T49	1		T31	1
valid_sources[0x04]	696	1			T7	1		T18	5		T8	2
valid_sources[0x05]	588	1			T16	1		T18	9		T8	2
valid_sources[0x06]	750	1			T2	3		T34	2		T49	1
valid_sources[0x07]	727	1			T31	9		T32	13		T143	3
valid_sources[0x08]	1021	1			T18	2		T8	1		T133	1
valid_sources[0x09]	908	1			T7	3		T16	1		T18	3
valid_sources[0x0a]	801	1			T97	1		T31	3		T32	17
valid_sources[0x0b]	736	1			T31	10		T32	11		T33	8
valid_sources[0x0c]	768	1			T7	1		T8	1		T34	1
valid_sources[0x0d]	1189	1			T30	3		T31	3		T32	18
valid_sources[0x0e]	927	1			T30	1		T144	1		T31	5
valid_sources[0x0f]	621	1			T18	7		T34	1		T133	1
valid_sources[0x10]	552	1			T31	3		T32	13		T141	1
valid_sources[0x11]	610	1			T31	6		T32	17		T33	1
valid_sources[0x12]	811	1			T31	8		T32	18		T33	2
valid_sources[0x13]	798	1			T21	3		T31	4		T58	2
valid_sources[0x14]	871	1			T16	1		T8	1		T119	1
valid_sources[0x15]	899	1			T34	1		T145	2		T119	1
valid_sources[0x16]	603	1			T34	1		T103	5		T31	3
valid_sources[0x17]	893	1			T13	10		T49	1		T31	5
valid_sources[0x18]	672	1			T31	2		T32	16		T62	2
valid_sources[0x19]	698	1			T8	1		T26	2		T34	1
valid_sources[0x1a]	808	1			T31	6		T32	11		T33	10
valid_sources[0x1b]	743	1			T8	1		T26	1		T133	1
valid_sources[0x1c]	598	1			T34	2		T31	4		T32	10
valid_sources[0x1d]	914	1			T21	1		T119	1		T31	3
valid_sources[0x1e]	569	1			T7	1		T22	3		T34	1
valid_sources[0x1f]	760	1			T7	1		T8	2		T21	1
valid_sources[0x20]	944	1			T16	1		T8	1		T31	1
valid_sources[0x21]	798	1			T21	1		T34	3		T31	3
valid_sources[0x22]	800	1			T18	5		T21	1		T146	1
valid_sources[0x23]	591	1			T7	1		T21	1		T31	4
valid_sources[0x24]	637	1			T3	1		T21	1		T31	2
valid_sources[0x25]	662	1			T7	2		T31	13		T32	7
valid_sources[0x26]	701	1			T12	1		T77	1		T21	2
valid_sources[0x27]	599	1			T49	2		T31	1		T32	16
valid_sources[0x28]	996	1			T31	10		T32	21		T33	2
valid_sources[0x29]	783	1			T8	1		T21	1		T119	1
valid_sources[0x2a]	878	1			T49	1		T147	1		T30	3
valid_sources[0x2b]	781	1			T34	1		T31	6		T32	10
valid_sources[0x2c]	581	1			T49	2		T31	4		T32	11
valid_sources[0x2d]	755	1			T119	1		T31	1		T32	10
valid_sources[0x2e]	770	1			T49	1		T31	4		T32	7
valid_sources[0x2f]	747	1			T21	1		T34	2		T31	6
valid_sources[0x30]	808	1			T7	1		T31	1		T32	10
valid_sources[0x31]	733	1			T18	6		T49	1		T31	4
valid_sources[0x32]	545	1			T8	1		T30	1		T31	8
valid_sources[0x33]	576	1			T22	1		T31	1		T32	17
valid_sources[0x34]	855	1			T7	1		T15	1		T8	1
valid_sources[0x35]	714	1			T21	1		T31	5		T32	21
valid_sources[0x36]	822	1			T18	6		T26	2		T119	1
valid_sources[0x37]	686	1			T7	1		T21	1		T34	2
valid_sources[0x38]	954	1			T34	2		T9	1		T147	1
valid_sources[0x39]	982	1			T8	1		T119	1		T31	7
valid_sources[0x3a]	755	1			T21	2		T119	1		T146	1
valid_sources[0x3b]	887	1			T49	1		T31	1		T32	7
valid_sources[0x3c]	1069	1			T7	1		T21	1		T9	12
valid_sources[0x3d]	789	1			T11	26		T34	2		T146	1
valid_sources[0x3e]	680	1			T22	1		T21	1		T133	1
valid_sources[0x3f]	638	1			T16	1		T18	1		T8	1
valid_sources[0x40]	592	1			T34	1		T148	2		T119	1
valid_sources[0x41]	666	1			T7	1		T16	1		T22	1
valid_sources[0x42]	982	1			T18	2		T31	5		T32	10
valid_sources[0x43]	872	1			T31	1		T32	21		T33	4
valid_sources[0x44]	682	1			T119	1		T31	6		T32	9
valid_sources[0x45]	640	1			T49	1		T32	15		T143	1
valid_sources[0x46]	964	1			T21	2		T119	1		T31	4
valid_sources[0x47]	680	1			T7	1		T21	1		T133	1
valid_sources[0x48]	1009	1			T8	1		T149	1		T31	9
valid_sources[0x49]	713	1			T31	3		T32	15		T150	4
valid_sources[0x4a]	670	1			T7	1		T31	8		T32	6
valid_sources[0x4b]	628	1			T49	1		T31	6		T32	14
valid_sources[0x4c]	668	1			T8	1		T49	1		T31	5
valid_sources[0x4d]	776	1			T34	1		T9	9		T31	3
valid_sources[0x4e]	579	1			T21	2		T31	3		T32	3
valid_sources[0x4f]	827	1			T7	1		T21	1		T31	2
valid_sources[0x50]	920	1			T16	1		T22	1		T31	4
valid_sources[0x51]	815	1			T32	17		T138	1		T33	1
valid_sources[0x52]	674	1			T133	1		T31	1		T32	10
valid_sources[0x53]	932	1			T18	3		T97	1		T21	1
valid_sources[0x54]	650	1			T8	2		T34	2		T133	2
valid_sources[0x55]	767	1			T31	5		T32	11		T33	10
valid_sources[0x56]	841	1			T21	1		T49	1		T30	2
valid_sources[0x57]	726	1			T7	1		T49	1		T148	3
valid_sources[0x58]	632	1			T119	1		T31	3		T32	11
valid_sources[0x59]	641	1			T8	1		T21	1		T34	1
valid_sources[0x5a]	882	1			T21	1		T31	6		T58	2
valid_sources[0x5b]	801	1			T26	1		T49	1		T151	5
valid_sources[0x5c]	567	1			T4	2		T18	2		T34	1
valid_sources[0x5d]	786	1			T7	2		T16	1		T18	1
valid_sources[0x5e]	1159	1			T14	17		T49	1		T104	7
valid_sources[0x5f]	589	1			T9	1		T31	7		T32	14
valid_sources[0x60]	689	1			T7	1		T18	3		T21	1
valid_sources[0x61]	959	1			T7	1		T16	1		T49	1
valid_sources[0x62]	597	1			T16	1		T133	1		T147	1
valid_sources[0x63]	551	1			T10	1		T18	1		T119	1
valid_sources[0x64]	936	1			T16	1		T147	1		T31	4
valid_sources[0x65]	815	1			T31	1		T32	16		T33	11
valid_sources[0x66]	690	1			T119	1		T31	9		T32	19
valid_sources[0x67]	953	1			T31	2		T32	13		T52	50
valid_sources[0x68]	636	1			T16	1		T31	2		T32	19
valid_sources[0x69]	789	1			T7	1		T31	8		T32	13
valid_sources[0x6a]	710	1			T16	1		T21	1		T34	1
valid_sources[0x6b]	926	1			T18	2		T147	1		T31	9
valid_sources[0x6c]	620	1			T152	1		T119	1		T31	5
valid_sources[0x6d]	823	1			T2	2		T31	8		T32	13
valid_sources[0x6e]	1008	1			T34	1		T31	9		T32	16
valid_sources[0x6f]	804	1			T8	1		T21	1		T133	1
valid_sources[0x70]	1043	1			T146	1		T31	2		T32	11
valid_sources[0x71]	941	1			T34	1		T146	1		T31	4
valid_sources[0x72]	642	1			T7	2		T21	1		T146	1
valid_sources[0x73]	785	1			T21	2		T34	1		T13	8
valid_sources[0x74]	742	1			T21	1		T34	1		T49	1
valid_sources[0x75]	672	1			T18	6		T31	4		T32	11
valid_sources[0x76]	833	1			T7	2		T31	2		T32	16
valid_sources[0x77]	761	1			T2	4		T34	1		T31	5
valid_sources[0x78]	751	1			T21	1		T31	1		T32	17
valid_sources[0x79]	753	1			T7	1		T8	1		T31	4
valid_sources[0x7a]	597	1			T16	1		T8	2		T34	1
valid_sources[0x7b]	797	1			T8	1		T30	4		T31	3
valid_sources[0x7c]	830	1			T18	2		T49	1		T30	3
valid_sources[0x7d]	1054	1			T21	1		T146	1		T31	9
valid_sources[0x7e]	1019	1			T8	1		T26	1		T21	1
valid_sources[0x7f]	629	1			T133	1		T27	7		T49	2
valid_sources[0x80]	1407	1			T31	5		T32	9		T48	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44913

1

T7

17

T11

2

T8

14

values[0x0]

all_enables

biggest_size

60538

1

T1

2

T2

2

T4

1

values[0x1]

all_enables

biggest_size

58293

1

T7

2

T11

2

T15

1