Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15934311

1

T2

14252

T4

4921

T5

30939

full_word

152643591

1

T2

142179

T4

1065

T6

5202

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	168577572	1			T2	156431		T4	5986		T6	5202
auto[TlIntgErrCmd]	101	1			T105	1		T106	4		T107	3
auto[TlIntgErrData]	103	1			T105	4		T106	4		T107	4
auto[TlIntgErrBoth]	126	1			T105	5		T106	12		T107	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81170713

1

T2

77999

T4

2977

T6

2626

auto[1]

87407189

1

T2

78432

T4

3009

T6

2576

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7786001	1			T2	7032		T4	2446		T5	15979
auto[TlIntgErrNone]	partial	auto[1]	8148010	1			T2	7220		T4	2475		T5	14960
auto[TlIntgErrNone]	full_word	auto[0]	73384565	1			T2	70967		T4	531		T6	2626
auto[TlIntgErrNone]	full_word	auto[1]	79258996	1			T2	71212		T4	534		T6	2576
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T105	1		T106	3		T107	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T106	1		T107	1		T123	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T122	1		T124	1		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T126	1		T127	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T106	3		T107	2		T123	1
auto[TlIntgErrData]	partial	auto[1]	51	1			T105	3		T106	1		T107	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T126	1		T129	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T105	1		T126	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T105	1		T106	5		T107	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T105	4		T106	7		T107	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T132	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T123	1		T121	1		T132	1