Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	836036	1			T13	12164		T14	4770		T9	31
auto[1]	11297771	1			T2	48131		T6	2626		T5	1968
auto[2]	659042	1			T13	11020		T14	3076		T9	19
auto[3]	11023749	1			T2	48154		T6	2575		T5	2016

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14809348	1			T2	79403		T6	5201		T5	6
auto[1]	2192783	1			T2	8110		T5	103		T7	1
auto[2]	2232409	1			T2	7941		T5	242		T7	3
auto[3]	4582058	1			T2	831		T5	3633		T11	7

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10950939

1

T2

96280

T6

5201

T5

3984

auto[1]

12865659

1

T2

5

T15

3

T16

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	335222	1			T13	10078		T14	3919		T9	26
auto[0]	auto[0]	auto[1]	34598	1			T13	1014		T14	402		T9	1
auto[0]	auto[0]	auto[2]	34744	1			T13	969		T14	411		T9	4
auto[0]	auto[0]	auto[3]	91102	1			T13	103		T14	37		T49	82
auto[0]	auto[1]	auto[0]	3702758	1			T2	39843		T6	2626		T7	1
auto[0]	auto[1]	auto[1]	392278	1			T2	4025		T5	15		T11	68
auto[0]	auto[1]	auto[2]	424789	1			T2	3857		T5	73		T7	1
auto[0]	auto[1]	auto[3]	634373	1			T2	402		T5	1880		T11	7
auto[0]	auto[2]	auto[0]	254149	1			T13	9339		T14	2408		T9	17
auto[0]	auto[2]	auto[1]	32540	1			T13	954		T14	270		T9	1
auto[0]	auto[2]	auto[2]	22739	1			T13	663		T14	352		T9	1
auto[0]	auto[2]	auto[3]	60511	1			T13	64		T14	46		T49	54
auto[0]	auto[3]	auto[0]	3540718	1			T2	39557		T6	2575		T5	6
auto[0]	auto[3]	auto[1]	402729	1			T2	4083		T5	88		T7	1
auto[0]	auto[3]	auto[2]	415733	1			T2	4084		T5	169		T7	2
auto[0]	auto[3]	auto[3]	571956	1			T2	429		T5	1753		T12	144
auto[1]	auto[0]	auto[0]	11397	1			T14	1		T140	1073		T141	794
auto[1]	auto[0]	auto[1]	50689	1			T140	4959		T141	3625		T142	4156
auto[1]	auto[0]	auto[2]	50495	1			T140	4903		T141	3647		T142	4162
auto[1]	auto[0]	auto[3]	227789	1			T140	22078		T141	16330		T142	18486
auto[1]	auto[1]	auto[0]	3480557	1			T2	3		T16	2		T97	84394
auto[1]	auto[1]	auto[1]	632365	1			T2	1		T97	8382		T77	5476
auto[1]	auto[1]	auto[2]	614658	1			T97	8440		T77	6160		T78	5054
auto[1]	auto[1]	auto[3]	1415993	1			T97	830		T77	529		T78	429
auto[1]	auto[2]	auto[0]	9340	1			T49	1		T140	993		T141	726
auto[1]	auto[2]	auto[1]	41462	1			T140	4482		T141	3496		T142	3897
auto[1]	auto[2]	auto[2]	43087	1			T140	4220		T141	2972		T142	3442
auto[1]	auto[2]	auto[3]	195214	1			T140	18654		T141	13918		T142	15626
auto[1]	auto[3]	auto[0]	3475207	1			T16	1		T97	84389		T77	60967
auto[1]	auto[3]	auto[1]	606122	1			T2	1		T15	1		T97	8468
auto[1]	auto[3]	auto[2]	626164	1			T97	8463		T77	5535		T78	4546
auto[1]	auto[3]	auto[3]	1385120	1			T15	2		T97	874		T77	581