Unified Coverage Report :: Module :: prim_ram_1p_scr

Module : prim_ram_1p_scr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.40	98.11	91.49			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_ram_1p_scr	97.87	100.00	91.49			100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	91.49			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.40	100.00	92.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_addr_scr.u_prim_subst_perm	100.00	100.00
gen_diffuse_data[0].u_prim_subst_perm_dec	100.00	100.00
gen_diffuse_data[0].u_prim_subst_perm_enc	100.00	100.00
gen_par_scr[0].u_prim_prince	100.00			100.00
u_intg_error	100.00	100.00
u_prim_ram_1p_adv	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_ram_1p_scr

	Line No.	Total	Covered	Percent
TOTAL		53	52	98.11
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
ALWAYS	315	10	9	90.00
ALWAYS	343	26	26	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	1	1
114	1	1
115	1	1
121	1	1
131	1	1
134	1	1
137	1	1
145	1	1
150	1	1
171	1	1
184	1	1
213	1	1
219	1	1
245	1	1
275	1	1
300	1	1
309	1	1
315	1	1
316	1	1
318	1	1
319	1	1
322	1	1
323	1	1
324	1	1
325	1	1
327	0	1
333	1	1
			MISSING_ELSE
343	1	1
344	1	1
345	1	1
346	1	1
347	1	1
348	1	1
349	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
362	1	1
363	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
371	1	1
372	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_ram_1p_scr

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       112
 EXPRESSION (req_i & key_valid_i)
             --1--   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T16,T19
1	1	Covered	T2,T4,T6

 LINE       114
 EXPRESSION (gnt_o & ((~write_i)))
             --1--   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T6

 LINE       115
 EXPRESSION (gnt_o & write_i)
             --1--   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T16
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T6

 LINE       121
 EXPRESSION (read_en & (write_en_q | write_pending_q) & (addr_scr == waddr_scr_q))
             ---1---   ---------------2--------------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T6
1	0	1	Covered	T2,T18,T19
1	1	0	Covered	T2,T6,T5
1	1	1	Covered	T2,T15,T16

 LINE       121
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T5
1	0	Covered	T2,T4,T6

 LINE       121
 SUB-EXPRESSION (addr_scr == waddr_scr_q)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       131
 EXPRESSION (((~intg_error_w_q)) & ((~intg_error_buf)) & (read_en | write_en_q | write_pending_q))
             ---------1---------   ---------2---------   --------------------3-------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T4,T6

 LINE       131
 SUB-EXPRESSION (read_en | write_en_q | write_pending_q)
                 ---1---   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T6,T5
0	1	0	Covered	T2,T4,T6
1	0	0	Covered	T2,T4,T5

 LINE       134
 EXPRESSION ((write_en_q | write_pending_q) & ((~read_en)) & ((~intg_error_w_q)))
             ---------------1--------------   ------2-----   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T6

 LINE       134
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T5
1	0	Covered	T2,T4,T6

 LINE       137
 EXPRESSION (write_en_q & read_en)
             -----1----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T6,T5

 LINE       145
 EXPRESSION (read_en ? addr_scr : waddr_scr_q)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       300
 EXPRESSION (macro_write ? 1'b0 : (rw_collision ? 1'b1 : write_pending_q))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       300
 SUB-EXPRESSION (rw_collision ? 1'b1 : write_pending_q)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T5

 LINE       309
 EXPRESSION (write_pending_q ? wdata_scr_q : wdata_scr_d)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T5

 LINE       318
 EXPRESSION (((!intg_error_r_q)) && rvalid_q)
             ---------1---------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

---

Branch Coverage for Module : prim_ram_1p_scr

	Line No.	Total	Covered	Percent
Branches		17	17	100.00
TERNARY	145	2	2	100.00
TERNARY	300	3	3	100.00
TERNARY	309	2	2	100.00
IF	318	3	3	100.00
IF	343	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	145	(read_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	(macro_write) ? 
-2-:	300	(rw_collision) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T6
0	1	Covered	T2,T6,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	(write_pending_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	318	if (((!intg_error_r_q) && rvalid_q))
-2-:	322	if (addr_collision_q)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T15,T16
1	0	Covered	T2,T4,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	343	if ((!rst_ni))
-2-:	362	if (read_en)
-3-:	365	if (write_en_d)
-4-:	371	if (rw_collision)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T4,T6
0	0	-	-	Covered	T1,T2,T3
0	-	1	-	Covered	T2,T4,T6
0	-	0	-	Covered	T1,T2,T3
0	-	-	1	Covered	T2,T6,T5
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_ram_1p_scr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DepthPow2Check_A	903	903	0	0
DiffWidthMinimum_A	903	903	0	0
DiffWidthWithParity_A	903	903	0	0

DepthPow2Check_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903	903	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

DiffWidthMinimum_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903	903	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

DiffWidthWithParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903	903	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Line No.	Total	Covered	Percent
TOTAL		52	52	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
ALWAYS	315	9	9	100.00
ALWAYS	343	26	26	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	1	1
114	1	1
115	1	1
121	1	1
131	1	1
134	1	1
137	1	1
145	1	1
150	1	1
171	1	1
184	1	1
213	1	1
219	1	1
245	1	1
275	1	1
300	1	1
309	1	1
315	1	1
316	1	1
318	1	1
319	1	1
322	1	1
323	1	1
324	1	1
325	1	1
327		excluded
			Exclude Annotation: VC_COV_UNR
333	1	1
			MISSING_ELSE
343	1	1
344	1	1
345	1	1
346	1	1
347	1	1
348	1	1
349	1	1
350	1	1
351	1	1
352	1	1
353	1	1
354	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
362	1	1
363	1	1
			MISSING_ELSE
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
371	1	1
372	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       112
 EXPRESSION (req_i & key_valid_i)
             --1--   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T16,T19
1	1	Covered	T2,T4,T6

 LINE       114
 EXPRESSION (gnt_o & ((~write_i)))
             --1--   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T6

 LINE       115
 EXPRESSION (gnt_o & write_i)
             --1--   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T16
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T6

 LINE       121
 EXPRESSION (read_en & (write_en_q | write_pending_q) & (addr_scr == waddr_scr_q))
             ---1---   ---------------2--------------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T6
1	0	1	Covered	T2,T18,T19
1	1	0	Covered	T2,T6,T5
1	1	1	Covered	T2,T15,T16

 LINE       121
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T5
1	0	Covered	T2,T4,T6

 LINE       121
 SUB-EXPRESSION (addr_scr == waddr_scr_q)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       131
 EXPRESSION (((~intg_error_w_q)) & ((~intg_error_buf)) & (read_en | write_en_q | write_pending_q))
             ---------1---------   ---------2---------   --------------------3-------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T4,T6

 LINE       131
 SUB-EXPRESSION (read_en | write_en_q | write_pending_q)
                 ---1---   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T6,T5
0	1	0	Covered	T2,T4,T6
1	0	0	Covered	T2,T4,T5

 LINE       134
 EXPRESSION ((write_en_q | write_pending_q) & ((~read_en)) & ((~intg_error_w_q)))
             ---------------1--------------   ------2-----   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T6

 LINE       134
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T5
1	0	Covered	T2,T4,T6

 LINE       137
 EXPRESSION (write_en_q & read_en)
             -----1----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T6,T5

 LINE       145
 EXPRESSION (read_en ? addr_scr : waddr_scr_q)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       300
 EXPRESSION (macro_write ? 1'b0 : (rw_collision ? 1'b1 : write_pending_q))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       300
 SUB-EXPRESSION (rw_collision ? 1'b1 : write_pending_q)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T5

 LINE       309
 EXPRESSION (write_pending_q ? wdata_scr_q : wdata_scr_d)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T5

 LINE       318
 EXPRESSION (((!intg_error_r_q)) && rvalid_q)
             ---------1---------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

---

Branch Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Line No.	Total	Covered	Percent
Branches		17	17	100.00
TERNARY	145	2	2	100.00
TERNARY	300	3	3	100.00
TERNARY	309	2	2	100.00
IF	318	3	3	100.00
IF	343	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	145	(read_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	(macro_write) ? 
-2-:	300	(rw_collision) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T6
0	1	Covered	T2,T6,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	(write_pending_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	318	if (((!intg_error_r_q) && rvalid_q))
-2-:	322	if (addr_collision_q)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T15,T16
1	0	Covered	T2,T4,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	343	if ((!rst_ni))
-2-:	362	if (read_en)
-3-:	365	if (write_en_d)
-4-:	371	if (rw_collision)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T4,T6
0	0	-	-	Covered	T1,T2,T3
0	-	1	-	Covered	T2,T4,T6
0	-	0	-	Covered	T1,T2,T3
0	-	-	1	Covered	T2,T6,T5
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DepthPow2Check_A	903	903	0	0
DiffWidthMinimum_A	903	903	0	0
DiffWidthWithParity_A	903	903	0	0

DepthPow2Check_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903	903	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

DiffWidthMinimum_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903	903	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

DiffWidthWithParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903	903	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0