Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1121671906	160705	0	0
ctrl_regwen_rd_A	1121671906	9007	0	0
exec_rd_A	1121671906	8121	0	0
exec_regwen_rd_A	1121671906	9528	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121671906	160705	0	0
T31	72488	1157	0	0
T32	85734	2606	0	0
T33	0	1754	0	0
T50	570556	0	0	0
T51	0	1119	0	0
T52	0	6345	0	0
T53	0	3577	0	0
T54	0	6905	0	0
T55	0	2429	0	0
T56	0	3457	0	0
T57	0	579	0	0
T58	228000	0	0	0
T59	103334	0	0	0
T60	1004	0	0	0
T61	154666	0	0	0
T62	436000	0	0	0
T63	1123	0	0	0
T64	197517	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121671906	9007	0	0
T33	74055	150	0	0
T51	62631	261	0	0
T52	0	583	0	0
T53	0	729	0	0
T57	0	67	0	0
T85	96391	0	0	0
T96	437920	0	0	0
T108	0	206	0	0
T109	0	642	0	0
T110	0	362	0	0
T111	0	159	0	0
T112	0	791	0	0
T113	78844	0	0	0
T114	46763	0	0	0
T115	261322	0	0	0
T116	820396	0	0	0
T117	164252	0	0	0
T118	384160	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121671906	8121	0	0
T33	74055	101	0	0
T51	62631	290	0	0
T52	0	341	0	0
T53	0	648	0	0
T57	0	97	0	0
T85	96391	0	0	0
T96	437920	0	0	0
T108	0	157	0	0
T109	0	637	0	0
T110	0	279	0	0
T111	0	134	0	0
T112	0	832	0	0
T113	78844	0	0	0
T114	46763	0	0	0
T115	261322	0	0	0
T116	820396	0	0	0
T117	164252	0	0	0
T118	384160	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1121671906	9528	0	0
T33	74055	181	0	0
T51	62631	318	0	0
T52	0	602	0	0
T53	0	729	0	0
T57	0	89	0	0
T85	96391	0	0	0
T96	437920	0	0	0
T108	0	219	0	0
T109	0	735	0	0
T110	0	429	0	0
T111	0	128	0	0
T112	0	919	0	0
T113	78844	0	0	0
T114	46763	0	0	0
T115	261322	0	0	0
T116	820396	0	0	0
T117	164252	0	0	0
T118	384160	0	0	0