Line Coverage for Module :
tlul_sram_byte
| Line No. | Total | Covered | Percent |
TOTAL | | 65 | 65 | 100.00 |
ALWAYS | 58 | 3 | 3 | 100.00 |
CONT_ASSIGN | 75 | 1 | 1 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
ALWAYS | 86 | 20 | 20 | 100.00 |
CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
ALWAYS | 180 | 2 | 2 | 100.00 |
ALWAYS | 191 | 0 | 0 | |
ALWAYS | 191 | 2 | 2 | 100.00 |
ALWAYS | 210 | 2 | 2 | 100.00 |
ALWAYS | 217 | 20 | 20 | 100.00 |
CONT_ASSIGN | 264 | 1 | 1 | 100.00 |
CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
ALWAYS | 293 | 4 | 4 | 100.00 |
CONT_ASSIGN | 311 | 1 | 1 | 100.00 |
CONT_ASSIGN | 320 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
58 |
1 |
1 |
59 |
1 |
1 |
61 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
96 |
1 |
1 |
97 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
106 |
1 |
1 |
107 |
1 |
1 |
108 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
121 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
147 |
1 |
1 |
180 |
1 |
1 |
181 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
192 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
217 |
1 |
1 |
219 |
1 |
1 |
228 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
244 |
1 |
1 |
246 |
1 |
1 |
248 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
254 |
1 |
1 |
255 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
264 |
1 |
1 |
268 |
1 |
1 |
293 |
1 |
1 |
296 |
1 |
1 |
300 |
1 |
1 |
305 |
1 |
1 |
311 |
1 |
1 |
320 |
1 |
1 |
Cond Coverage for Module :
tlul_sram_byte
| Total | Covered | Percent |
Conditions | 54 | 49 | 90.74 |
Logical | 54 | 49 | 90.74 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 75
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T2,T4,T6 |
LINE 76
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T5 |
1 | 1 | Covered | T2,T4,T6 |
LINE 77
EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T16,T19,T13 |
1 | 1 | Covered | T2,T4,T6 |
LINE 78
EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T5 |
1 | 1 | Covered | T2,T4,T6 |
LINE 79
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T6 |
0 | 1 | Covered | T2,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
LINE 79
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 79
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T6 |
LINE 81
EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
---------------1-------------- ------------2----------- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T4,T6 |
1 | 0 | 1 | Covered | T2,T4,T5 |
1 | 1 | 0 | Covered | T11,T20,T21 |
1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 82
EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
------1----- --------2-------- ------------3------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T4,T6 |
1 | 1 | 0 | Covered | T2,T4,T5 |
1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 108
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T13,T14,T9 |
1 | Covered | T2,T4,T5 |
LINE 180
EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
--------------1-------------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T4,T6 |
1 | 1 | Covered | T2,T4,T5 |
LINE 192
EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
-------------------1------------------
-1- | Status | Tests |
0 | Covered | T2,T4,T5 |
1 | Covered | T2,T4,T5 |
LINE 219
EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait)
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T5,T22 |
1 | 0 | Covered | T1,T2,T3 |
LINE 248
EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T11,T20,T21 |
0 | 1 | Covered | T2,T4,T5 |
1 | 0 | Covered | T2,T4,T5 |
LINE 254
EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
------1----- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T2,T4,T5 |
LINE 268
EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
---1--- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T6 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 296
EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
--------1-------- -----------------2---------------- -------------3------------- ----------------4---------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T2,T4,T6 |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 300
EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)))
--------1-------- ---------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T2,T4,T6 |
FSM Coverage for Module :
tlul_sram_byte
Summary for FSM :: gen_integ_handling.state_q
| Total | Covered | Percent | |
States |
3 |
3 |
100.00 |
(Not included in score) |
Transitions |
3 |
3 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q
states | Line No. | Covered | Tests |
StPassThru |
121 |
Covered |
T1,T2,T3 |
StWaitRd |
97 |
Covered |
T2,T4,T5 |
StWriteCmd |
111 |
Covered |
T2,T4,T5 |
transitions | Line No. | Covered | Tests |
StPassThru->StWaitRd |
97 |
Covered |
T2,T4,T5 |
StWaitRd->StWriteCmd |
111 |
Covered |
T2,T4,T5 |
StWriteCmd->StPassThru |
121 |
Covered |
T2,T4,T5 |
Branch Coverage for Module :
tlul_sram_byte
| Line No. | Total | Covered | Percent |
Branches |
|
19 |
16 |
84.21 |
IF |
58 |
2 |
2 |
100.00 |
CASE |
92 |
9 |
6 |
66.67 |
IF |
180 |
2 |
2 |
100.00 |
TERNARY |
192 |
2 |
2 |
100.00 |
IF |
228 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 58 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 case (gen_integ_handling.state_q)
-2-: 94 if (gen_integ_handling.byte_wr_txn)
-3-: 96 if (gen_integ_handling.byte_req_ack)
-4-: 108 if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-5-: 110 if (gen_integ_handling.sram_d_ack)
-6-: 120 if (gen_integ_handling.sram_a_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
StPassThru |
1 |
1 |
- |
- |
- |
Covered |
T2,T4,T5 |
StPassThru |
1 |
0 |
- |
- |
- |
Covered |
T11,T16,T19 |
StPassThru |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StWaitRd |
- |
- |
1 |
1 |
- |
Covered |
T2,T4,T5 |
StWaitRd |
- |
- |
1 |
0 |
- |
Not Covered |
|
StWaitRd |
- |
- |
0 |
- |
- |
Covered |
T13,T14,T9 |
StWriteCmd |
- |
- |
- |
- |
1 |
Covered |
T2,T4,T5 |
StWriteCmd |
- |
- |
- |
- |
0 |
Not Covered |
|
default |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 180 if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 (gen_integ_handling.held_data.a_mask[i]) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T5 |
0 |
Covered |
T2,T4,T5 |
LineNo. Expression
-1-: 228 if (gen_integ_handling.wr_phase)
-2-: 244 if (gen_integ_handling.rd_phase)
-3-: 248 if (((!error_i) || gen_integ_handling.stall_host))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T2,T4,T5 |
0 |
1 |
1 |
Covered |
T2,T4,T5 |
0 |
1 |
0 |
Covered |
T11,T20,T21 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_sram_byte
Assertion Details
gen_integ_handling.ByteAccessStateChange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1109975877 |
7209904 |
0 |
0 |
T2 |
693856 |
7220 |
0 |
0 |
T3 |
1002 |
0 |
0 |
0 |
T4 |
127428 |
2475 |
0 |
0 |
T5 |
235880 |
14960 |
0 |
0 |
T6 |
72432 |
0 |
0 |
0 |
T7 |
937335 |
11 |
0 |
0 |
T10 |
33661 |
0 |
0 |
0 |
T11 |
343783 |
858 |
0 |
0 |
T12 |
76206 |
726 |
0 |
0 |
T15 |
94387 |
14218 |
0 |
0 |
T16 |
0 |
6489 |
0 |
0 |
T17 |
0 |
4105 |
0 |
0 |
T18 |
0 |
29988 |
0 |
0 |
gen_integ_handling.ReadCompleteStateChange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1109975877 |
7209904 |
0 |
0 |
T2 |
693856 |
7220 |
0 |
0 |
T3 |
1002 |
0 |
0 |
0 |
T4 |
127428 |
2475 |
0 |
0 |
T5 |
235880 |
14960 |
0 |
0 |
T6 |
72432 |
0 |
0 |
0 |
T7 |
937335 |
11 |
0 |
0 |
T10 |
33661 |
0 |
0 |
0 |
T11 |
343783 |
858 |
0 |
0 |
T12 |
76206 |
726 |
0 |
0 |
T15 |
94387 |
14218 |
0 |
0 |
T16 |
0 |
6489 |
0 |
0 |
T17 |
0 |
4105 |
0 |
0 |
T18 |
0 |
29988 |
0 |
0 |
gen_integ_handling.TlulSramByteTlSize_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1109975877 |
1109849231 |
0 |
0 |
T1 |
722 |
669 |
0 |
0 |
T2 |
693856 |
693786 |
0 |
0 |
T3 |
1002 |
932 |
0 |
0 |
T4 |
127428 |
127348 |
0 |
0 |
T5 |
235880 |
235803 |
0 |
0 |
T6 |
72432 |
72376 |
0 |
0 |
T7 |
937335 |
937101 |
0 |
0 |
T10 |
33661 |
33568 |
0 |
0 |
T11 |
343783 |
343699 |
0 |
0 |
T12 |
76206 |
76144 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
| Line No. | Total | Covered | Percent |
TOTAL | | 65 | 65 | 100.00 |
ALWAYS | 58 | 3 | 3 | 100.00 |
CONT_ASSIGN | 75 | 1 | 1 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
ALWAYS | 86 | 20 | 20 | 100.00 |
CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
ALWAYS | 180 | 2 | 2 | 100.00 |
ALWAYS | 191 | 0 | 0 | |
ALWAYS | 191 | 2 | 2 | 100.00 |
ALWAYS | 210 | 2 | 2 | 100.00 |
ALWAYS | 217 | 20 | 20 | 100.00 |
CONT_ASSIGN | 264 | 1 | 1 | 100.00 |
CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
ALWAYS | 293 | 4 | 4 | 100.00 |
CONT_ASSIGN | 311 | 1 | 1 | 100.00 |
CONT_ASSIGN | 320 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
58 |
1 |
1 |
59 |
1 |
1 |
61 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
96 |
1 |
1 |
97 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
106 |
1 |
1 |
107 |
1 |
1 |
108 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
121 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
Exclude Annotation: VC_COV_UNR |
147 |
1 |
1 |
180 |
1 |
1 |
181 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
192 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
217 |
1 |
1 |
219 |
1 |
1 |
228 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
244 |
1 |
1 |
246 |
1 |
1 |
248 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
254 |
1 |
1 |
255 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
264 |
1 |
1 |
268 |
1 |
1 |
293 |
1 |
1 |
296 |
1 |
1 |
300 |
1 |
1 |
305 |
1 |
1 |
311 |
1 |
1 |
320 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
| Total | Covered | Percent |
Conditions | 49 | 49 | 100.00 |
Logical | 49 | 49 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 75
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T2,T4,T6 |
LINE 76
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T5 |
1 | 1 | Covered | T2,T4,T6 |
LINE 77
EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T16,T19,T13 |
1 | 1 | Covered | T2,T4,T6 |
LINE 78
EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T5 |
1 | 1 | Covered | T2,T4,T6 |
LINE 79
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T4,T6 |
0 | 1 | Covered | T2,T4,T6 |
1 | 0 | Covered | T1,T2,T3 |
LINE 79
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 79
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T6 |
LINE 81
EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
---------------1-------------- ------------2----------- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T4,T6 |
1 | 0 | 1 | Covered | T2,T4,T5 |
1 | 1 | 0 | Covered | T11,T20,T21 |
1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 82
EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
------1----- --------2-------- ------------3------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T4,T6 |
1 | 1 | 0 | Covered | T2,T4,T5 |
1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 108
EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T13,T14,T9 |
1 | Covered | T2,T4,T5 |
LINE 180
EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
--------------1-------------- -------------2------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
[UNR] this should not happen because the read latency of prim_ram_1p_scr is always 1 cycle |
1 | 0 | Covered | T2,T4,T6 |
1 | 1 | Covered | T2,T4,T5 |
LINE 192
EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
-------------------1------------------
-1- | Status | Tests |
0 | Covered | T2,T4,T5 |
1 | Covered | T2,T4,T5 |
LINE 219
EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait)
------1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T5,T22 |
1 | 0 | Covered | T1,T2,T3 |
LINE 248
EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T11,T20,T21 |
0 | 1 | Covered | T2,T4,T5 |
1 | 0 | Covered | T2,T4,T5 |
LINE 254
EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
------1----- -----------------2----------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T2,T4,T5 |
LINE 268
EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
---1--- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T6 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 296
EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
--------1-------- -----------------2---------------- -------------3------------- ----------------4---------------
-1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | 1 | Covered | T2,T4,T6 |
1 | 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 300
EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)))
--------1-------- ---------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T2,T4,T6 |
FSM Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
Summary for FSM :: gen_integ_handling.state_q
| Total | Covered | Percent | |
States |
3 |
3 |
100.00 |
(Not included in score) |
Transitions |
3 |
3 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q
states | Line No. | Covered | Tests |
StPassThru |
121 |
Covered |
T1,T2,T3 |
StWaitRd |
97 |
Covered |
T2,T4,T5 |
StWriteCmd |
111 |
Covered |
T2,T4,T5 |
transitions | Line No. | Covered | Tests |
StPassThru->StWaitRd |
97 |
Covered |
T2,T4,T5 |
StWaitRd->StWriteCmd |
111 |
Covered |
T2,T4,T5 |
StWriteCmd->StPassThru |
121 |
Covered |
T2,T4,T5 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
| Line No. | Total | Covered | Percent |
Branches |
|
16 |
16 |
100.00 |
IF |
58 |
2 |
2 |
100.00 |
CASE |
92 |
6 |
6 |
100.00 |
IF |
180 |
2 |
2 |
100.00 |
TERNARY |
192 |
2 |
2 |
100.00 |
IF |
228 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 58 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 92 case (gen_integ_handling.state_q)
-2-: 94 if (gen_integ_handling.byte_wr_txn)
-3-: 96 if (gen_integ_handling.byte_req_ack)
-4-: 108 if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-5-: 110 if (gen_integ_handling.sram_d_ack)
-6-: 120 if (gen_integ_handling.sram_a_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests | Exclude Annotation |
StPassThru |
1 |
1 |
- |
- |
- |
Covered |
T2,T4,T5 |
|
StPassThru |
1 |
0 |
- |
- |
- |
Covered |
T11,T16,T19 |
|
StPassThru |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
StWaitRd |
- |
- |
1 |
1 |
- |
Covered |
T2,T4,T5 |
|
StWaitRd |
- |
- |
1 |
0 |
- |
Excluded |
|
[UNR] this should not happen because the read latency of prim_ram_1p_scr is always 1 cycle |
StWaitRd |
- |
- |
0 |
- |
- |
Covered |
T13,T14,T9 |
|
StWriteCmd |
- |
- |
- |
- |
1 |
Covered |
T2,T4,T5 |
|
StWriteCmd |
- |
- |
- |
- |
0 |
Excluded |
|
[UNR] this should not happen because prim_ram_1p_scr can always accept a read or write operation |
default |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 180 if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 (gen_integ_handling.held_data.a_mask[i]) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T4,T5 |
0 |
Covered |
T2,T4,T5 |
LineNo. Expression
-1-: 228 if (gen_integ_handling.wr_phase)
-2-: 244 if (gen_integ_handling.rd_phase)
-3-: 248 if (((!error_i) || gen_integ_handling.stall_host))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T2,T4,T5 |
0 |
1 |
1 |
Covered |
T2,T4,T5 |
0 |
1 |
0 |
Covered |
T11,T20,T21 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte
Assertion Details
gen_integ_handling.ByteAccessStateChange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1109975877 |
7209904 |
0 |
0 |
T2 |
693856 |
7220 |
0 |
0 |
T3 |
1002 |
0 |
0 |
0 |
T4 |
127428 |
2475 |
0 |
0 |
T5 |
235880 |
14960 |
0 |
0 |
T6 |
72432 |
0 |
0 |
0 |
T7 |
937335 |
11 |
0 |
0 |
T10 |
33661 |
0 |
0 |
0 |
T11 |
343783 |
858 |
0 |
0 |
T12 |
76206 |
726 |
0 |
0 |
T15 |
94387 |
14218 |
0 |
0 |
T16 |
0 |
6489 |
0 |
0 |
T17 |
0 |
4105 |
0 |
0 |
T18 |
0 |
29988 |
0 |
0 |
gen_integ_handling.ReadCompleteStateChange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1109975877 |
7209904 |
0 |
0 |
T2 |
693856 |
7220 |
0 |
0 |
T3 |
1002 |
0 |
0 |
0 |
T4 |
127428 |
2475 |
0 |
0 |
T5 |
235880 |
14960 |
0 |
0 |
T6 |
72432 |
0 |
0 |
0 |
T7 |
937335 |
11 |
0 |
0 |
T10 |
33661 |
0 |
0 |
0 |
T11 |
343783 |
858 |
0 |
0 |
T12 |
76206 |
726 |
0 |
0 |
T15 |
94387 |
14218 |
0 |
0 |
T16 |
0 |
6489 |
0 |
0 |
T17 |
0 |
4105 |
0 |
0 |
T18 |
0 |
29988 |
0 |
0 |
gen_integ_handling.TlulSramByteTlSize_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1109975877 |
1109849231 |
0 |
0 |
T1 |
722 |
669 |
0 |
0 |
T2 |
693856 |
693786 |
0 |
0 |
T3 |
1002 |
932 |
0 |
0 |
T4 |
127428 |
127348 |
0 |
0 |
T5 |
235880 |
235803 |
0 |
0 |
T6 |
72432 |
72376 |
0 |
0 |
T7 |
937335 |
937101 |
0 |
0 |
T10 |
33661 |
33568 |
0 |
0 |
T11 |
343783 |
343699 |
0 |
0 |
T12 |
76206 |
76144 |
0 |
0 |