| T793 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3226684238 |
|
|
Apr 30 01:28:27 PM PDT 24 |
Apr 30 01:28:31 PM PDT 24 |
1353042252 ps |
| T794 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1682288469 |
|
|
Apr 30 01:22:42 PM PDT 24 |
Apr 30 01:24:24 PM PDT 24 |
6784435608 ps |
| T795 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3793809665 |
|
|
Apr 30 01:17:40 PM PDT 24 |
Apr 30 01:44:56 PM PDT 24 |
108085712716 ps |
| T796 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1634001627 |
|
|
Apr 30 01:12:11 PM PDT 24 |
Apr 30 01:12:15 PM PDT 24 |
1691445000 ps |
| T797 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2529282267 |
|
|
Apr 30 01:11:01 PM PDT 24 |
Apr 30 01:11:49 PM PDT 24 |
29428786334 ps |
| T798 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3785613782 |
|
|
Apr 30 01:20:38 PM PDT 24 |
Apr 30 01:24:39 PM PDT 24 |
8209107070 ps |
| T799 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.535332826 |
|
|
Apr 30 01:15:07 PM PDT 24 |
Apr 30 01:15:21 PM PDT 24 |
832738619 ps |
| T800 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2212744792 |
|
|
Apr 30 01:13:29 PM PDT 24 |
Apr 30 01:15:58 PM PDT 24 |
41307499819 ps |
| T801 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3702445933 |
|
|
Apr 30 01:12:51 PM PDT 24 |
Apr 30 01:13:02 PM PDT 24 |
406071993 ps |
| T802 |
/workspace/coverage/default/48.sram_ctrl_regwen.3641086912 |
|
|
Apr 30 01:28:25 PM PDT 24 |
Apr 30 01:31:26 PM PDT 24 |
1770946184 ps |
| T803 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.3109682777 |
|
|
Apr 30 01:24:27 PM PDT 24 |
Apr 30 01:26:54 PM PDT 24 |
27567058372 ps |
| T804 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2616396257 |
|
|
Apr 30 01:25:56 PM PDT 24 |
Apr 30 01:46:25 PM PDT 24 |
54256763656 ps |
| T805 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.131282262 |
|
|
Apr 30 01:23:23 PM PDT 24 |
Apr 30 01:28:27 PM PDT 24 |
55128675028 ps |
| T806 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2556304589 |
|
|
Apr 30 01:20:54 PM PDT 24 |
Apr 30 01:26:01 PM PDT 24 |
5122421705 ps |
| T807 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1173242673 |
|
|
Apr 30 01:20:30 PM PDT 24 |
Apr 30 01:25:36 PM PDT 24 |
63377627164 ps |
| T808 |
/workspace/coverage/default/48.sram_ctrl_stress_all.1060789520 |
|
|
Apr 30 01:28:34 PM PDT 24 |
Apr 30 02:47:32 PM PDT 24 |
59204004241 ps |
| T809 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.160943917 |
|
|
Apr 30 01:27:14 PM PDT 24 |
Apr 30 01:28:30 PM PDT 24 |
10211311618 ps |
| T810 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2707410655 |
|
|
Apr 30 01:24:10 PM PDT 24 |
Apr 30 01:24:34 PM PDT 24 |
1494445937 ps |
| T811 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.4290038672 |
|
|
Apr 30 01:18:02 PM PDT 24 |
Apr 30 01:22:37 PM PDT 24 |
14332231505 ps |
| T812 |
/workspace/coverage/default/41.sram_ctrl_bijection.2471084257 |
|
|
Apr 30 01:26:02 PM PDT 24 |
Apr 30 01:52:19 PM PDT 24 |
90489532779 ps |
| T813 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.261523371 |
|
|
Apr 30 01:11:45 PM PDT 24 |
Apr 30 01:13:26 PM PDT 24 |
776925762 ps |
| T814 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3407899973 |
|
|
Apr 30 01:15:27 PM PDT 24 |
Apr 30 01:16:41 PM PDT 24 |
2715770306 ps |
| T815 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.71191587 |
|
|
Apr 30 01:18:35 PM PDT 24 |
Apr 30 01:44:24 PM PDT 24 |
24311725292 ps |
| T816 |
/workspace/coverage/default/40.sram_ctrl_smoke.2759694483 |
|
|
Apr 30 01:25:41 PM PDT 24 |
Apr 30 01:27:39 PM PDT 24 |
1084926886 ps |
| T817 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3871911145 |
|
|
Apr 30 01:12:37 PM PDT 24 |
Apr 30 01:13:18 PM PDT 24 |
766142428 ps |
| T818 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2079814627 |
|
|
Apr 30 01:28:03 PM PDT 24 |
Apr 30 01:28:54 PM PDT 24 |
506408683 ps |
| T38 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2392424188 |
|
|
Apr 30 01:11:04 PM PDT 24 |
Apr 30 01:11:07 PM PDT 24 |
983738152 ps |
| T819 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.3023287678 |
|
|
Apr 30 01:28:29 PM PDT 24 |
Apr 30 01:30:35 PM PDT 24 |
2085032329 ps |
| T820 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3775183708 |
|
|
Apr 30 01:16:27 PM PDT 24 |
Apr 30 02:35:24 PM PDT 24 |
122450619707 ps |
| T821 |
/workspace/coverage/default/33.sram_ctrl_alert_test.2075335006 |
|
|
Apr 30 01:23:27 PM PDT 24 |
Apr 30 01:23:28 PM PDT 24 |
24939846 ps |
| T822 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3025603521 |
|
|
Apr 30 01:13:41 PM PDT 24 |
Apr 30 01:14:58 PM PDT 24 |
45417277205 ps |
| T823 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2992459269 |
|
|
Apr 30 01:26:29 PM PDT 24 |
Apr 30 01:32:37 PM PDT 24 |
29798329391 ps |
| T824 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.835609247 |
|
|
Apr 30 01:28:50 PM PDT 24 |
Apr 30 01:30:20 PM PDT 24 |
826245651 ps |
| T825 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.240586533 |
|
|
Apr 30 01:12:30 PM PDT 24 |
Apr 30 01:14:19 PM PDT 24 |
785706788 ps |
| T826 |
/workspace/coverage/default/12.sram_ctrl_smoke.2253230292 |
|
|
Apr 30 01:14:25 PM PDT 24 |
Apr 30 01:14:31 PM PDT 24 |
698492780 ps |
| T827 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.47899726 |
|
|
Apr 30 01:21:19 PM PDT 24 |
Apr 30 01:28:12 PM PDT 24 |
27187023312 ps |
| T828 |
/workspace/coverage/default/29.sram_ctrl_bijection.1004069760 |
|
|
Apr 30 01:21:48 PM PDT 24 |
Apr 30 01:33:43 PM PDT 24 |
33450333256 ps |
| T829 |
/workspace/coverage/default/35.sram_ctrl_bijection.4290567010 |
|
|
Apr 30 01:23:49 PM PDT 24 |
Apr 30 01:56:05 PM PDT 24 |
169316312422 ps |
| T830 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.303198957 |
|
|
Apr 30 01:20:14 PM PDT 24 |
Apr 30 01:20:44 PM PDT 24 |
16437662817 ps |
| T831 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2943123765 |
|
|
Apr 30 01:28:58 PM PDT 24 |
Apr 30 01:29:23 PM PDT 24 |
1149949161 ps |
| T832 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1328196434 |
|
|
Apr 30 01:11:47 PM PDT 24 |
Apr 30 01:15:23 PM PDT 24 |
6392623640 ps |
| T833 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3321616503 |
|
|
Apr 30 01:15:49 PM PDT 24 |
Apr 30 01:16:28 PM PDT 24 |
6948475129 ps |
| T834 |
/workspace/coverage/default/1.sram_ctrl_smoke.4129078852 |
|
|
Apr 30 01:11:01 PM PDT 24 |
Apr 30 01:11:11 PM PDT 24 |
1582437913 ps |
| T835 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.172164630 |
|
|
Apr 30 01:12:13 PM PDT 24 |
Apr 30 01:13:06 PM PDT 24 |
2669043693 ps |
| T836 |
/workspace/coverage/default/18.sram_ctrl_partial_access.3665775619 |
|
|
Apr 30 01:16:52 PM PDT 24 |
Apr 30 01:17:56 PM PDT 24 |
814920266 ps |
| T837 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.1319771728 |
|
|
Apr 30 01:13:29 PM PDT 24 |
Apr 30 01:15:30 PM PDT 24 |
2785869805 ps |
| T838 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1503773762 |
|
|
Apr 30 01:18:05 PM PDT 24 |
Apr 30 01:18:08 PM PDT 24 |
1396955120 ps |
| T839 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.161836290 |
|
|
Apr 30 01:27:07 PM PDT 24 |
Apr 30 01:30:29 PM PDT 24 |
7246217812 ps |
| T840 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2396787934 |
|
|
Apr 30 01:15:28 PM PDT 24 |
Apr 30 01:15:36 PM PDT 24 |
931077044 ps |
| T841 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.25707980 |
|
|
Apr 30 01:17:06 PM PDT 24 |
Apr 30 01:17:09 PM PDT 24 |
351953331 ps |
| T842 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.4168127013 |
|
|
Apr 30 01:28:43 PM PDT 24 |
Apr 30 01:46:27 PM PDT 24 |
47043810020 ps |
| T843 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1831453431 |
|
|
Apr 30 01:18:18 PM PDT 24 |
Apr 30 01:23:08 PM PDT 24 |
16729680879 ps |
| T844 |
/workspace/coverage/default/42.sram_ctrl_bijection.4180478381 |
|
|
Apr 30 01:26:21 PM PDT 24 |
Apr 30 02:10:34 PM PDT 24 |
861921751722 ps |
| T845 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3620242333 |
|
|
Apr 30 01:11:11 PM PDT 24 |
Apr 30 01:13:08 PM PDT 24 |
3198872183 ps |
| T846 |
/workspace/coverage/default/23.sram_ctrl_regwen.258199109 |
|
|
Apr 30 01:19:24 PM PDT 24 |
Apr 30 01:36:08 PM PDT 24 |
61006256661 ps |
| T847 |
/workspace/coverage/default/42.sram_ctrl_regwen.2532885170 |
|
|
Apr 30 01:26:34 PM PDT 24 |
Apr 30 01:32:44 PM PDT 24 |
49204458930 ps |
| T848 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3049792247 |
|
|
Apr 30 01:26:54 PM PDT 24 |
Apr 30 01:54:53 PM PDT 24 |
27274945537 ps |
| T849 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3706789403 |
|
|
Apr 30 01:13:42 PM PDT 24 |
Apr 30 01:14:14 PM PDT 24 |
3275421207 ps |
| T850 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3739360596 |
|
|
Apr 30 01:11:45 PM PDT 24 |
Apr 30 01:34:01 PM PDT 24 |
36142188353 ps |
| T851 |
/workspace/coverage/default/25.sram_ctrl_smoke.1974023444 |
|
|
Apr 30 01:20:05 PM PDT 24 |
Apr 30 01:20:56 PM PDT 24 |
610495725 ps |
| T852 |
/workspace/coverage/default/32.sram_ctrl_partial_access.1880069051 |
|
|
Apr 30 01:22:49 PM PDT 24 |
Apr 30 01:23:07 PM PDT 24 |
1758259694 ps |
| T853 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2071049040 |
|
|
Apr 30 01:18:39 PM PDT 24 |
Apr 30 01:22:32 PM PDT 24 |
15718469018 ps |
| T854 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.539821673 |
|
|
Apr 30 01:18:51 PM PDT 24 |
Apr 30 01:18:55 PM PDT 24 |
681071851 ps |
| T855 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.1313742640 |
|
|
Apr 30 01:21:50 PM PDT 24 |
Apr 30 01:22:13 PM PDT 24 |
2834361230 ps |
| T856 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.316220650 |
|
|
Apr 30 01:11:11 PM PDT 24 |
Apr 30 01:11:15 PM PDT 24 |
1539886314 ps |
| T857 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2772022236 |
|
|
Apr 30 01:19:40 PM PDT 24 |
Apr 30 01:19:55 PM PDT 24 |
1461292933 ps |
| T858 |
/workspace/coverage/default/32.sram_ctrl_alert_test.1525056252 |
|
|
Apr 30 01:23:05 PM PDT 24 |
Apr 30 01:23:06 PM PDT 24 |
29673572 ps |
| T859 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.2770182211 |
|
|
Apr 30 01:28:54 PM PDT 24 |
Apr 30 01:32:50 PM PDT 24 |
4288092716 ps |
| T860 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.520827644 |
|
|
Apr 30 01:13:19 PM PDT 24 |
Apr 30 01:13:23 PM PDT 24 |
1166262353 ps |
| T861 |
/workspace/coverage/default/6.sram_ctrl_bijection.1361749921 |
|
|
Apr 30 01:11:52 PM PDT 24 |
Apr 30 01:38:41 PM PDT 24 |
144751235912 ps |
| T862 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.2355816291 |
|
|
Apr 30 01:24:56 PM PDT 24 |
Apr 30 01:26:03 PM PDT 24 |
4998365933 ps |
| T863 |
/workspace/coverage/default/10.sram_ctrl_regwen.2954117721 |
|
|
Apr 30 01:13:47 PM PDT 24 |
Apr 30 01:22:53 PM PDT 24 |
6564182877 ps |
| T864 |
/workspace/coverage/default/4.sram_ctrl_stress_all.2384015040 |
|
|
Apr 30 01:11:47 PM PDT 24 |
Apr 30 01:53:15 PM PDT 24 |
211552022493 ps |
| T865 |
/workspace/coverage/default/7.sram_ctrl_partial_access.1813524930 |
|
|
Apr 30 01:12:12 PM PDT 24 |
Apr 30 01:14:44 PM PDT 24 |
2196730333 ps |
| T866 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2991329 |
|
|
Apr 30 01:11:23 PM PDT 24 |
Apr 30 01:11:32 PM PDT 24 |
2823372320 ps |
| T867 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.785782728 |
|
|
Apr 30 01:16:34 PM PDT 24 |
Apr 30 01:19:50 PM PDT 24 |
3767003300 ps |
| T868 |
/workspace/coverage/default/39.sram_ctrl_bijection.2115852947 |
|
|
Apr 30 01:25:14 PM PDT 24 |
Apr 30 01:37:19 PM PDT 24 |
203043287475 ps |
| T869 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.1073185841 |
|
|
Apr 30 01:19:41 PM PDT 24 |
Apr 30 01:19:47 PM PDT 24 |
2799158406 ps |
| T870 |
/workspace/coverage/default/3.sram_ctrl_executable.1286295107 |
|
|
Apr 30 01:11:26 PM PDT 24 |
Apr 30 01:28:44 PM PDT 24 |
18486151122 ps |
| T871 |
/workspace/coverage/default/3.sram_ctrl_regwen.1765267981 |
|
|
Apr 30 01:11:25 PM PDT 24 |
Apr 30 01:27:05 PM PDT 24 |
13488218693 ps |
| T872 |
/workspace/coverage/default/8.sram_ctrl_smoke.4100279389 |
|
|
Apr 30 01:12:31 PM PDT 24 |
Apr 30 01:13:41 PM PDT 24 |
798388946 ps |
| T873 |
/workspace/coverage/default/41.sram_ctrl_smoke.540686935 |
|
|
Apr 30 01:26:02 PM PDT 24 |
Apr 30 01:26:15 PM PDT 24 |
2655126939 ps |
| T874 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.2941543322 |
|
|
Apr 30 01:17:33 PM PDT 24 |
Apr 30 01:17:37 PM PDT 24 |
344843419 ps |
| T875 |
/workspace/coverage/default/5.sram_ctrl_bijection.1359106161 |
|
|
Apr 30 01:11:38 PM PDT 24 |
Apr 30 01:38:39 PM PDT 24 |
25497297014 ps |
| T876 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.4148739316 |
|
|
Apr 30 01:14:44 PM PDT 24 |
Apr 30 01:14:48 PM PDT 24 |
681618573 ps |
| T877 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1112127618 |
|
|
Apr 30 01:15:14 PM PDT 24 |
Apr 30 01:17:12 PM PDT 24 |
6247325051 ps |
| T878 |
/workspace/coverage/default/32.sram_ctrl_regwen.2907027213 |
|
|
Apr 30 01:23:01 PM PDT 24 |
Apr 30 01:37:11 PM PDT 24 |
31445319943 ps |
| T879 |
/workspace/coverage/default/0.sram_ctrl_executable.3657053284 |
|
|
Apr 30 01:11:01 PM PDT 24 |
Apr 30 01:21:27 PM PDT 24 |
6855752618 ps |
| T880 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1269090635 |
|
|
Apr 30 01:23:59 PM PDT 24 |
Apr 30 01:33:38 PM PDT 24 |
8438178935 ps |
| T881 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3492203776 |
|
|
Apr 30 01:11:51 PM PDT 24 |
Apr 30 01:25:10 PM PDT 24 |
16180385822 ps |
| T882 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2294995436 |
|
|
Apr 30 01:26:08 PM PDT 24 |
Apr 30 01:35:15 PM PDT 24 |
22482362284 ps |
| T883 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.1410690450 |
|
|
Apr 30 01:22:26 PM PDT 24 |
Apr 30 01:23:05 PM PDT 24 |
1495654801 ps |
| T884 |
/workspace/coverage/default/0.sram_ctrl_smoke.476103627 |
|
|
Apr 30 01:11:05 PM PDT 24 |
Apr 30 01:11:19 PM PDT 24 |
3115851189 ps |
| T885 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2896321686 |
|
|
Apr 30 01:21:46 PM PDT 24 |
Apr 30 01:48:36 PM PDT 24 |
26690424022 ps |
| T886 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.931582931 |
|
|
Apr 30 01:18:27 PM PDT 24 |
Apr 30 01:18:30 PM PDT 24 |
680631073 ps |
| T887 |
/workspace/coverage/default/3.sram_ctrl_stress_all.3327765512 |
|
|
Apr 30 01:11:33 PM PDT 24 |
Apr 30 02:17:03 PM PDT 24 |
227523749808 ps |
| T888 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.317734841 |
|
|
Apr 30 01:16:32 PM PDT 24 |
Apr 30 01:32:55 PM PDT 24 |
15410502005 ps |
| T889 |
/workspace/coverage/default/49.sram_ctrl_smoke.3153358772 |
|
|
Apr 30 01:28:42 PM PDT 24 |
Apr 30 01:29:03 PM PDT 24 |
1311170999 ps |
| T890 |
/workspace/coverage/default/37.sram_ctrl_partial_access.2696916394 |
|
|
Apr 30 01:24:31 PM PDT 24 |
Apr 30 01:25:05 PM PDT 24 |
457027084 ps |
| T891 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.847456499 |
|
|
Apr 30 01:17:05 PM PDT 24 |
Apr 30 01:30:11 PM PDT 24 |
8638748653 ps |
| T892 |
/workspace/coverage/default/46.sram_ctrl_smoke.1559161827 |
|
|
Apr 30 01:27:33 PM PDT 24 |
Apr 30 01:27:52 PM PDT 24 |
1358249592 ps |
| T893 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.3314210670 |
|
|
Apr 30 01:17:55 PM PDT 24 |
Apr 30 01:43:55 PM PDT 24 |
20834847266 ps |
| T894 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3804282091 |
|
|
Apr 30 01:12:33 PM PDT 24 |
Apr 30 01:12:34 PM PDT 24 |
12287654 ps |
| T895 |
/workspace/coverage/default/24.sram_ctrl_smoke.1119424792 |
|
|
Apr 30 01:19:34 PM PDT 24 |
Apr 30 01:19:52 PM PDT 24 |
5402683860 ps |
| T896 |
/workspace/coverage/default/47.sram_ctrl_bijection.765132453 |
|
|
Apr 30 01:28:02 PM PDT 24 |
Apr 30 01:53:34 PM PDT 24 |
96774798105 ps |
| T897 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1090145710 |
|
|
Apr 30 01:26:15 PM PDT 24 |
Apr 30 01:26:19 PM PDT 24 |
2412283187 ps |
| T898 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.487562135 |
|
|
Apr 30 01:14:46 PM PDT 24 |
Apr 30 01:17:11 PM PDT 24 |
6906477886 ps |
| T899 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.1833605419 |
|
|
Apr 30 01:11:39 PM PDT 24 |
Apr 30 01:12:54 PM PDT 24 |
9361416251 ps |
| T900 |
/workspace/coverage/default/8.sram_ctrl_regwen.1196979150 |
|
|
Apr 30 01:12:44 PM PDT 24 |
Apr 30 01:23:21 PM PDT 24 |
8764983725 ps |
| T901 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.30377277 |
|
|
Apr 30 01:22:09 PM PDT 24 |
Apr 30 01:22:21 PM PDT 24 |
3024593303 ps |
| T902 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1185979615 |
|
|
Apr 30 01:21:48 PM PDT 24 |
Apr 30 01:24:49 PM PDT 24 |
5713068862 ps |
| T903 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2789099198 |
|
|
Apr 30 01:26:39 PM PDT 24 |
Apr 30 01:32:00 PM PDT 24 |
5368638378 ps |
| T904 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3105091413 |
|
|
Apr 30 01:12:29 PM PDT 24 |
Apr 30 01:13:01 PM PDT 24 |
1485044573 ps |
| T905 |
/workspace/coverage/default/22.sram_ctrl_executable.510841973 |
|
|
Apr 30 01:18:51 PM PDT 24 |
Apr 30 01:39:16 PM PDT 24 |
21903764460 ps |
| T906 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1668533156 |
|
|
Apr 30 01:23:56 PM PDT 24 |
Apr 30 01:29:40 PM PDT 24 |
5251792981 ps |
| T907 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.490362488 |
|
|
Apr 30 01:11:13 PM PDT 24 |
Apr 30 01:15:08 PM PDT 24 |
3646592151 ps |
| T908 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3009883626 |
|
|
Apr 30 01:16:59 PM PDT 24 |
Apr 30 01:24:14 PM PDT 24 |
72662987385 ps |
| T909 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.1823449283 |
|
|
Apr 30 01:19:09 PM PDT 24 |
Apr 30 01:19:28 PM PDT 24 |
757049931 ps |
| T910 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.155586418 |
|
|
Apr 30 01:23:07 PM PDT 24 |
Apr 30 01:27:49 PM PDT 24 |
4011843380 ps |
| T911 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2017971653 |
|
|
Apr 30 01:26:01 PM PDT 24 |
Apr 30 01:31:00 PM PDT 24 |
2281720012 ps |
| T912 |
/workspace/coverage/default/10.sram_ctrl_bijection.3964844865 |
|
|
Apr 30 01:13:29 PM PDT 24 |
Apr 30 01:58:24 PM PDT 24 |
165581260626 ps |
| T913 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2248271923 |
|
|
Apr 30 01:27:35 PM PDT 24 |
Apr 30 01:27:36 PM PDT 24 |
66235035 ps |
| T914 |
/workspace/coverage/default/18.sram_ctrl_bijection.3364965891 |
|
|
Apr 30 01:16:51 PM PDT 24 |
Apr 30 01:57:45 PM PDT 24 |
632135386190 ps |
| T915 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.513203977 |
|
|
Apr 30 01:11:32 PM PDT 24 |
Apr 30 01:14:00 PM PDT 24 |
10364428903 ps |
| T916 |
/workspace/coverage/default/38.sram_ctrl_bijection.2042258131 |
|
|
Apr 30 01:24:50 PM PDT 24 |
Apr 30 01:40:20 PM PDT 24 |
83332060253 ps |
| T917 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.4266319670 |
|
|
Apr 30 01:28:50 PM PDT 24 |
Apr 30 01:29:02 PM PDT 24 |
1382590048 ps |
| T918 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3253708572 |
|
|
Apr 30 01:11:04 PM PDT 24 |
Apr 30 02:21:01 PM PDT 24 |
133592719129 ps |
| T919 |
/workspace/coverage/default/7.sram_ctrl_smoke.2077241831 |
|
|
Apr 30 01:12:07 PM PDT 24 |
Apr 30 01:12:14 PM PDT 24 |
683293320 ps |
| T920 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.2247778978 |
|
|
Apr 30 01:14:42 PM PDT 24 |
Apr 30 01:14:51 PM PDT 24 |
2905816483 ps |
| T921 |
/workspace/coverage/default/14.sram_ctrl_smoke.3971738277 |
|
|
Apr 30 01:15:14 PM PDT 24 |
Apr 30 01:16:09 PM PDT 24 |
770098235 ps |
| T922 |
/workspace/coverage/default/26.sram_ctrl_partial_access.3654338592 |
|
|
Apr 30 01:20:28 PM PDT 24 |
Apr 30 01:20:45 PM PDT 24 |
893307411 ps |
| T923 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.4271662178 |
|
|
Apr 30 01:20:17 PM PDT 24 |
Apr 30 01:21:32 PM PDT 24 |
2355019356 ps |
| T924 |
/workspace/coverage/default/20.sram_ctrl_bijection.1772338269 |
|
|
Apr 30 01:17:47 PM PDT 24 |
Apr 30 01:28:10 PM PDT 24 |
9611343210 ps |
| T925 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.284740182 |
|
|
Apr 30 01:15:54 PM PDT 24 |
Apr 30 01:18:20 PM PDT 24 |
28712515444 ps |
| T926 |
/workspace/coverage/default/47.sram_ctrl_executable.642631621 |
|
|
Apr 30 01:28:08 PM PDT 24 |
Apr 30 01:32:06 PM PDT 24 |
4473640449 ps |
| T927 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.298610323 |
|
|
Apr 30 01:25:28 PM PDT 24 |
Apr 30 01:26:41 PM PDT 24 |
21890695816 ps |
| T928 |
/workspace/coverage/default/36.sram_ctrl_executable.2475025399 |
|
|
Apr 30 01:24:16 PM PDT 24 |
Apr 30 01:41:23 PM PDT 24 |
8708716017 ps |
| T929 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1076742061 |
|
|
Apr 30 01:21:09 PM PDT 24 |
Apr 30 01:22:11 PM PDT 24 |
951479338 ps |
| T930 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2415798202 |
|
|
Apr 30 01:28:35 PM PDT 24 |
Apr 30 01:29:36 PM PDT 24 |
4104800989 ps |
| T931 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.3905898004 |
|
|
Apr 30 01:15:59 PM PDT 24 |
Apr 30 01:48:20 PM PDT 24 |
22388988238 ps |
| T932 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.2509599255 |
|
|
Apr 30 01:23:07 PM PDT 24 |
Apr 30 01:42:09 PM PDT 24 |
17410000684 ps |
| T933 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2624328429 |
|
|
Apr 30 01:18:46 PM PDT 24 |
Apr 30 01:20:19 PM PDT 24 |
52635848984 ps |
| T934 |
/workspace/coverage/default/9.sram_ctrl_regwen.1114428022 |
|
|
Apr 30 01:13:18 PM PDT 24 |
Apr 30 01:23:30 PM PDT 24 |
16879617586 ps |
| T935 |
/workspace/coverage/default/0.sram_ctrl_bijection.3679364085 |
|
|
Apr 30 01:11:03 PM PDT 24 |
Apr 30 01:51:33 PM PDT 24 |
460437749862 ps |
| T936 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2677582313 |
|
|
Apr 30 01:28:42 PM PDT 24 |
Apr 30 01:30:56 PM PDT 24 |
2647865181 ps |
| T937 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2242436074 |
|
|
Apr 30 01:19:26 PM PDT 24 |
Apr 30 02:12:44 PM PDT 24 |
1820951042756 ps |
| T938 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.429252091 |
|
|
Apr 30 01:25:46 PM PDT 24 |
Apr 30 01:25:54 PM PDT 24 |
2831226275 ps |
| T939 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.932250620 |
|
|
Apr 30 01:25:55 PM PDT 24 |
Apr 30 01:26:30 PM PDT 24 |
19115551865 ps |
| T940 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3973582618 |
|
|
Apr 30 01:24:36 PM PDT 24 |
Apr 30 01:48:48 PM PDT 24 |
51709424699 ps |
| T941 |
/workspace/coverage/default/12.sram_ctrl_bijection.1080726767 |
|
|
Apr 30 01:14:27 PM PDT 24 |
Apr 30 01:51:02 PM PDT 24 |
354296607264 ps |
| T942 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3357546083 |
|
|
Apr 30 01:28:09 PM PDT 24 |
Apr 30 01:28:13 PM PDT 24 |
381321624 ps |
| T943 |
/workspace/coverage/default/14.sram_ctrl_alert_test.49575333 |
|
|
Apr 30 01:15:38 PM PDT 24 |
Apr 30 01:15:39 PM PDT 24 |
43458580 ps |
| T944 |
/workspace/coverage/default/46.sram_ctrl_regwen.2336263585 |
|
|
Apr 30 01:27:43 PM PDT 24 |
Apr 30 01:37:52 PM PDT 24 |
74416993462 ps |
| T98 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1143148861 |
|
|
Apr 30 12:44:16 PM PDT 24 |
Apr 30 12:44:17 PM PDT 24 |
22788029 ps |
| T99 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3278893219 |
|
|
Apr 30 12:44:26 PM PDT 24 |
Apr 30 12:45:28 PM PDT 24 |
70414974492 ps |
| T945 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3748444343 |
|
|
Apr 30 12:44:10 PM PDT 24 |
Apr 30 12:44:14 PM PDT 24 |
695366915 ps |
| T100 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1179299663 |
|
|
Apr 30 12:44:49 PM PDT 24 |
Apr 30 12:44:50 PM PDT 24 |
158278201 ps |
| T66 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1028828945 |
|
|
Apr 30 12:44:41 PM PDT 24 |
Apr 30 12:44:42 PM PDT 24 |
47787707 ps |
| T946 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1596550113 |
|
|
Apr 30 12:44:19 PM PDT 24 |
Apr 30 12:44:23 PM PDT 24 |
1418654815 ps |
| T947 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.894844475 |
|
|
Apr 30 12:44:30 PM PDT 24 |
Apr 30 12:44:32 PM PDT 24 |
90818266 ps |
| T105 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2987672060 |
|
|
Apr 30 12:44:17 PM PDT 24 |
Apr 30 12:44:19 PM PDT 24 |
878870581 ps |
| T67 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.340216776 |
|
|
Apr 30 12:44:12 PM PDT 24 |
Apr 30 12:44:13 PM PDT 24 |
39621555 ps |
| T68 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.410002557 |
|
|
Apr 30 12:44:35 PM PDT 24 |
Apr 30 12:44:36 PM PDT 24 |
31046176 ps |
| T106 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.86986035 |
|
|
Apr 30 12:44:38 PM PDT 24 |
Apr 30 12:44:41 PM PDT 24 |
162696214 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3987658086 |
|
|
Apr 30 12:44:43 PM PDT 24 |
Apr 30 12:44:47 PM PDT 24 |
380344318 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.935172324 |
|
|
Apr 30 12:44:23 PM PDT 24 |
Apr 30 12:44:27 PM PDT 24 |
1423907706 ps |
| T69 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2032075758 |
|
|
Apr 30 12:44:52 PM PDT 24 |
Apr 30 12:45:20 PM PDT 24 |
3859452515 ps |
| T70 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.160689012 |
|
|
Apr 30 12:44:49 PM PDT 24 |
Apr 30 12:45:40 PM PDT 24 |
8292841971 ps |
| T71 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2866719570 |
|
|
Apr 30 12:44:28 PM PDT 24 |
Apr 30 12:44:30 PM PDT 24 |
17638858 ps |
| T107 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1384733837 |
|
|
Apr 30 12:44:48 PM PDT 24 |
Apr 30 12:44:50 PM PDT 24 |
91812453 ps |
| T123 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.29466331 |
|
|
Apr 30 12:44:17 PM PDT 24 |
Apr 30 12:44:19 PM PDT 24 |
323925403 ps |
| T101 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1730979328 |
|
|
Apr 30 12:44:28 PM PDT 24 |
Apr 30 12:44:29 PM PDT 24 |
27175850 ps |
| T122 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3096942157 |
|
|
Apr 30 12:44:12 PM PDT 24 |
Apr 30 12:44:14 PM PDT 24 |
326591846 ps |
| T950 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1788679038 |
|
|
Apr 30 12:44:49 PM PDT 24 |
Apr 30 12:44:53 PM PDT 24 |
139537517 ps |
| T951 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.829161931 |
|
|
Apr 30 12:44:34 PM PDT 24 |
Apr 30 12:44:39 PM PDT 24 |
140721158 ps |
| T72 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1365266329 |
|
|
Apr 30 12:44:27 PM PDT 24 |
Apr 30 12:44:28 PM PDT 24 |
13016793 ps |
| T73 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1943861571 |
|
|
Apr 30 12:44:20 PM PDT 24 |
Apr 30 12:44:49 PM PDT 24 |
14771298319 ps |
| T952 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.846621187 |
|
|
Apr 30 12:44:49 PM PDT 24 |
Apr 30 12:44:53 PM PDT 24 |
368287204 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1147966909 |
|
|
Apr 30 12:44:52 PM PDT 24 |
Apr 30 12:44:58 PM PDT 24 |
1352401360 ps |
| T121 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3615704387 |
|
|
Apr 30 12:44:42 PM PDT 24 |
Apr 30 12:44:44 PM PDT 24 |
1908241157 ps |
| T74 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2882508981 |
|
|
Apr 30 12:44:23 PM PDT 24 |
Apr 30 12:44:24 PM PDT 24 |
48166186 ps |
| T75 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1720891939 |
|
|
Apr 30 12:44:41 PM PDT 24 |
Apr 30 12:44:42 PM PDT 24 |
17627385 ps |
| T954 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2738898920 |
|
|
Apr 30 12:44:27 PM PDT 24 |
Apr 30 12:44:28 PM PDT 24 |
16636426 ps |
| T955 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3693482502 |
|
|
Apr 30 12:44:49 PM PDT 24 |
Apr 30 12:44:53 PM PDT 24 |
712129641 ps |
| T132 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.639086741 |
|
|
Apr 30 12:44:16 PM PDT 24 |
Apr 30 12:44:19 PM PDT 24 |
1752831076 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.305430148 |
|
|
Apr 30 12:44:23 PM PDT 24 |
Apr 30 12:44:26 PM PDT 24 |
301794209 ps |
| T957 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.716713598 |
|
|
Apr 30 12:44:29 PM PDT 24 |
Apr 30 12:44:34 PM PDT 24 |
1995033644 ps |
| T958 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3898599344 |
|
|
Apr 30 12:44:49 PM PDT 24 |
Apr 30 12:44:50 PM PDT 24 |
45154055 ps |
| T79 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2260671548 |
|
|
Apr 30 12:44:50 PM PDT 24 |
Apr 30 12:45:45 PM PDT 24 |
14349225381 ps |
| T80 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1775708546 |
|
|
Apr 30 12:44:20 PM PDT 24 |
Apr 30 12:44:21 PM PDT 24 |
32716470 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3272757335 |
|
|
Apr 30 12:44:20 PM PDT 24 |
Apr 30 12:44:22 PM PDT 24 |
115250798 ps |
| T960 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.337194802 |
|
|
Apr 30 12:44:36 PM PDT 24 |
Apr 30 12:44:37 PM PDT 24 |
64815063 ps |
| T961 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3660731094 |
|
|
Apr 30 12:44:48 PM PDT 24 |
Apr 30 12:44:49 PM PDT 24 |
15874686 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.356569607 |
|
|
Apr 30 12:44:27 PM PDT 24 |
Apr 30 12:44:31 PM PDT 24 |
376523962 ps |
| T963 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.661479120 |
|
|
Apr 30 12:44:51 PM PDT 24 |
Apr 30 12:44:55 PM PDT 24 |
360275517 ps |
| T964 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1328915368 |
|
|
Apr 30 12:44:33 PM PDT 24 |
Apr 30 12:44:34 PM PDT 24 |
40169846 ps |
| T965 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3348367164 |
|
|
Apr 30 12:44:11 PM PDT 24 |
Apr 30 12:44:13 PM PDT 24 |
776958733 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.572724072 |
|
|
Apr 30 12:44:26 PM PDT 24 |
Apr 30 12:44:30 PM PDT 24 |
745678102 ps |
| T81 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2193038418 |
|
|
Apr 30 12:44:43 PM PDT 24 |
Apr 30 12:44:45 PM PDT 24 |
15287989 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3316076568 |
|
|
Apr 30 12:44:11 PM PDT 24 |
Apr 30 12:44:38 PM PDT 24 |
3726496816 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2092959455 |
|
|
Apr 30 12:44:19 PM PDT 24 |
Apr 30 12:44:21 PM PDT 24 |
138770595 ps |
| T968 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3901528710 |
|
|
Apr 30 12:44:49 PM PDT 24 |
Apr 30 12:44:50 PM PDT 24 |
26949217 ps |
| T969 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.979109993 |
|
|
Apr 30 12:44:25 PM PDT 24 |
Apr 30 12:44:28 PM PDT 24 |
189538393 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.614981536 |
|
|
Apr 30 12:44:10 PM PDT 24 |
Apr 30 12:44:11 PM PDT 24 |
27338935 ps |
| T971 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.343896228 |
|
|
Apr 30 12:44:50 PM PDT 24 |
Apr 30 12:44:52 PM PDT 24 |
91035689 ps |
| T972 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3942783724 |
|
|
Apr 30 12:44:48 PM PDT 24 |
Apr 30 12:44:52 PM PDT 24 |
364633863 ps |
| T973 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1550869587 |
|
|
Apr 30 12:44:27 PM PDT 24 |
Apr 30 12:44:32 PM PDT 24 |
1425709658 ps |
| T93 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1275318227 |
|
|
Apr 30 12:44:26 PM PDT 24 |
Apr 30 12:44:53 PM PDT 24 |
3876116659 ps |
| T126 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.133887131 |
|
|
Apr 30 12:44:36 PM PDT 24 |
Apr 30 12:44:39 PM PDT 24 |
818370992 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2015067467 |
|
|
Apr 30 12:44:07 PM PDT 24 |
Apr 30 12:44:08 PM PDT 24 |
10524353 ps |
| T975 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1249114371 |
|
|
Apr 30 12:44:41 PM PDT 24 |
Apr 30 12:44:46 PM PDT 24 |
297183595 ps |
| T976 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2660664497 |
|
|
Apr 30 12:44:42 PM PDT 24 |
Apr 30 12:45:09 PM PDT 24 |
3854089681 ps |
| T977 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.923147571 |
|
|
Apr 30 12:44:33 PM PDT 24 |
Apr 30 12:44:37 PM PDT 24 |
1469193862 ps |
| T978 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.395594071 |
|
|
Apr 30 12:44:17 PM PDT 24 |
Apr 30 12:44:18 PM PDT 24 |
15433007 ps |
| T94 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3675060406 |
|
|
Apr 30 12:44:28 PM PDT 24 |
Apr 30 12:44:58 PM PDT 24 |
7699028993 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2229872409 |
|
|
Apr 30 12:44:11 PM PDT 24 |
Apr 30 12:44:12 PM PDT 24 |
24582733 ps |
| T979 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2442502629 |
|
|
Apr 30 12:44:50 PM PDT 24 |
Apr 30 12:44:51 PM PDT 24 |
28790097 ps |
| T87 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1499260709 |
|
|
Apr 30 12:44:33 PM PDT 24 |
Apr 30 12:45:27 PM PDT 24 |
29318066395 ps |
| T980 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.985489752 |
|
|
Apr 30 12:44:30 PM PDT 24 |
Apr 30 12:44:34 PM PDT 24 |
37904069 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.202007498 |
|
|
Apr 30 12:44:17 PM PDT 24 |
Apr 30 12:44:18 PM PDT 24 |
28116830 ps |
| T131 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1242041019 |
|
|
Apr 30 12:44:09 PM PDT 24 |
Apr 30 12:44:12 PM PDT 24 |
139439479 ps |
| T982 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2933872052 |
|
|
Apr 30 12:44:42 PM PDT 24 |
Apr 30 12:44:43 PM PDT 24 |
43961905 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2847835318 |
|
|
Apr 30 12:44:11 PM PDT 24 |
Apr 30 12:44:15 PM PDT 24 |
60367349 ps |
| T984 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2678292186 |
|
|
Apr 30 12:44:35 PM PDT 24 |
Apr 30 12:44:39 PM PDT 24 |
363408802 ps |
| T985 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2207387002 |
|
|
Apr 30 12:44:41 PM PDT 24 |
Apr 30 12:44:44 PM PDT 24 |
268390715 ps |
| T986 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2678346458 |
|
|
Apr 30 12:44:12 PM PDT 24 |
Apr 30 12:44:13 PM PDT 24 |
13523868 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2396192579 |
|
|
Apr 30 12:44:08 PM PDT 24 |
Apr 30 12:44:09 PM PDT 24 |
29379900 ps |
| T988 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2214299985 |
|
|
Apr 30 12:44:35 PM PDT 24 |
Apr 30 12:44:36 PM PDT 24 |
44249713 ps |
| T989 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1635277733 |
|
|
Apr 30 12:44:27 PM PDT 24 |
Apr 30 12:44:29 PM PDT 24 |
46497708 ps |
| T88 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1920675506 |
|
|
Apr 30 12:44:33 PM PDT 24 |
Apr 30 12:45:20 PM PDT 24 |
14733657144 ps |
| T127 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3641873463 |
|
|
Apr 30 12:44:28 PM PDT 24 |
Apr 30 12:44:31 PM PDT 24 |
518307244 ps |
| T89 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3436966797 |
|
|
Apr 30 12:44:35 PM PDT 24 |
Apr 30 12:44:36 PM PDT 24 |
12798153 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3308417542 |
|
|
Apr 30 12:44:16 PM PDT 24 |
Apr 30 12:44:17 PM PDT 24 |
29477443 ps |
| T991 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3460240255 |
|
|
Apr 30 12:44:11 PM PDT 24 |
Apr 30 12:44:15 PM PDT 24 |
121515297 ps |
| T992 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1462725623 |
|
|
Apr 30 12:44:18 PM PDT 24 |
Apr 30 12:44:20 PM PDT 24 |
127034240 ps |
| T129 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1256844497 |
|
|
Apr 30 12:44:29 PM PDT 24 |
Apr 30 12:44:31 PM PDT 24 |
191043100 ps |
| T90 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4204459701 |
|
|
Apr 30 12:44:21 PM PDT 24 |
Apr 30 12:44:22 PM PDT 24 |
14889322 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3057037328 |
|
|
Apr 30 12:44:12 PM PDT 24 |
Apr 30 12:44:15 PM PDT 24 |
711657787 ps |
| T91 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1926032260 |
|
|
Apr 30 12:44:29 PM PDT 24 |
Apr 30 12:44:57 PM PDT 24 |
7638476031 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.402590811 |
|
|
Apr 30 12:44:06 PM PDT 24 |
Apr 30 12:44:33 PM PDT 24 |
15405116511 ps |
| T995 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2598889256 |
|
|
Apr 30 12:44:29 PM PDT 24 |
Apr 30 12:44:30 PM PDT 24 |
27159144 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.631468303 |
|
|
Apr 30 12:44:27 PM PDT 24 |
Apr 30 12:44:28 PM PDT 24 |
21734543 ps |
| T997 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2613970170 |
|
|
Apr 30 12:44:43 PM PDT 24 |
Apr 30 12:44:48 PM PDT 24 |
1309991972 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1727284099 |
|
|
Apr 30 12:44:20 PM PDT 24 |
Apr 30 12:44:21 PM PDT 24 |
168730102 ps |
| T999 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.943565667 |
|
|
Apr 30 12:44:10 PM PDT 24 |
Apr 30 12:44:13 PM PDT 24 |
295022010 ps |
| T1000 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2255842627 |
|
|
Apr 30 12:44:35 PM PDT 24 |
Apr 30 12:44:36 PM PDT 24 |
27802554 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.62124167 |
|
|
Apr 30 12:44:20 PM PDT 24 |
Apr 30 12:44:25 PM PDT 24 |
499103921 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.631951347 |
|
|
Apr 30 12:44:21 PM PDT 24 |
Apr 30 12:44:26 PM PDT 24 |
139583665 ps |
| T1003 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.551291085 |
|
|
Apr 30 12:44:26 PM PDT 24 |
Apr 30 12:44:30 PM PDT 24 |
1365479807 ps |
| T1004 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.358634662 |
|
|
Apr 30 12:44:11 PM PDT 24 |
Apr 30 12:44:12 PM PDT 24 |
50324119 ps |