Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16624136	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150285216

1

T1

1662

T2

12166

T3

1136

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82173306	1			T1	16057		T2	4051		T3	3172
values[0x0]	40712896	1			T1	5240		T2	4292		T3	1050
values[0x1]	44023150	1			T1	11258		T2	4185		T3	2023

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8439870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158469482

1

T1

14852

T2

12346

T3

3694

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	677422	1			T2	51		T8	5043		T11	870
valid_sources[0x01]	499020	1			T1	143		T2	46		T8	4864
valid_sources[0x02]	527208	1			T1	846		T2	72		T7	6
valid_sources[0x03]	594476	1			T2	63		T8	4837		T11	889
valid_sources[0x04]	510304	1			T2	45		T8	4969		T11	934
valid_sources[0x05]	528658	1			T1	330		T2	29		T8	4854
valid_sources[0x06]	563059	1			T1	154		T2	38		T8	4806
valid_sources[0x07]	519131	1			T1	660		T2	44		T8	5006
valid_sources[0x08]	1030980	1			T1	46		T2	33		T8	4695
valid_sources[0x09]	503634	1			T2	44		T8	5089		T11	989
valid_sources[0x0a]	1234560	1			T1	1469		T2	39		T8	4906
valid_sources[0x0b]	577588	1			T2	56		T8	4757		T11	806
valid_sources[0x0c]	556624	1			T2	37		T7	3		T8	5008
valid_sources[0x0d]	526375	1			T2	55		T8	4869		T11	796
valid_sources[0x0e]	536042	1			T2	47		T8	5138		T11	1140
valid_sources[0x0f]	560530	1			T2	58		T8	4721		T11	968
valid_sources[0x10]	590629	1			T2	63		T8	5009		T11	900
valid_sources[0x11]	539619	1			T2	36		T7	2		T8	4949
valid_sources[0x12]	511309	1			T2	49		T8	4776		T11	1123
valid_sources[0x13]	509309	1			T1	74		T2	46		T7	4
valid_sources[0x14]	524611	1			T1	336		T2	31		T7	7
valid_sources[0x15]	515937	1			T1	211		T2	135		T8	4872
valid_sources[0x16]	579060	1			T1	801		T2	65		T7	1
valid_sources[0x17]	520547	1			T2	42		T8	4778		T11	958
valid_sources[0x18]	516667	1			T1	175		T2	58		T8	5002
valid_sources[0x19]	569816	1			T2	69		T8	4692		T11	1021
valid_sources[0x1a]	518244	1			T2	33		T7	3		T8	4848
valid_sources[0x1b]	519809	1			T2	34		T8	5005		T11	899
valid_sources[0x1c]	556967	1			T1	862		T2	45		T8	5020
valid_sources[0x1d]	551157	1			T1	221		T2	55		T8	4961
valid_sources[0x1e]	540431	1			T2	71		T7	7		T8	4866
valid_sources[0x1f]	509942	1			T1	88		T2	59		T7	1
valid_sources[0x20]	525997	1			T2	43		T7	5		T8	4552
valid_sources[0x21]	594176	1			T2	32		T8	4729		T11	884
valid_sources[0x22]	521881	1			T2	19		T7	5		T8	5071
valid_sources[0x23]	542328	1			T1	33		T2	45		T3	3136
valid_sources[0x24]	519492	1			T2	57		T3	3109		T7	8
valid_sources[0x25]	534463	1			T2	53		T8	4892		T11	1173
valid_sources[0x26]	538389	1			T1	25		T2	50		T8	4984
valid_sources[0x27]	577365	1			T2	69		T7	4		T8	4921
valid_sources[0x28]	578036	1			T2	66		T7	8		T8	4595
valid_sources[0x29]	548666	1			T2	41		T8	4759		T11	930
valid_sources[0x2a]	517054	1			T1	138		T2	71		T8	4972
valid_sources[0x2b]	526244	1			T2	36		T8	4841		T11	932
valid_sources[0x2c]	532905	1			T2	38		T8	4879		T11	837
valid_sources[0x2d]	1528588	1			T1	458		T2	30		T8	4886
valid_sources[0x2e]	525795	1			T1	101		T2	59		T7	6
valid_sources[0x2f]	538275	1			T1	98		T2	46		T8	4948
valid_sources[0x30]	516286	1			T2	62		T7	6		T8	4795
valid_sources[0x31]	2581978	1			T1	335		T2	54		T8	4952
valid_sources[0x32]	2780471	1			T2	47		T7	21		T8	4876
valid_sources[0x33]	659102	1			T2	78		T7	14		T8	5083
valid_sources[0x34]	524652	1			T2	27		T8	4928		T11	915
valid_sources[0x35]	1698254	1			T1	427		T2	35		T7	2
valid_sources[0x36]	523460	1			T1	419		T2	54		T7	2
valid_sources[0x37]	576007	1			T1	119		T2	65		T7	2
valid_sources[0x38]	508303	1			T1	89		T2	53		T7	5
valid_sources[0x39]	558160	1			T2	35		T8	4598		T11	1047
valid_sources[0x3a]	540848	1			T2	41		T8	4956		T11	947
valid_sources[0x3b]	539573	1			T2	24		T8	4928		T11	917
valid_sources[0x3c]	508026	1			T2	62		T8	4933		T11	1153
valid_sources[0x3d]	517276	1			T1	27		T2	51		T8	4794
valid_sources[0x3e]	529538	1			T2	62		T7	9		T8	4808
valid_sources[0x3f]	523797	1			T2	36		T8	4948		T11	814
valid_sources[0x40]	1997160	1			T1	903		T2	49		T8	4817
valid_sources[0x41]	525513	1			T2	39		T8	4885		T11	914
valid_sources[0x42]	594647	1			T2	65		T8	4862		T11	925
valid_sources[0x43]	534164	1			T1	56		T2	58		T8	5113
valid_sources[0x44]	504881	1			T2	51		T7	7		T8	4937
valid_sources[0x45]	589793	1			T1	393		T2	53		T7	14
valid_sources[0x46]	528197	1			T2	15		T8	4892		T11	858
valid_sources[0x47]	588630	1			T1	527		T2	66		T7	7
valid_sources[0x48]	1814821	1			T2	45		T8	4746		T11	1013
valid_sources[0x49]	555114	1			T2	53		T8	4692		T11	847
valid_sources[0x4a]	541648	1			T2	39		T7	6		T8	4659
valid_sources[0x4b]	523106	1			T1	15		T2	69		T7	2
valid_sources[0x4c]	530959	1			T2	14		T8	4917		T11	889
valid_sources[0x4d]	516459	1			T1	20		T2	44		T7	4
valid_sources[0x4e]	535725	1			T2	61		T8	4853		T11	953
valid_sources[0x4f]	808152	1			T1	36		T2	70		T8	4796
valid_sources[0x50]	543942	1			T2	87		T8	4861		T11	921
valid_sources[0x51]	501880	1			T1	220		T2	33		T8	4845
valid_sources[0x52]	1721741	1			T2	53		T8	4872		T11	915
valid_sources[0x53]	502560	1			T1	260		T2	60		T8	4706
valid_sources[0x54]	561408	1			T1	36		T2	51		T7	5
valid_sources[0x55]	533602	1			T1	763		T2	34		T8	4962
valid_sources[0x56]	541977	1			T1	284		T2	68		T7	5
valid_sources[0x57]	1031062	1			T1	280		T2	76		T7	6
valid_sources[0x58]	504708	1			T2	52		T7	5		T8	4857
valid_sources[0x59]	582520	1			T2	32		T7	9		T8	4878
valid_sources[0x5a]	563158	1			T1	34		T2	31		T7	4
valid_sources[0x5b]	538476	1			T2	35		T8	4810		T11	941
valid_sources[0x5c]	510456	1			T1	61		T2	36		T8	5018
valid_sources[0x5d]	531407	1			T2	32		T8	4832		T11	902
valid_sources[0x5e]	555631	1			T1	131		T2	49		T8	4776
valid_sources[0x5f]	632323	1			T2	46		T8	4801		T11	765
valid_sources[0x60]	515934	1			T2	40		T8	4785		T11	889
valid_sources[0x61]	507354	1			T1	520		T2	63		T8	4757
valid_sources[0x62]	595090	1			T2	32		T8	4703		T11	947
valid_sources[0x63]	511865	1			T1	621		T2	48		T7	6
valid_sources[0x64]	600726	1			T2	26		T8	4887		T11	856
valid_sources[0x65]	602381	1			T1	783		T2	41		T7	2
valid_sources[0x66]	689811	1			T2	54		T7	1		T8	4818
valid_sources[0x67]	510612	1			T2	56		T7	6		T8	4791
valid_sources[0x68]	555009	1			T2	40		T8	4839		T11	944
valid_sources[0x69]	574386	1			T2	60		T7	6		T8	5063
valid_sources[0x6a]	552830	1			T1	43		T2	70		T8	4915
valid_sources[0x6b]	501767	1			T2	39		T8	4937		T11	978
valid_sources[0x6c]	544219	1			T2	39		T8	4840		T11	1062
valid_sources[0x6d]	529724	1			T1	486		T2	45		T7	5
valid_sources[0x6e]	518964	1			T2	39		T7	3		T8	4818
valid_sources[0x6f]	537811	1			T1	221		T2	46		T7	7
valid_sources[0x70]	523743	1			T2	26		T8	4838		T11	982
valid_sources[0x71]	566624	1			T2	39		T8	4754		T11	960
valid_sources[0x72]	572983	1			T2	74		T8	4686		T11	789
valid_sources[0x73]	515498	1			T1	412		T2	44		T7	12
valid_sources[0x74]	521425	1			T1	1419		T2	54		T8	4842
valid_sources[0x75]	512134	1			T2	45		T7	7		T8	5045
valid_sources[0x76]	572301	1			T1	10		T2	63		T8	4694
valid_sources[0x77]	510551	1			T2	20		T8	4770		T11	982
valid_sources[0x78]	496540	1			T2	53		T7	1		T8	4739
valid_sources[0x79]	1055417	1			T2	40		T8	4956		T11	849
valid_sources[0x7a]	554868	1			T2	61		T8	4889		T11	747
valid_sources[0x7b]	599600	1			T1	869		T2	17		T7	5
valid_sources[0x7c]	516023	1			T2	57		T8	4901		T11	760
valid_sources[0x7d]	568360	1			T1	286		T2	37		T8	4921
valid_sources[0x7e]	511172	1			T2	57		T7	4		T8	4825
valid_sources[0x7f]	1942593	1			T2	54		T7	10		T8	4983
valid_sources[0x80]	531372	1			T2	55		T7	9		T8	4856

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73819148

1

T1

129

T2

3865

T3

582

values[0x0]

all_enables

biggest_size

38231778

1

T1

796

T2

4234

T3

292

values[0x1]

all_enables

biggest_size

38234290

1

T1

737

T2

4067

T3

262

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

158060

1

T2

3679

T7

1

T8

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56131	1			T2	1034		T4	25		T5	14
values[0x0]	66411	1			T2	1370		T7	1		T8	12
values[0x1]	71100	1			T1	1		T2	1524		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

166794

1

T2

3806

T7

1

T8

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	686	1			T2	14		T4	1		T16	1
valid_sources[0x01]	827	1			T2	13		T4	1		T16	8
valid_sources[0x02]	560	1			T2	15		T16	8		T30	29
valid_sources[0x03]	995	1			T2	15		T18	1		T16	4
valid_sources[0x04]	761	1			T2	14		T4	1		T16	2
valid_sources[0x05]	603	1			T2	9		T16	1		T30	37
valid_sources[0x06]	822	1			T2	15		T16	8		T30	40
valid_sources[0x07]	829	1			T2	12		T16	2		T30	16
valid_sources[0x08]	663	1			T2	17		T4	1		T16	4
valid_sources[0x09]	735	1			T2	16		T16	3		T30	30
valid_sources[0x0a]	575	1			T2	16		T16	10		T30	22
valid_sources[0x0b]	700	1			T2	14		T16	6		T30	22
valid_sources[0x0c]	767	1			T2	20		T16	4		T30	38
valid_sources[0x0d]	709	1			T2	24		T8	19		T18	1
valid_sources[0x0e]	766	1			T2	18		T16	2		T30	16
valid_sources[0x0f]	661	1			T2	19		T16	4		T30	25
valid_sources[0x10]	533	1			T2	19		T16	8		T30	15
valid_sources[0x11]	556	1			T2	18		T92	1		T16	2
valid_sources[0x12]	1046	1			T2	11		T25	1		T16	7
valid_sources[0x13]	768	1			T2	14		T4	2		T16	5
valid_sources[0x14]	1069	1			T2	12		T4	1		T16	3
valid_sources[0x15]	680	1			T2	9		T16	9		T46	3
valid_sources[0x16]	739	1			T2	16		T16	5		T30	13
valid_sources[0x17]	614	1			T2	19		T16	5		T30	21
valid_sources[0x18]	609	1			T2	16		T12	6		T4	1
valid_sources[0x19]	796	1			T2	14		T16	7		T30	20
valid_sources[0x1a]	842	1			T2	15		T16	6		T30	17
valid_sources[0x1b]	757	1			T2	22		T16	5		T46	2
valid_sources[0x1c]	992	1			T2	19		T16	3		T62	1
valid_sources[0x1d]	624	1			T2	24		T16	2		T30	13
valid_sources[0x1e]	630	1			T2	15		T10	1		T16	11
valid_sources[0x1f]	678	1			T2	13		T16	2		T30	33
valid_sources[0x20]	658	1			T2	14		T16	10		T30	9
valid_sources[0x21]	1175	1			T2	15		T16	13		T30	25
valid_sources[0x22]	558	1			T2	16		T4	1		T16	3
valid_sources[0x23]	638	1			T2	18		T16	8		T30	50
valid_sources[0x24]	865	1			T2	17		T16	10		T30	16
valid_sources[0x25]	758	1			T2	18		T16	10		T30	21
valid_sources[0x26]	1064	1			T2	11		T18	1		T21	1
valid_sources[0x27]	824	1			T2	18		T9	2		T21	1
valid_sources[0x28]	768	1			T2	22		T16	5		T30	28
valid_sources[0x29]	598	1			T2	10		T16	6		T30	20
valid_sources[0x2a]	1051	1			T2	13		T4	2		T16	4
valid_sources[0x2b]	747	1			T2	21		T4	1		T16	4
valid_sources[0x2c]	601	1			T2	23		T16	2		T30	23
valid_sources[0x2d]	654	1			T2	11		T16	12		T30	28
valid_sources[0x2e]	570	1			T2	11		T16	6		T30	12
valid_sources[0x2f]	717	1			T2	10		T4	1		T16	5
valid_sources[0x30]	885	1			T2	14		T21	1		T14	3
valid_sources[0x31]	670	1			T1	1		T2	12		T16	4
valid_sources[0x32]	684	1			T2	26		T16	8		T30	14
valid_sources[0x33]	868	1			T2	15		T18	1		T16	2
valid_sources[0x34]	824	1			T2	18		T11	2		T4	1
valid_sources[0x35]	841	1			T2	6		T16	6		T30	33
valid_sources[0x36]	756	1			T2	15		T16	7		T30	28
valid_sources[0x37]	678	1			T2	17		T16	5		T62	1
valid_sources[0x38]	656	1			T2	13		T16	2		T30	39
valid_sources[0x39]	646	1			T2	17		T30	25		T49	10
valid_sources[0x3a]	711	1			T2	15		T21	5		T4	1
valid_sources[0x3b]	1108	1			T2	15		T16	6		T30	30
valid_sources[0x3c]	616	1			T2	13		T16	3		T30	34
valid_sources[0x3d]	737	1			T2	18		T10	1		T16	3
valid_sources[0x3e]	1052	1			T2	16		T16	4		T30	33
valid_sources[0x3f]	902	1			T2	19		T16	2		T30	25
valid_sources[0x40]	898	1			T2	16		T16	7		T30	19
valid_sources[0x41]	560	1			T2	13		T4	1		T16	6
valid_sources[0x42]	623	1			T2	19		T16	2		T30	18
valid_sources[0x43]	803	1			T2	14		T21	1		T16	10
valid_sources[0x44]	778	1			T2	19		T10	1		T4	1
valid_sources[0x45]	677	1			T2	11		T16	9		T30	33
valid_sources[0x46]	1046	1			T2	14		T16	2		T30	10
valid_sources[0x47]	813	1			T2	7		T4	1		T60	1
valid_sources[0x48]	637	1			T2	21		T4	1		T16	8
valid_sources[0x49]	852	1			T2	14		T16	5		T30	29
valid_sources[0x4a]	629	1			T2	18		T16	5		T30	27
valid_sources[0x4b]	599	1			T2	12		T16	8		T30	16
valid_sources[0x4c]	642	1			T2	8		T18	5		T21	1
valid_sources[0x4d]	887	1			T2	15		T16	10		T30	25
valid_sources[0x4e]	749	1			T2	23		T16	4		T30	27
valid_sources[0x4f]	824	1			T2	12		T16	3		T30	15
valid_sources[0x50]	655	1			T2	18		T16	5		T30	26
valid_sources[0x51]	687	1			T2	14		T21	1		T16	3
valid_sources[0x52]	772	1			T2	8		T4	1		T16	5
valid_sources[0x53]	657	1			T2	14		T16	10		T30	11
valid_sources[0x54]	570	1			T2	6		T16	8		T30	12
valid_sources[0x55]	1112	1			T2	15		T10	1		T16	4
valid_sources[0x56]	720	1			T2	17		T4	1		T16	8
valid_sources[0x57]	739	1			T2	18		T16	8		T46	2
valid_sources[0x58]	646	1			T2	14		T16	9		T32	1
valid_sources[0x59]	557	1			T2	15		T10	1		T21	1
valid_sources[0x5a]	864	1			T2	15		T16	2		T30	36
valid_sources[0x5b]	673	1			T2	13		T25	1		T16	4
valid_sources[0x5c]	646	1			T2	16		T61	2		T16	4
valid_sources[0x5d]	915	1			T2	18		T16	1		T30	36
valid_sources[0x5e]	935	1			T2	21		T16	6		T30	13
valid_sources[0x5f]	854	1			T2	14		T16	7		T30	18
valid_sources[0x60]	1163	1			T2	13		T10	1		T16	3
valid_sources[0x61]	703	1			T2	10		T16	4		T46	4
valid_sources[0x62]	818	1			T2	14		T16	3		T30	11
valid_sources[0x63]	637	1			T2	21		T16	8		T30	16
valid_sources[0x64]	647	1			T2	15		T16	3		T30	40
valid_sources[0x65]	842	1			T2	15		T9	2		T16	7
valid_sources[0x66]	791	1			T2	19		T21	1		T4	1
valid_sources[0x67]	987	1			T2	16		T16	3		T30	20
valid_sources[0x68]	793	1			T2	9		T16	5		T30	30
valid_sources[0x69]	688	1			T2	18		T9	3		T16	12
valid_sources[0x6a]	676	1			T2	13		T16	8		T30	24
valid_sources[0x6b]	657	1			T2	20		T16	7		T30	30
valid_sources[0x6c]	611	1			T2	16		T16	11		T46	2
valid_sources[0x6d]	785	1			T2	14		T16	6		T30	15
valid_sources[0x6e]	620	1			T2	14		T16	5		T30	19
valid_sources[0x6f]	774	1			T2	25		T9	3		T16	6
valid_sources[0x70]	880	1			T2	22		T16	3		T30	29
valid_sources[0x71]	732	1			T2	13		T18	1		T4	1
valid_sources[0x72]	643	1			T2	16		T16	5		T30	14
valid_sources[0x73]	567	1			T2	20		T16	3		T30	16
valid_sources[0x74]	588	1			T2	24		T21	1		T16	2
valid_sources[0x75]	770	1			T2	20		T16	4		T30	34
valid_sources[0x76]	615	1			T2	16		T16	4		T30	20
valid_sources[0x77]	564	1			T2	18		T18	6		T16	10
valid_sources[0x78]	697	1			T2	18		T92	1		T4	1
valid_sources[0x79]	752	1			T2	9		T18	3		T21	1
valid_sources[0x7a]	679	1			T2	15		T14	4		T16	6
valid_sources[0x7b]	596	1			T2	12		T21	1		T16	10
valid_sources[0x7c]	805	1			T2	12		T16	5		T30	25
valid_sources[0x7d]	897	1			T2	24		T18	1		T16	9
valid_sources[0x7e]	656	1			T2	16		T16	5		T30	23
valid_sources[0x7f]	1046	1			T2	22		T16	8		T30	14
valid_sources[0x80]	693	1			T2	11		T18	2		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43091

1

T2

958

T4

8

T5

3

values[0x0]

all_enables

biggest_size

58392

1

T2

1358

T7

1

T8

6

values[0x1]

all_enables

biggest_size

56577

1

T2

1363

T8

2

T9

2