Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16533853

1

T1

30893

T2

7466

T3

5109

full_word

147208587

1

T1

1662

T2

12362

T3

1136

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	163742120	1			T1	32555		T2	19828		T3	6245
auto[TlIntgErrCmd]	106	1			T102	4		T103	8		T104	4
auto[TlIntgErrData]	113	1			T102	3		T103	7		T104	3
auto[TlIntgErrBoth]	101	1			T102	3		T103	5		T104	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78913777

1

T1

16057

T2

5056

T3

3172

auto[1]

84828663

1

T1

16498

T2

14772

T3

3073

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8097852	1			T1	15928		T2	1648		T3	2590
auto[TlIntgErrNone]	partial	auto[1]	8435708	1			T1	14965		T2	5818		T3	2519
auto[TlIntgErrNone]	full_word	auto[0]	70815794	1			T1	129		T2	3408		T3	582
auto[TlIntgErrNone]	full_word	auto[1]	76392766	1			T1	1533		T2	8954		T3	554
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T102	2		T103	3		T104	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T102	2		T103	5		T104	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T118	1		T119	1		T120	2
auto[TlIntgErrData]	partial	auto[0]	49	1			T102	2		T103	3		T118	5
auto[TlIntgErrData]	partial	auto[1]	54	1			T102	1		T103	3		T104	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T120	1		T121	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T103	1		T119	1		T123	2
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T103	1		T104	1		T118	5
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T102	3		T103	4		T104	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T119	1		T124	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T104	1		T121	1		T126	1