Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	692985	1			T2	6		T14	31269		T15	1795
auto[1]	11533034	1			T1	1967		T2	7		T3	400
auto[2]	544500	1			T2	3		T14	26711		T15	815
auto[3]	11263890	1			T1	2127		T2	1		T3	371

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14738781	1			T1	5		T2	14		T3	10
auto[1]	2252530	1			T1	84		T2	1		T3	98
auto[2]	2283352	1			T1	249		T2	1		T3	89
auto[3]	4759746	1			T1	3756		T2	1		T3	574

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9673364

1

T1

4094

T2

17

T3

771

auto[1]

14361045

1

T11

184292

T12

232950

T13

122241

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	278767	1			T2	4		T15	1480		T48	374
auto[0]	auto[0]	auto[1]	29665	1			T2	1		T15	158		T48	52
auto[0]	auto[0]	auto[2]	29794	1			T2	1		T15	143		T97	1
auto[0]	auto[0]	auto[3]	82956	1			T15	14		T97	1		T48	4
auto[0]	auto[1]	auto[0]	3293405	1			T2	6		T3	7		T12	10
auto[0]	auto[1]	auto[1]	358200	1			T1	4		T3	77		T17	751
auto[0]	auto[1]	auto[2]	377843	1			T1	62		T3	18		T12	2
auto[0]	auto[1]	auto[3]	551713	1			T1	1901		T2	1		T3	298
auto[0]	auto[2]	auto[0]	208866	1			T2	3		T15	657		T48	122
auto[0]	auto[2]	auto[1]	28146	1			T15	54		T48	15		T132	30
auto[0]	auto[2]	auto[2]	21695	1			T15	90		T97	1		T48	16
auto[0]	auto[2]	auto[3]	57225	1			T15	14		T97	3		T48	2
auto[0]	auto[3]	auto[0]	3125021	1			T1	5		T2	1		T3	3
auto[0]	auto[3]	auto[1]	355558	1			T1	80		T3	21		T17	777
auto[0]	auto[3]	auto[2]	375900	1			T1	187		T3	71		T17	777
auto[0]	auto[3]	auto[3]	498610	1			T1	1855		T3	276		T17	173
auto[1]	auto[0]	auto[0]	8955	1			T14	1012		T97	746		T133	1
auto[1]	auto[0]	auto[1]	40589	1			T14	4787		T97	3443		T134	1978
auto[1]	auto[0]	auto[2]	40523	1			T14	4674		T97	3435		T134	2125
auto[1]	auto[0]	auto[3]	181736	1			T14	20796		T97	15530		T79	3
auto[1]	auto[1]	auto[0]	3909348	1			T11	3216		T12	96920		T13	51022
auto[1]	auto[1]	auto[1]	715796	1			T11	13531		T12	8884		T13	4563
auto[1]	auto[1]	auto[2]	694905	1			T11	14749		T12	9770		T13	4974
auto[1]	auto[1]	auto[3]	1631824	1			T11	60187		T12	902		T13	504
auto[1]	auto[2]	auto[0]	7731	1			T14	945		T97	649		T134	249
auto[1]	auto[2]	auto[1]	34859	1			T14	4152		T97	3147		T134	1198
auto[1]	auto[2]	auto[2]	33971	1			T14	3978		T97	2794		T134	2203
auto[1]	auto[2]	auto[3]	152007	1			T14	17636		T97	12969		T134	9838
auto[1]	auto[3]	auto[0]	3906688	1			T11	3282		T12	97058		T13	50913
auto[1]	auto[3]	auto[1]	689717	1			T11	15007		T12	9770		T13	5121
auto[1]	auto[3]	auto[2]	708721	1			T11	13681		T12	8760		T13	4673
auto[1]	auto[3]	auto[3]	1603675	1			T11	60639		T12	886		T13	471