Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1085762178	151989	0	0
ctrl_regwen_rd_A	1085762178	11334	0	0
exec_rd_A	1085762178	10632	0	0
exec_regwen_rd_A	1085762178	11072	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1085762178	151989	0	0
T2	210867	4999	0	0
T3	74021	0	0	0
T7	40023	0	0	0
T8	131112	0	0	0
T9	1519	0	0	0
T10	1231	0	0	0
T11	594981	0	0	0
T12	526035	0	0	0
T13	275245	0	0	0
T16	0	2135	0	0
T17	79155	0	0	0
T30	0	7264	0	0
T49	0	1515	0	0
T50	0	1681	0	0
T51	0	4885	0	0
T52	0	748	0	0
T53	0	3455	0	0
T54	0	1698	0	0
T55	0	2813	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1085762178	11334	0	0
T15	228182	0	0	0
T16	67945	149	0	0
T30	317994	901	0	0
T32	34929	0	0	0
T33	33864	0	0	0
T46	148251	0	0	0
T49	49621	0	0	0
T62	527252	0	0	0
T105	0	430	0	0
T106	0	309	0	0
T107	0	535	0	0
T108	0	445	0	0
T109	0	256	0	0
T110	0	1180	0	0
T111	0	451	0	0
T112	0	227	0	0
T113	178949	0	0	0
T114	121326	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1085762178	10632	0	0
T15	228182	0	0	0
T16	67945	144	0	0
T30	317994	567	0	0
T32	34929	0	0	0
T33	33864	0	0	0
T46	148251	0	0	0
T49	49621	0	0	0
T62	527252	0	0	0
T105	0	416	0	0
T106	0	308	0	0
T107	0	537	0	0
T108	0	425	0	0
T109	0	286	0	0
T110	0	1025	0	0
T111	0	455	0	0
T112	0	245	0	0
T113	178949	0	0	0
T114	121326	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1085762178	11072	0	0
T15	228182	0	0	0
T16	67945	160	0	0
T30	317994	812	0	0
T32	34929	0	0	0
T33	33864	0	0	0
T46	148251	0	0	0
T49	49621	0	0	0
T62	527252	0	0	0
T105	0	376	0	0
T106	0	303	0	0
T107	0	567	0	0
T108	0	476	0	0
T109	0	276	0	0
T110	0	1043	0	0
T111	0	547	0	0
T112	0	173	0	0
T113	178949	0	0	0
T114	121326	0	0	0