Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.06 99.81 96.99 100.00 100.00 98.60 99.70 98.33


Total test records in report: 1033
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T792 /workspace/coverage/default/5.sram_ctrl_ram_cfg.3165390485 May 02 01:51:37 PM PDT 24 May 02 01:51:41 PM PDT 24 1371375420 ps
T793 /workspace/coverage/default/37.sram_ctrl_partial_access.305220277 May 02 01:54:43 PM PDT 24 May 02 01:55:28 PM PDT 24 930224280 ps
T794 /workspace/coverage/default/41.sram_ctrl_alert_test.350220535 May 02 01:55:23 PM PDT 24 May 02 01:55:25 PM PDT 24 35880838 ps
T795 /workspace/coverage/default/46.sram_ctrl_lc_escalation.2823995798 May 02 01:56:19 PM PDT 24 May 02 01:56:37 PM PDT 24 2494192155 ps
T796 /workspace/coverage/default/13.sram_ctrl_executable.56693846 May 02 01:51:55 PM PDT 24 May 02 01:53:04 PM PDT 24 21072421204 ps
T797 /workspace/coverage/default/36.sram_ctrl_partial_access.3690619326 May 02 01:54:31 PM PDT 24 May 02 01:54:46 PM PDT 24 910907294 ps
T798 /workspace/coverage/default/31.sram_ctrl_alert_test.1521703064 May 02 01:53:47 PM PDT 24 May 02 01:53:48 PM PDT 24 43989597 ps
T799 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.4067457458 May 02 01:55:08 PM PDT 24 May 02 01:56:13 PM PDT 24 4479288472 ps
T800 /workspace/coverage/default/5.sram_ctrl_multiple_keys.1653952159 May 02 01:51:37 PM PDT 24 May 02 02:02:24 PM PDT 24 12323738223 ps
T801 /workspace/coverage/default/1.sram_ctrl_alert_test.2344789191 May 02 01:51:29 PM PDT 24 May 02 01:51:31 PM PDT 24 93845783 ps
T802 /workspace/coverage/default/41.sram_ctrl_partial_access.2365284692 May 02 01:55:15 PM PDT 24 May 02 01:57:46 PM PDT 24 1441961808 ps
T803 /workspace/coverage/default/46.sram_ctrl_executable.800430139 May 02 01:56:19 PM PDT 24 May 02 02:11:11 PM PDT 24 22401535378 ps
T804 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3771343958 May 02 01:52:14 PM PDT 24 May 02 01:56:21 PM PDT 24 4180998301 ps
T805 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1192713591 May 02 01:51:30 PM PDT 24 May 02 01:51:38 PM PDT 24 743412279 ps
T806 /workspace/coverage/default/38.sram_ctrl_mem_walk.3856293518 May 02 01:54:52 PM PDT 24 May 02 01:59:09 PM PDT 24 15768918252 ps
T807 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1012508073 May 02 01:53:17 PM PDT 24 May 02 01:58:10 PM PDT 24 18580299255 ps
T808 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.246384917 May 02 01:51:58 PM PDT 24 May 02 01:54:34 PM PDT 24 10170434226 ps
T809 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2070900596 May 02 01:51:22 PM PDT 24 May 02 01:57:34 PM PDT 24 5652356353 ps
T810 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3335188138 May 02 01:53:41 PM PDT 24 May 02 01:54:21 PM PDT 24 952286168 ps
T811 /workspace/coverage/default/35.sram_ctrl_stress_all.113626947 May 02 01:54:28 PM PDT 24 May 02 03:02:59 PM PDT 24 191992792625 ps
T812 /workspace/coverage/default/47.sram_ctrl_smoke.1924451484 May 02 01:56:25 PM PDT 24 May 02 01:56:33 PM PDT 24 697504987 ps
T813 /workspace/coverage/default/0.sram_ctrl_lc_escalation.2420440860 May 02 01:51:20 PM PDT 24 May 02 01:52:43 PM PDT 24 26386107836 ps
T814 /workspace/coverage/default/28.sram_ctrl_max_throughput.3314446359 May 02 01:53:24 PM PDT 24 May 02 01:54:37 PM PDT 24 1503877314 ps
T815 /workspace/coverage/default/5.sram_ctrl_regwen.3114846883 May 02 01:51:36 PM PDT 24 May 02 02:04:43 PM PDT 24 15729842263 ps
T816 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1824645973 May 02 01:53:19 PM PDT 24 May 02 01:54:42 PM PDT 24 9617339842 ps
T817 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.4255731805 May 02 01:53:01 PM PDT 24 May 02 01:56:57 PM PDT 24 3212958283 ps
T818 /workspace/coverage/default/20.sram_ctrl_smoke.512663479 May 02 01:52:34 PM PDT 24 May 02 01:52:47 PM PDT 24 2855224365 ps
T819 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3168459803 May 02 01:52:52 PM PDT 24 May 02 01:53:01 PM PDT 24 270775548 ps
T820 /workspace/coverage/default/38.sram_ctrl_max_throughput.2118163597 May 02 01:54:51 PM PDT 24 May 02 01:54:58 PM PDT 24 691780995 ps
T821 /workspace/coverage/default/1.sram_ctrl_mem_walk.2229335636 May 02 01:51:28 PM PDT 24 May 02 01:53:40 PM PDT 24 7083001816 ps
T822 /workspace/coverage/default/26.sram_ctrl_executable.4152677160 May 02 01:53:11 PM PDT 24 May 02 02:06:32 PM PDT 24 44716907360 ps
T823 /workspace/coverage/default/16.sram_ctrl_executable.1154591539 May 02 01:52:06 PM PDT 24 May 02 02:19:29 PM PDT 24 81246538221 ps
T824 /workspace/coverage/default/37.sram_ctrl_regwen.1585503994 May 02 01:54:44 PM PDT 24 May 02 02:03:28 PM PDT 24 19108866097 ps
T825 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1759608124 May 02 01:54:45 PM PDT 24 May 02 02:14:37 PM PDT 24 29746351147 ps
T826 /workspace/coverage/default/27.sram_ctrl_ram_cfg.3819094388 May 02 01:53:12 PM PDT 24 May 02 01:53:17 PM PDT 24 699906067 ps
T827 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.4108881752 May 02 01:52:06 PM PDT 24 May 02 01:53:05 PM PDT 24 2365190340 ps
T828 /workspace/coverage/default/12.sram_ctrl_alert_test.112603921 May 02 01:51:55 PM PDT 24 May 02 01:51:58 PM PDT 24 45714798 ps
T829 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3402912580 May 02 01:51:42 PM PDT 24 May 02 01:54:11 PM PDT 24 9608601855 ps
T830 /workspace/coverage/default/48.sram_ctrl_alert_test.4017551076 May 02 01:56:56 PM PDT 24 May 02 01:56:58 PM PDT 24 36364519 ps
T831 /workspace/coverage/default/15.sram_ctrl_alert_test.2934274250 May 02 01:52:06 PM PDT 24 May 02 01:52:08 PM PDT 24 16137606 ps
T832 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.823615667 May 02 01:51:38 PM PDT 24 May 02 01:51:50 PM PDT 24 567665224 ps
T833 /workspace/coverage/default/30.sram_ctrl_ram_cfg.3550572134 May 02 01:53:34 PM PDT 24 May 02 01:53:39 PM PDT 24 1608206868 ps
T834 /workspace/coverage/default/30.sram_ctrl_max_throughput.3530370890 May 02 01:53:35 PM PDT 24 May 02 01:54:30 PM PDT 24 4599848503 ps
T835 /workspace/coverage/default/22.sram_ctrl_lc_escalation.2683338056 May 02 01:52:37 PM PDT 24 May 02 01:53:20 PM PDT 24 13383326869 ps
T836 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.852007667 May 02 01:52:38 PM PDT 24 May 02 01:59:56 PM PDT 24 7516859240 ps
T837 /workspace/coverage/default/2.sram_ctrl_lc_escalation.3507746026 May 02 01:51:36 PM PDT 24 May 02 01:52:22 PM PDT 24 6284004954 ps
T838 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.4173467129 May 02 01:54:12 PM PDT 24 May 02 01:58:03 PM PDT 24 5164781453 ps
T839 /workspace/coverage/default/37.sram_ctrl_multiple_keys.2918134850 May 02 01:54:35 PM PDT 24 May 02 02:08:50 PM PDT 24 17983175613 ps
T840 /workspace/coverage/default/3.sram_ctrl_executable.2489924175 May 02 01:51:27 PM PDT 24 May 02 02:05:48 PM PDT 24 19383161466 ps
T841 /workspace/coverage/default/26.sram_ctrl_lc_escalation.2463531539 May 02 01:53:09 PM PDT 24 May 02 01:53:54 PM PDT 24 14626445766 ps
T842 /workspace/coverage/default/40.sram_ctrl_bijection.1017257212 May 02 01:55:10 PM PDT 24 May 02 02:38:13 PM PDT 24 634454837241 ps
T843 /workspace/coverage/default/34.sram_ctrl_multiple_keys.4158757990 May 02 01:54:11 PM PDT 24 May 02 02:02:40 PM PDT 24 51067722336 ps
T844 /workspace/coverage/default/10.sram_ctrl_partial_access.1736689034 May 02 01:51:45 PM PDT 24 May 02 01:53:07 PM PDT 24 1896825356 ps
T845 /workspace/coverage/default/1.sram_ctrl_smoke.3559545178 May 02 01:51:21 PM PDT 24 May 02 01:51:40 PM PDT 24 5374837133 ps
T846 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.319548439 May 02 01:53:25 PM PDT 24 May 02 01:56:32 PM PDT 24 12155461536 ps
T847 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.879418882 May 02 01:52:34 PM PDT 24 May 02 01:53:01 PM PDT 24 821780567 ps
T848 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1391924605 May 02 01:55:31 PM PDT 24 May 02 01:55:43 PM PDT 24 692086088 ps
T849 /workspace/coverage/default/44.sram_ctrl_stress_all.3176468355 May 02 01:55:56 PM PDT 24 May 02 02:46:09 PM PDT 24 93346484370 ps
T850 /workspace/coverage/default/35.sram_ctrl_multiple_keys.3898590301 May 02 01:54:20 PM PDT 24 May 02 01:59:01 PM PDT 24 9121719247 ps
T851 /workspace/coverage/default/16.sram_ctrl_ram_cfg.1001929820 May 02 01:52:09 PM PDT 24 May 02 01:52:14 PM PDT 24 845729414 ps
T852 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.861973642 May 02 01:56:31 PM PDT 24 May 02 02:01:24 PM PDT 24 17906452286 ps
T853 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1151643392 May 02 01:51:38 PM PDT 24 May 02 02:13:20 PM PDT 24 17953052100 ps
T854 /workspace/coverage/default/49.sram_ctrl_partial_access.163463689 May 02 01:57:06 PM PDT 24 May 02 01:57:23 PM PDT 24 1464333642 ps
T855 /workspace/coverage/default/40.sram_ctrl_stress_all.1479773732 May 02 01:55:16 PM PDT 24 May 02 03:09:57 PM PDT 24 117306175475 ps
T856 /workspace/coverage/default/5.sram_ctrl_stress_all.2323474196 May 02 01:51:36 PM PDT 24 May 02 02:36:13 PM PDT 24 24539263945 ps
T857 /workspace/coverage/default/4.sram_ctrl_executable.1842198964 May 02 01:51:38 PM PDT 24 May 02 02:06:05 PM PDT 24 25101578141 ps
T858 /workspace/coverage/default/19.sram_ctrl_stress_all.1596644531 May 02 01:52:30 PM PDT 24 May 02 02:52:17 PM PDT 24 603534715263 ps
T859 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1227464032 May 02 01:51:26 PM PDT 24 May 02 01:51:34 PM PDT 24 2782457985 ps
T860 /workspace/coverage/default/23.sram_ctrl_smoke.4246847633 May 02 01:52:36 PM PDT 24 May 02 01:53:00 PM PDT 24 663444587 ps
T861 /workspace/coverage/default/40.sram_ctrl_alert_test.1387040865 May 02 01:55:17 PM PDT 24 May 02 01:55:18 PM PDT 24 39874779 ps
T862 /workspace/coverage/default/15.sram_ctrl_stress_all.3376518680 May 02 01:52:05 PM PDT 24 May 02 02:28:01 PM PDT 24 25404090101 ps
T863 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.635486535 May 02 01:54:52 PM PDT 24 May 02 02:01:17 PM PDT 24 21649128287 ps
T864 /workspace/coverage/default/21.sram_ctrl_max_throughput.1528386661 May 02 01:52:36 PM PDT 24 May 02 01:52:46 PM PDT 24 1013222222 ps
T865 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2800530926 May 02 01:51:28 PM PDT 24 May 02 01:52:05 PM PDT 24 4222014126 ps
T866 /workspace/coverage/default/24.sram_ctrl_max_throughput.2954189562 May 02 01:52:47 PM PDT 24 May 02 01:53:25 PM PDT 24 1565724990 ps
T867 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2106866267 May 02 01:52:14 PM PDT 24 May 02 01:53:18 PM PDT 24 1001016538 ps
T868 /workspace/coverage/default/3.sram_ctrl_max_throughput.1019869463 May 02 01:51:31 PM PDT 24 May 02 01:51:41 PM PDT 24 2722818707 ps
T869 /workspace/coverage/default/1.sram_ctrl_bijection.2937536227 May 02 01:51:19 PM PDT 24 May 02 02:13:21 PM PDT 24 230780120000 ps
T870 /workspace/coverage/default/23.sram_ctrl_partial_access.2380888559 May 02 01:52:39 PM PDT 24 May 02 01:53:02 PM PDT 24 5623439905 ps
T871 /workspace/coverage/default/47.sram_ctrl_executable.686464650 May 02 01:56:42 PM PDT 24 May 02 02:06:24 PM PDT 24 52667208994 ps
T872 /workspace/coverage/default/37.sram_ctrl_mem_walk.143679415 May 02 01:54:46 PM PDT 24 May 02 01:57:14 PM PDT 24 9218066763 ps
T873 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1411886879 May 02 01:52:13 PM PDT 24 May 02 01:52:53 PM PDT 24 804296322 ps
T874 /workspace/coverage/default/3.sram_ctrl_regwen.1780773506 May 02 01:51:27 PM PDT 24 May 02 01:52:40 PM PDT 24 6568186301 ps
T875 /workspace/coverage/default/16.sram_ctrl_stress_all.3268382798 May 02 01:52:08 PM PDT 24 May 02 02:46:23 PM PDT 24 234328659570 ps
T876 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2866481363 May 02 01:52:13 PM PDT 24 May 02 01:59:30 PM PDT 24 38100941184 ps
T877 /workspace/coverage/default/44.sram_ctrl_alert_test.1548690149 May 02 01:56:02 PM PDT 24 May 02 01:56:04 PM PDT 24 113667566 ps
T878 /workspace/coverage/default/43.sram_ctrl_mem_walk.3334787614 May 02 01:55:48 PM PDT 24 May 02 01:58:12 PM PDT 24 27530204887 ps
T879 /workspace/coverage/default/29.sram_ctrl_max_throughput.2922623439 May 02 01:53:24 PM PDT 24 May 02 01:54:49 PM PDT 24 777912644 ps
T880 /workspace/coverage/default/10.sram_ctrl_alert_test.900864023 May 02 01:51:55 PM PDT 24 May 02 01:51:57 PM PDT 24 21862385 ps
T881 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1173919342 May 02 01:56:03 PM PDT 24 May 02 02:01:43 PM PDT 24 53166789263 ps
T882 /workspace/coverage/default/31.sram_ctrl_smoke.2459707490 May 02 01:53:39 PM PDT 24 May 02 01:54:58 PM PDT 24 2794054985 ps
T883 /workspace/coverage/default/9.sram_ctrl_lc_escalation.1947830468 May 02 01:51:46 PM PDT 24 May 02 01:53:14 PM PDT 24 28816188774 ps
T884 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.947843098 May 02 01:53:38 PM PDT 24 May 02 02:01:45 PM PDT 24 26308202523 ps
T885 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.756942882 May 02 01:54:19 PM PDT 24 May 02 01:55:29 PM PDT 24 2006717084 ps
T886 /workspace/coverage/default/6.sram_ctrl_max_throughput.1132804288 May 02 01:51:37 PM PDT 24 May 02 01:53:32 PM PDT 24 772072587 ps
T887 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.602208588 May 02 01:53:17 PM PDT 24 May 02 02:04:23 PM PDT 24 10723461325 ps
T888 /workspace/coverage/default/49.sram_ctrl_smoke.4162828908 May 02 01:56:56 PM PDT 24 May 02 01:57:43 PM PDT 24 419431701 ps
T889 /workspace/coverage/default/27.sram_ctrl_partial_access.981001434 May 02 01:53:09 PM PDT 24 May 02 01:54:31 PM PDT 24 1257164165 ps
T890 /workspace/coverage/default/30.sram_ctrl_partial_access.3590567297 May 02 01:53:40 PM PDT 24 May 02 01:54:04 PM PDT 24 5699175553 ps
T891 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3557574157 May 02 01:54:43 PM PDT 24 May 02 01:59:25 PM PDT 24 4535041854 ps
T892 /workspace/coverage/default/11.sram_ctrl_partial_access.2162730527 May 02 01:51:54 PM PDT 24 May 02 01:52:29 PM PDT 24 3002882639 ps
T893 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1654972505 May 02 01:51:35 PM PDT 24 May 02 01:52:38 PM PDT 24 784916883 ps
T894 /workspace/coverage/default/28.sram_ctrl_alert_test.1806551952 May 02 01:53:25 PM PDT 24 May 02 01:53:28 PM PDT 24 22159870 ps
T895 /workspace/coverage/default/34.sram_ctrl_alert_test.2259785128 May 02 01:54:22 PM PDT 24 May 02 01:54:23 PM PDT 24 13380355 ps
T896 /workspace/coverage/default/21.sram_ctrl_smoke.2469867125 May 02 01:52:27 PM PDT 24 May 02 01:52:49 PM PDT 24 3642144139 ps
T897 /workspace/coverage/default/30.sram_ctrl_mem_walk.3490626620 May 02 01:53:36 PM PDT 24 May 02 01:58:09 PM PDT 24 14338653241 ps
T898 /workspace/coverage/default/39.sram_ctrl_mem_walk.1292282720 May 02 01:55:08 PM PDT 24 May 02 02:00:52 PM PDT 24 86085977375 ps
T899 /workspace/coverage/default/47.sram_ctrl_partial_access.142094103 May 02 01:56:32 PM PDT 24 May 02 01:59:13 PM PDT 24 1757857064 ps
T900 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.3212371718 May 02 01:54:54 PM PDT 24 May 02 01:56:09 PM PDT 24 10451028525 ps
T901 /workspace/coverage/default/34.sram_ctrl_lc_escalation.1037433291 May 02 01:54:12 PM PDT 24 May 02 01:55:28 PM PDT 24 43489863713 ps
T902 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2879205260 May 02 01:52:07 PM PDT 24 May 02 01:52:46 PM PDT 24 738986202 ps
T903 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3361772641 May 02 01:52:37 PM PDT 24 May 02 01:54:59 PM PDT 24 7805480585 ps
T904 /workspace/coverage/default/16.sram_ctrl_regwen.2582585621 May 02 01:52:06 PM PDT 24 May 02 01:52:27 PM PDT 24 3053679620 ps
T905 /workspace/coverage/default/0.sram_ctrl_regwen.3175622125 May 02 01:51:26 PM PDT 24 May 02 02:13:23 PM PDT 24 29004906081 ps
T906 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2705042733 May 02 01:54:15 PM PDT 24 May 02 02:01:33 PM PDT 24 69026213191 ps
T907 /workspace/coverage/default/21.sram_ctrl_multiple_keys.456334298 May 02 01:52:24 PM PDT 24 May 02 01:55:41 PM PDT 24 2960630495 ps
T908 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.2436162619 May 02 01:55:01 PM PDT 24 May 02 01:56:04 PM PDT 24 3782919066 ps
T909 /workspace/coverage/default/42.sram_ctrl_lc_escalation.2987060828 May 02 01:55:31 PM PDT 24 May 02 01:56:59 PM PDT 24 52042460184 ps
T910 /workspace/coverage/default/23.sram_ctrl_stress_all.2347246474 May 02 01:52:47 PM PDT 24 May 02 03:45:19 PM PDT 24 380452359805 ps
T911 /workspace/coverage/default/47.sram_ctrl_mem_walk.2894762186 May 02 01:56:42 PM PDT 24 May 02 01:58:46 PM PDT 24 8977531689 ps
T912 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2921441891 May 02 01:52:07 PM PDT 24 May 02 01:52:49 PM PDT 24 4587191700 ps
T913 /workspace/coverage/default/14.sram_ctrl_ram_cfg.3835735669 May 02 01:52:12 PM PDT 24 May 02 01:52:17 PM PDT 24 4198582659 ps
T914 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2874187783 May 02 01:52:35 PM PDT 24 May 02 01:58:22 PM PDT 24 11148032371 ps
T915 /workspace/coverage/default/31.sram_ctrl_stress_all.916482167 May 02 01:53:47 PM PDT 24 May 02 02:43:33 PM PDT 24 637358661262 ps
T916 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1153989490 May 02 01:51:31 PM PDT 24 May 02 01:58:41 PM PDT 24 46849539370 ps
T917 /workspace/coverage/default/44.sram_ctrl_ram_cfg.3411398982 May 02 01:55:57 PM PDT 24 May 02 01:56:01 PM PDT 24 1411441885 ps
T918 /workspace/coverage/default/37.sram_ctrl_smoke.154220024 May 02 01:54:37 PM PDT 24 May 02 01:56:58 PM PDT 24 949707238 ps
T919 /workspace/coverage/default/48.sram_ctrl_ram_cfg.3367657901 May 02 01:56:54 PM PDT 24 May 02 01:56:58 PM PDT 24 1416290104 ps
T920 /workspace/coverage/default/17.sram_ctrl_max_throughput.3888486931 May 02 01:52:04 PM PDT 24 May 02 01:52:10 PM PDT 24 2669292110 ps
T921 /workspace/coverage/default/8.sram_ctrl_max_throughput.1947348570 May 02 01:51:44 PM PDT 24 May 02 01:51:55 PM PDT 24 2202992332 ps
T922 /workspace/coverage/default/47.sram_ctrl_multiple_keys.4158683006 May 02 01:56:31 PM PDT 24 May 02 02:13:39 PM PDT 24 7141773054 ps
T923 /workspace/coverage/default/13.sram_ctrl_partial_access.2072052736 May 02 01:51:58 PM PDT 24 May 02 01:52:22 PM PDT 24 1488068346 ps
T924 /workspace/coverage/default/28.sram_ctrl_regwen.1896014178 May 02 01:53:19 PM PDT 24 May 02 01:58:20 PM PDT 24 2317849768 ps
T925 /workspace/coverage/default/10.sram_ctrl_ram_cfg.3590205474 May 02 01:51:54 PM PDT 24 May 02 01:51:58 PM PDT 24 347689418 ps
T926 /workspace/coverage/default/42.sram_ctrl_mem_walk.1388510823 May 02 01:55:38 PM PDT 24 May 02 01:59:46 PM PDT 24 16421847868 ps
T927 /workspace/coverage/default/29.sram_ctrl_lc_escalation.2226984864 May 02 01:53:26 PM PDT 24 May 02 01:53:39 PM PDT 24 1648607288 ps
T928 /workspace/coverage/default/9.sram_ctrl_ram_cfg.234748515 May 02 01:51:47 PM PDT 24 May 02 01:51:51 PM PDT 24 1371949254 ps
T929 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3948983477 May 02 01:55:07 PM PDT 24 May 02 02:00:12 PM PDT 24 71207748331 ps
T930 /workspace/coverage/default/42.sram_ctrl_smoke.218010278 May 02 01:55:25 PM PDT 24 May 02 01:56:10 PM PDT 24 726288166 ps
T931 /workspace/coverage/default/24.sram_ctrl_executable.3105851896 May 02 01:52:47 PM PDT 24 May 02 02:20:34 PM PDT 24 92188749373 ps
T932 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1978708105 May 02 01:53:48 PM PDT 24 May 02 01:54:50 PM PDT 24 3776438399 ps
T933 /workspace/coverage/default/0.sram_ctrl_mem_walk.477595352 May 02 01:51:26 PM PDT 24 May 02 01:56:25 PM PDT 24 81051509439 ps
T934 /workspace/coverage/default/42.sram_ctrl_partial_access.2893747288 May 02 01:55:33 PM PDT 24 May 02 01:57:28 PM PDT 24 1373290819 ps
T935 /workspace/coverage/default/44.sram_ctrl_partial_access.337319009 May 02 01:55:59 PM PDT 24 May 02 01:56:22 PM PDT 24 1158280131 ps
T936 /workspace/coverage/default/7.sram_ctrl_mem_walk.2895007293 May 02 01:51:50 PM PDT 24 May 02 01:54:09 PM PDT 24 11315193332 ps
T937 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3515750366 May 02 01:51:29 PM PDT 24 May 02 01:52:05 PM PDT 24 2546502072 ps
T938 /workspace/coverage/default/7.sram_ctrl_partial_access.1357310570 May 02 01:51:35 PM PDT 24 May 02 01:51:58 PM PDT 24 1559103631 ps
T939 /workspace/coverage/default/6.sram_ctrl_multiple_keys.1692428115 May 02 01:51:34 PM PDT 24 May 02 02:06:51 PM PDT 24 74517975872 ps
T940 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.499776746 May 02 01:37:44 PM PDT 24 May 02 01:37:48 PM PDT 24 241636757 ps
T63 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3500531079 May 02 01:38:01 PM PDT 24 May 02 01:38:03 PM PDT 24 58464600 ps
T64 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.935451684 May 02 01:37:58 PM PDT 24 May 02 01:38:26 PM PDT 24 3843752219 ps
T65 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.924908933 May 02 01:38:04 PM PDT 24 May 02 01:38:07 PM PDT 24 106043761 ps
T102 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.854051466 May 02 01:37:56 PM PDT 24 May 02 01:37:59 PM PDT 24 215980411 ps
T99 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2506946304 May 02 01:37:48 PM PDT 24 May 02 01:37:50 PM PDT 24 36929387 ps
T941 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.526617145 May 02 01:37:47 PM PDT 24 May 02 01:37:53 PM PDT 24 1827397236 ps
T93 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1862602338 May 02 01:37:58 PM PDT 24 May 02 01:38:01 PM PDT 24 59045050 ps
T66 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2172337296 May 02 01:37:36 PM PDT 24 May 02 01:37:38 PM PDT 24 16316440 ps
T103 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3271190035 May 02 01:37:56 PM PDT 24 May 02 01:37:59 PM PDT 24 194846930 ps
T104 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.330036857 May 02 01:37:46 PM PDT 24 May 02 01:37:49 PM PDT 24 359243393 ps
T100 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1920758173 May 02 01:38:12 PM PDT 24 May 02 01:38:14 PM PDT 24 16889566 ps
T101 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2143063995 May 02 01:38:03 PM PDT 24 May 02 01:38:05 PM PDT 24 21381405 ps
T67 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.897389995 May 02 01:37:37 PM PDT 24 May 02 01:37:39 PM PDT 24 25784261 ps
T942 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.556423694 May 02 01:37:59 PM PDT 24 May 02 01:38:04 PM PDT 24 724168418 ps
T94 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3512462076 May 02 01:37:58 PM PDT 24 May 02 01:38:00 PM PDT 24 14547166 ps
T943 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.111358829 May 02 01:37:39 PM PDT 24 May 02 01:37:41 PM PDT 24 16055055 ps
T118 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.649987823 May 02 01:37:37 PM PDT 24 May 02 01:37:41 PM PDT 24 1110097250 ps
T944 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2939004478 May 02 01:37:33 PM PDT 24 May 02 01:37:37 PM PDT 24 1073517324 ps
T119 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3425255421 May 02 01:37:59 PM PDT 24 May 02 01:38:03 PM PDT 24 538407449 ps
T95 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2638027024 May 02 01:37:39 PM PDT 24 May 02 01:37:41 PM PDT 24 23872204 ps
T68 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3538678616 May 02 01:37:46 PM PDT 24 May 02 01:37:48 PM PDT 24 29660206 ps
T945 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1055497139 May 02 01:37:35 PM PDT 24 May 02 01:37:37 PM PDT 24 16087827 ps
T69 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3458461161 May 02 01:37:33 PM PDT 24 May 02 01:37:36 PM PDT 24 44009869 ps
T96 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3921605650 May 02 01:37:51 PM PDT 24 May 02 01:37:53 PM PDT 24 38113557 ps
T123 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4149026539 May 02 01:37:31 PM PDT 24 May 02 01:37:33 PM PDT 24 220145612 ps
T70 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2080109198 May 02 01:37:47 PM PDT 24 May 02 01:38:41 PM PDT 24 28239673828 ps
T71 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1353867699 May 02 01:37:47 PM PDT 24 May 02 01:37:49 PM PDT 24 14506360 ps
T946 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.20884755 May 02 01:38:05 PM PDT 24 May 02 01:38:08 PM PDT 24 12487447 ps
T72 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1277529694 May 02 01:38:02 PM PDT 24 May 02 01:38:38 PM PDT 24 52599192548 ps
T947 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4027473132 May 02 01:37:37 PM PDT 24 May 02 01:37:39 PM PDT 24 101019620 ps
T948 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.588790654 May 02 01:38:05 PM PDT 24 May 02 01:38:10 PM PDT 24 285788562 ps
T949 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4030101577 May 02 01:37:45 PM PDT 24 May 02 01:37:50 PM PDT 24 210916112 ps
T74 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1729592718 May 02 01:37:47 PM PDT 24 May 02 01:38:41 PM PDT 24 7354774702 ps
T950 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3332101974 May 02 01:37:46 PM PDT 24 May 02 01:37:50 PM PDT 24 98244279 ps
T951 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4096356880 May 02 01:37:56 PM PDT 24 May 02 01:38:02 PM PDT 24 279710913 ps
T952 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3748003990 May 02 01:37:57 PM PDT 24 May 02 01:37:59 PM PDT 24 13566496 ps
T953 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3646203748 May 02 01:37:59 PM PDT 24 May 02 01:38:04 PM PDT 24 353902267 ps
T954 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1111599385 May 02 01:37:57 PM PDT 24 May 02 01:38:01 PM PDT 24 92672238 ps
T75 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3204971126 May 02 01:37:36 PM PDT 24 May 02 01:37:39 PM PDT 24 176610271 ps
T955 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2680430662 May 02 01:37:59 PM PDT 24 May 02 01:38:03 PM PDT 24 201266747 ps
T956 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2627411630 May 02 01:38:04 PM PDT 24 May 02 01:38:06 PM PDT 24 32516176 ps
T76 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1076016024 May 02 01:37:56 PM PDT 24 May 02 01:38:49 PM PDT 24 27036679998 ps
T957 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2030415291 May 02 01:38:06 PM PDT 24 May 02 01:38:09 PM PDT 24 129334325 ps
T958 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.734075493 May 02 01:37:33 PM PDT 24 May 02 01:37:39 PM PDT 24 158814011 ps
T959 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1987334641 May 02 01:37:38 PM PDT 24 May 02 01:37:42 PM PDT 24 117538876 ps
T960 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1982086973 May 02 01:37:47 PM PDT 24 May 02 01:37:52 PM PDT 24 377490585 ps
T961 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1813665263 May 02 01:38:05 PM PDT 24 May 02 01:38:10 PM PDT 24 1399306606 ps
T962 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3307625880 May 02 01:37:57 PM PDT 24 May 02 01:38:03 PM PDT 24 732855728 ps
T77 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3297645182 May 02 01:37:36 PM PDT 24 May 02 01:38:27 PM PDT 24 7280982540 ps
T124 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2105252433 May 02 01:37:36 PM PDT 24 May 02 01:37:39 PM PDT 24 417168225 ps
T84 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2190314715 May 02 01:37:51 PM PDT 24 May 02 01:38:48 PM PDT 24 14393207408 ps
T120 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.43557112 May 02 01:38:05 PM PDT 24 May 02 01:38:08 PM PDT 24 257198629 ps
T963 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.736284105 May 02 01:37:37 PM PDT 24 May 02 01:37:39 PM PDT 24 47194202 ps
T964 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3397661653 May 02 01:37:58 PM PDT 24 May 02 01:38:01 PM PDT 24 251305797 ps
T965 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2941325311 May 02 01:37:45 PM PDT 24 May 02 01:37:50 PM PDT 24 357458430 ps
T121 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3224273032 May 02 01:37:29 PM PDT 24 May 02 01:37:32 PM PDT 24 566782535 ps
T966 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.530835727 May 02 01:38:03 PM PDT 24 May 02 01:38:08 PM PDT 24 346028743 ps
T967 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1661274842 May 02 01:37:45 PM PDT 24 May 02 01:37:50 PM PDT 24 940079118 ps
T968 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2188936706 May 02 01:37:36 PM PDT 24 May 02 01:37:38 PM PDT 24 16661990 ps
T85 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3530542160 May 02 01:38:01 PM PDT 24 May 02 01:38:31 PM PDT 24 7538803867 ps
T969 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.469634359 May 02 01:37:47 PM PDT 24 May 02 01:37:49 PM PDT 24 46171860 ps
T970 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3962041670 May 02 01:38:06 PM PDT 24 May 02 01:38:11 PM PDT 24 1579821377 ps
T971 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3183401450 May 02 01:37:46 PM PDT 24 May 02 01:37:51 PM PDT 24 1409217258 ps
T86 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3012401529 May 02 01:37:36 PM PDT 24 May 02 01:38:04 PM PDT 24 3884345019 ps
T972 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3086888339 May 02 01:37:58 PM PDT 24 May 02 01:38:00 PM PDT 24 22535425 ps
T973 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1409212468 May 02 01:38:07 PM PDT 24 May 02 01:38:13 PM PDT 24 450792573 ps
T974 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1819774030 May 02 01:37:59 PM PDT 24 May 02 01:38:05 PM PDT 24 7579094432 ps
T975 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1618165783 May 02 01:37:58 PM PDT 24 May 02 01:38:00 PM PDT 24 38028622 ps
T976 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1224428140 May 02 01:37:58 PM PDT 24 May 02 01:38:03 PM PDT 24 386577622 ps
T977 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.93870026 May 02 01:37:37 PM PDT 24 May 02 01:37:39 PM PDT 24 24261321 ps
T87 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.534826380 May 02 01:37:59 PM PDT 24 May 02 01:38:26 PM PDT 24 3711876899 ps
T978 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3114203060 May 02 01:37:35 PM PDT 24 May 02 01:37:39 PM PDT 24 57883761 ps
T979 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.443142456 May 02 01:37:37 PM PDT 24 May 02 01:37:42 PM PDT 24 706075475 ps
T980 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.873383456 May 02 01:37:47 PM PDT 24 May 02 01:37:49 PM PDT 24 14241826 ps
T981 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1927857296 May 02 01:38:06 PM PDT 24 May 02 01:38:36 PM PDT 24 7552403166 ps
T982 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1410719193 May 02 01:37:58 PM PDT 24 May 02 01:38:02 PM PDT 24 210405168 ps
T983 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4138782589 May 02 01:37:46 PM PDT 24 May 02 01:37:48 PM PDT 24 28940647 ps
T984 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.939674120 May 02 01:37:33 PM PDT 24 May 02 01:37:37 PM PDT 24 273346606 ps
T985 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.659166724 May 02 01:37:56 PM PDT 24 May 02 01:37:58 PM PDT 24 112003950 ps
T986 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4083968695 May 02 01:38:03 PM PDT 24 May 02 01:38:07 PM PDT 24 182625971 ps
T987 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.676899364 May 02 01:37:36 PM PDT 24 May 02 01:37:39 PM PDT 24 64298594 ps
T988 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2647226173 May 02 01:37:39 PM PDT 24 May 02 01:37:42 PM PDT 24 15426360 ps
T989 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.404798147 May 02 01:38:01 PM PDT 24 May 02 01:38:02 PM PDT 24 30137442 ps
T990 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3656452599 May 02 01:37:36 PM PDT 24 May 02 01:38:05 PM PDT 24 15354137752 ps
T991 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1965426949 May 02 01:37:45 PM PDT 24 May 02 01:37:47 PM PDT 24 17250686 ps
T992 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.798580811 May 02 01:37:46 PM PDT 24 May 02 01:37:48 PM PDT 24 27708915 ps
T88 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.20250573 May 02 01:37:37 PM PDT 24 May 02 01:38:29 PM PDT 24 7661847744 ps
T993 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.746340720 May 02 01:37:45 PM PDT 24 May 02 01:37:47 PM PDT 24 22611819 ps
T994 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.246211941 May 02 01:37:58 PM PDT 24 May 02 01:38:02 PM PDT 24 53647248 ps
T995 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2602959865 May 02 01:37:57 PM PDT 24 May 02 01:38:01 PM PDT 24 267981627 ps
T996 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3927309248 May 02 01:38:00 PM PDT 24 May 02 01:38:02 PM PDT 24 45659087 ps
T997 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4021746315 May 02 01:38:07 PM PDT 24 May 02 01:38:09 PM PDT 24 23410535 ps
T126 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.962279890 May 02 01:37:59 PM PDT 24 May 02 01:38:03 PM PDT 24 631956208 ps
T998 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2898853595 May 02 01:37:38 PM PDT 24 May 02 01:37:44 PM PDT 24 2042513077 ps
T999 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4273087066 May 02 01:37:29 PM PDT 24 May 02 01:37:58 PM PDT 24 3862676758 ps
T1000 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2176711160 May 02 01:37:37 PM PDT 24 May 02 01:37:42 PM PDT 24 352270586 ps
T125 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4195920774 May 02 01:37:56 PM PDT 24 May 02 01:37:59 PM PDT 24 183081702 ps
T1001 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2838550164 May 02 01:37:59 PM PDT 24 May 02 01:38:05 PM PDT 24 355317435 ps
T1002 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1328340755 May 02 01:37:32 PM PDT 24 May 02 01:37:34 PM PDT 24 137752487 ps
T1003 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3564795059 May 02 01:37:34 PM PDT 24 May 02 01:37:39 PM PDT 24 689645987 ps
T89 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3754756784 May 02 01:37:37 PM PDT 24 May 02 01:37:40 PM PDT 24 180820619 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%