Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16791248	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150389134

1

T1

1411

T2

178978

T3

8492

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82205043	1			T1	772		T2	98483		T3	4675
values[0x0]	40815044	1			T1	383		T2	47360		T3	2199
values[0x1]	44160295	1			T1	394		T2	51148		T3	2460

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8523244	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158657138

1

T1

1496

T2

188062

T3

8910

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	552915	1			T1	9		T2	343		T3	29
valid_sources[0x01]	571695	1			T1	4		T2	509		T3	41
valid_sources[0x02]	749359	1			T1	1		T2	639		T3	49
valid_sources[0x03]	502043	1			T1	3		T2	787		T3	26
valid_sources[0x04]	521096	1			T1	6		T2	421		T3	32
valid_sources[0x05]	559672	1			T1	8		T2	821		T3	47
valid_sources[0x06]	564976	1			T2	802		T3	28		T7	22
valid_sources[0x07]	515996	1			T1	2		T2	364		T3	32
valid_sources[0x08]	603040	1			T1	6		T2	438		T3	30
valid_sources[0x09]	608760	1			T1	4		T2	659		T3	41
valid_sources[0x0a]	557236	1			T1	1		T2	229		T3	40
valid_sources[0x0b]	578503	1			T1	8		T2	1027		T3	41
valid_sources[0x0c]	502838	1			T1	7		T2	790		T3	38
valid_sources[0x0d]	537593	1			T1	9		T2	500		T3	31
valid_sources[0x0e]	1672666	1			T1	6		T2	75		T3	33
valid_sources[0x0f]	524979	1			T1	6		T2	373		T3	36
valid_sources[0x10]	557804	1			T2	1257		T3	42		T5	11
valid_sources[0x11]	542618	1			T1	6		T2	943		T3	40
valid_sources[0x12]	495118	1			T1	1		T2	1206		T3	31
valid_sources[0x13]	496011	1			T1	1		T2	732		T3	36
valid_sources[0x14]	523435	1			T1	5		T2	1010		T3	39
valid_sources[0x15]	536606	1			T1	2		T2	666		T3	39
valid_sources[0x16]	567853	1			T2	177		T3	27		T7	29
valid_sources[0x17]	500852	1			T1	12		T2	776		T3	49
valid_sources[0x18]	521025	1			T1	9		T2	532		T3	29
valid_sources[0x19]	507113	1			T1	13		T2	1034		T3	30
valid_sources[0x1a]	578196	1			T1	15		T2	1039		T3	33
valid_sources[0x1b]	506131	1			T1	1		T2	2398		T3	36
valid_sources[0x1c]	611020	1			T2	712		T3	42		T7	12
valid_sources[0x1d]	587549	1			T1	4		T2	809		T3	41
valid_sources[0x1e]	492845	1			T1	16		T2	554		T3	33
valid_sources[0x1f]	503319	1			T1	7		T2	1108		T3	22
valid_sources[0x20]	1623143	1			T2	1018		T3	43		T7	47
valid_sources[0x21]	514910	1			T1	4		T2	802		T3	39
valid_sources[0x22]	520104	1			T1	3		T2	491		T3	29
valid_sources[0x23]	510360	1			T1	3		T2	529		T3	30
valid_sources[0x24]	523753	1			T1	8		T2	700		T3	31
valid_sources[0x25]	526705	1			T1	10		T2	414		T3	43
valid_sources[0x26]	528235	1			T1	3		T2	419		T3	37
valid_sources[0x27]	490066	1			T1	11		T2	512		T3	45
valid_sources[0x28]	589080	1			T1	2		T2	384		T3	52
valid_sources[0x29]	1553970	1			T1	7		T2	252		T3	32
valid_sources[0x2a]	542455	1			T1	8		T2	805		T3	40
valid_sources[0x2b]	1682119	1			T1	2		T2	325		T3	44
valid_sources[0x2c]	499198	1			T1	5		T2	443		T3	26
valid_sources[0x2d]	1688457	1			T1	7		T2	704		T3	36
valid_sources[0x2e]	548483	1			T1	6		T2	1639		T3	31
valid_sources[0x2f]	502571	1			T1	11		T2	992		T3	36
valid_sources[0x30]	534688	1			T1	15		T2	970		T3	27
valid_sources[0x31]	539278	1			T1	3		T2	867		T3	51
valid_sources[0x32]	488202	1			T1	7		T2	1110		T3	37
valid_sources[0x33]	540223	1			T1	5		T2	533		T3	39
valid_sources[0x34]	501829	1			T1	6		T2	244		T3	32
valid_sources[0x35]	539149	1			T1	7		T2	795		T3	43
valid_sources[0x36]	544741	1			T1	12		T2	346		T3	27
valid_sources[0x37]	542959	1			T1	16		T2	771		T3	33
valid_sources[0x38]	511343	1			T1	4		T2	1250		T3	28
valid_sources[0x39]	510607	1			T1	1		T2	1380		T3	34
valid_sources[0x3a]	533556	1			T1	2		T2	691		T3	39
valid_sources[0x3b]	504464	1			T1	4		T2	329		T3	48
valid_sources[0x3c]	607817	1			T1	18		T2	1048		T3	34
valid_sources[0x3d]	713243	1			T1	9		T2	988		T3	59
valid_sources[0x3e]	512880	1			T1	5		T2	914		T3	36
valid_sources[0x3f]	627329	1			T1	5		T2	893		T3	28
valid_sources[0x40]	551169	1			T1	3		T2	694		T3	30
valid_sources[0x41]	486670	1			T1	9		T2	518		T3	33
valid_sources[0x42]	505261	1			T1	1		T2	168		T3	33
valid_sources[0x43]	583946	1			T1	9		T2	956		T3	35
valid_sources[0x44]	4556099	1			T1	4		T2	1158		T3	50
valid_sources[0x45]	2198902	1			T1	8		T2	1262		T3	49
valid_sources[0x46]	498019	1			T2	464		T3	27		T7	5
valid_sources[0x47]	1657425	1			T1	2		T2	552		T3	40
valid_sources[0x48]	540940	1			T1	2		T2	213		T3	40
valid_sources[0x49]	496299	1			T1	1		T2	773		T3	32
valid_sources[0x4a]	507628	1			T2	649		T3	42		T7	10
valid_sources[0x4b]	539148	1			T2	472		T3	44		T7	19
valid_sources[0x4c]	513137	1			T2	319		T3	43		T7	2
valid_sources[0x4d]	496062	1			T1	1		T2	473		T3	40
valid_sources[0x4e]	491785	1			T2	617		T3	40		T5	22
valid_sources[0x4f]	532910	1			T2	293		T3	39		T7	8
valid_sources[0x50]	559731	1			T1	10		T2	570		T3	39
valid_sources[0x51]	558411	1			T1	5		T2	1247		T3	45
valid_sources[0x52]	570420	1			T1	2		T2	1558		T3	36
valid_sources[0x53]	518493	1			T1	3		T2	1553		T3	41
valid_sources[0x54]	520246	1			T1	12		T2	214		T3	35
valid_sources[0x55]	531760	1			T2	1118		T3	27		T7	10
valid_sources[0x56]	572761	1			T1	2		T2	1124		T3	35
valid_sources[0x57]	544139	1			T2	731		T3	30		T7	5
valid_sources[0x58]	536820	1			T1	2		T2	969		T3	40
valid_sources[0x59]	537244	1			T1	17		T2	322		T3	37
valid_sources[0x5a]	509718	1			T1	5		T2	220		T3	31
valid_sources[0x5b]	497462	1			T1	2		T2	760		T3	28
valid_sources[0x5c]	496895	1			T1	4		T2	658		T3	28
valid_sources[0x5d]	533138	1			T1	5		T2	1644		T3	32
valid_sources[0x5e]	567039	1			T1	9		T2	561		T3	28
valid_sources[0x5f]	506409	1			T1	1		T2	752		T3	39
valid_sources[0x60]	536519	1			T1	5		T2	953		T3	34
valid_sources[0x61]	746144	1			T1	21		T2	613		T3	35
valid_sources[0x62]	581060	1			T1	6		T2	541		T3	41
valid_sources[0x63]	1988151	1			T1	11		T2	696		T3	28
valid_sources[0x64]	507746	1			T1	7		T2	1134		T3	32
valid_sources[0x65]	2087358	1			T1	9		T2	943		T3	26
valid_sources[0x66]	555864	1			T1	2		T2	390		T3	41
valid_sources[0x67]	527931	1			T1	1		T2	635		T3	27
valid_sources[0x68]	520516	1			T1	4		T2	1303		T3	35
valid_sources[0x69]	813633	1			T1	10		T2	1181		T3	32
valid_sources[0x6a]	548408	1			T1	3		T2	615		T3	37
valid_sources[0x6b]	549973	1			T1	6		T2	1056		T3	37
valid_sources[0x6c]	577030	1			T1	6		T2	416		T3	23
valid_sources[0x6d]	734763	1			T1	9		T2	1249		T3	32
valid_sources[0x6e]	520546	1			T2	524		T3	35		T5	15
valid_sources[0x6f]	597663	1			T1	5		T2	270		T3	33
valid_sources[0x70]	624339	1			T1	9		T2	416		T3	35
valid_sources[0x71]	499145	1			T1	5		T2	400		T3	38
valid_sources[0x72]	551362	1			T1	1		T2	592		T3	28
valid_sources[0x73]	569603	1			T1	9		T2	315		T3	40
valid_sources[0x74]	553072	1			T1	6		T2	1284		T3	37
valid_sources[0x75]	556374	1			T1	4		T2	303		T3	53
valid_sources[0x76]	633738	1			T1	3		T2	784		T3	23
valid_sources[0x77]	587688	1			T1	12		T2	434		T3	40
valid_sources[0x78]	514525	1			T1	15		T2	551		T3	36
valid_sources[0x79]	543171	1			T1	11		T2	1028		T3	32
valid_sources[0x7a]	597725	1			T2	456		T3	53		T7	2
valid_sources[0x7b]	510535	1			T1	19		T2	1041		T3	40
valid_sources[0x7c]	498424	1			T1	2		T2	632		T3	36
valid_sources[0x7d]	495910	1			T1	5		T2	241		T3	31
valid_sources[0x7e]	604711	1			T2	1915		T3	26		T7	38
valid_sources[0x7f]	539975	1			T1	1		T2	627		T3	37
valid_sources[0x80]	499185	1			T2	1803		T3	24		T7	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73768701

1

T1

707

T2

89510

T3

4249

values[0x0]

all_enables

biggest_size

38308346

1

T1

370

T2

44685

T3

2096

values[0x1]

all_enables

biggest_size

38312087

1

T1

334

T2

44783

T3

2147

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36468	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

169663

1

T2

7

T4

14

T5

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	59066	1			T4	18		T5	40		T8	1239
values[0x0]	70976	1			T2	18		T3	1		T4	13
values[0x1]	76089	1			T1	2		T2	14		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27461	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

178670

1

T2

9

T4

14

T5

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	724	1			T2	1		T5	1		T25	5
valid_sources[0x01]	1017	1			T25	18		T20	1		T49	8
valid_sources[0x02]	642	1			T2	1		T25	3		T6	1
valid_sources[0x03]	581	1			T4	1		T8	28		T25	10
valid_sources[0x04]	860	1			T4	1		T9	15		T18	2
valid_sources[0x05]	787	1			T8	65		T70	1		T25	2
valid_sources[0x06]	687	1			T25	13		T49	10		T83	16
valid_sources[0x07]	920	1			T5	2		T25	6		T49	15
valid_sources[0x08]	675	1			T4	1		T25	11		T49	19
valid_sources[0x09]	874	1			T25	16		T20	1		T49	22
valid_sources[0x0a]	587	1			T25	31		T127	8		T49	10
valid_sources[0x0b]	603	1			T8	3		T42	1		T25	31
valid_sources[0x0c]	731	1			T9	1		T25	6		T126	6
valid_sources[0x0d]	868	1			T4	1		T42	1		T25	27
valid_sources[0x0e]	981	1			T9	1		T25	6		T46	1
valid_sources[0x0f]	805	1			T25	15		T20	1		T49	11
valid_sources[0x10]	780	1			T1	1		T25	15		T125	1
valid_sources[0x11]	1132	1			T20	2		T49	18		T55	1
valid_sources[0x12]	795	1			T25	21		T46	3		T49	12
valid_sources[0x13]	804	1			T125	1		T20	2		T49	7
valid_sources[0x14]	565	1			T2	1		T9	3		T25	6
valid_sources[0x15]	788	1			T5	1		T25	12		T49	9
valid_sources[0x16]	820	1			T9	121		T43	1		T25	16
valid_sources[0x17]	817	1			T25	4		T49	14		T21	1
valid_sources[0x18]	701	1			T2	1		T9	1		T25	1
valid_sources[0x19]	631	1			T5	1		T8	3		T25	22
valid_sources[0x1a]	1122	1			T8	7		T25	12		T49	9
valid_sources[0x1b]	1162	1			T9	2		T25	10		T49	28
valid_sources[0x1c]	490	1			T25	6		T49	12		T48	18
valid_sources[0x1d]	803	1			T8	102		T25	14		T46	2
valid_sources[0x1e]	442	1			T25	17		T20	1		T49	12
valid_sources[0x1f]	702	1			T25	20		T126	1		T49	30
valid_sources[0x20]	643	1			T5	1		T8	1		T9	7
valid_sources[0x21]	1091	1			T42	1		T25	13		T6	2
valid_sources[0x22]	742	1			T25	2		T46	1		T49	18
valid_sources[0x23]	1011	1			T9	1		T25	7		T20	2
valid_sources[0x24]	657	1			T25	3		T49	21		T48	19
valid_sources[0x25]	809	1			T2	1		T4	1		T5	1
valid_sources[0x26]	578	1			T25	11		T46	1		T49	5
valid_sources[0x27]	725	1			T25	15		T6	2		T20	1
valid_sources[0x28]	985	1			T2	1		T8	71		T25	5
valid_sources[0x29]	850	1			T25	7		T19	6		T49	6
valid_sources[0x2a]	1074	1			T25	10		T133	1		T49	10
valid_sources[0x2b]	905	1			T8	84		T25	4		T134	1
valid_sources[0x2c]	586	1			T25	7		T125	1		T49	17
valid_sources[0x2d]	523	1			T25	1		T20	1		T49	12
valid_sources[0x2e]	1159	1			T25	9		T49	17		T55	1
valid_sources[0x2f]	732	1			T25	16		T125	2		T49	16
valid_sources[0x30]	963	1			T8	3		T25	11		T135	1
valid_sources[0x31]	900	1			T5	2		T49	8		T48	17
valid_sources[0x32]	642	1			T42	1		T25	1		T6	2
valid_sources[0x33]	1072	1			T25	6		T6	1		T49	31
valid_sources[0x34]	1136	1			T18	2		T25	5		T46	1
valid_sources[0x35]	1163	1			T9	41		T25	16		T6	1
valid_sources[0x36]	676	1			T5	2		T25	9		T20	1
valid_sources[0x37]	946	1			T127	4		T49	23		T48	32
valid_sources[0x38]	631	1			T5	1		T25	9		T49	26
valid_sources[0x39]	762	1			T2	2		T5	1		T8	11
valid_sources[0x3a]	753	1			T5	1		T8	4		T25	6
valid_sources[0x3b]	575	1			T25	10		T125	1		T49	12
valid_sources[0x3c]	580	1			T4	2		T5	1		T9	1
valid_sources[0x3d]	488	1			T25	7		T76	1		T20	1
valid_sources[0x3e]	754	1			T25	15		T49	17		T48	21
valid_sources[0x3f]	875	1			T2	1		T25	1		T20	1
valid_sources[0x40]	708	1			T8	170		T9	3		T25	26
valid_sources[0x41]	812	1			T2	1		T9	1		T25	16
valid_sources[0x42]	693	1			T5	1		T25	11		T125	1
valid_sources[0x43]	937	1			T5	1		T25	6		T49	27
valid_sources[0x44]	520	1			T25	16		T20	1		T49	19
valid_sources[0x45]	566	1			T4	1		T9	5		T25	11
valid_sources[0x46]	1098	1			T25	6		T49	12		T21	1
valid_sources[0x47]	647	1			T8	1		T25	8		T49	21
valid_sources[0x48]	754	1			T5	1		T25	11		T6	2
valid_sources[0x49]	1097	1			T2	1		T25	13		T6	1
valid_sources[0x4a]	796	1			T25	13		T29	1		T41	7
valid_sources[0x4b]	604	1			T8	2		T25	19		T44	11
valid_sources[0x4c]	1106	1			T25	4		T49	4		T48	24
valid_sources[0x4d]	1490	1			T5	1		T25	6		T134	1
valid_sources[0x4e]	631	1			T5	1		T9	2		T25	11
valid_sources[0x4f]	608	1			T5	1		T8	67		T25	6
valid_sources[0x50]	1061	1			T2	1		T25	2		T20	1
valid_sources[0x51]	1306	1			T8	106		T25	18		T49	14
valid_sources[0x52]	791	1			T25	7		T129	2		T126	1
valid_sources[0x53]	485	1			T25	7		T20	2		T49	4
valid_sources[0x54]	539	1			T42	1		T73	1		T25	28
valid_sources[0x55]	933	1			T5	1		T25	30		T46	1
valid_sources[0x56]	898	1			T4	1		T5	1		T9	1
valid_sources[0x57]	796	1			T73	2		T25	6		T49	13
valid_sources[0x58]	446	1			T25	7		T49	17		T55	1
valid_sources[0x59]	962	1			T8	3		T9	6		T25	26
valid_sources[0x5a]	1287	1			T25	11		T20	1		T49	8
valid_sources[0x5b]	892	1			T42	1		T25	2		T41	1
valid_sources[0x5c]	1263	1			T25	6		T6	1		T129	1
valid_sources[0x5d]	537	1			T9	1		T25	14		T129	1
valid_sources[0x5e]	1315	1			T8	44		T9	5		T25	5
valid_sources[0x5f]	573	1			T4	1		T25	14		T129	2
valid_sources[0x60]	701	1			T27	1		T25	16		T49	18
valid_sources[0x61]	441	1			T5	1		T25	1		T49	13
valid_sources[0x62]	880	1			T42	1		T25	6		T6	1
valid_sources[0x63]	613	1			T6	2		T49	13		T55	1
valid_sources[0x64]	672	1			T9	3		T42	1		T25	16
valid_sources[0x65]	515	1			T4	1		T9	3		T25	13
valid_sources[0x66]	935	1			T25	19		T129	1		T46	1
valid_sources[0x67]	809	1			T8	3		T20	1		T49	29
valid_sources[0x68]	729	1			T25	23		T49	25		T21	2
valid_sources[0x69]	781	1			T4	1		T25	5		T49	11
valid_sources[0x6a]	551	1			T4	1		T5	2		T9	21
valid_sources[0x6b]	845	1			T2	1		T10	3		T25	22
valid_sources[0x6c]	590	1			T2	3		T25	9		T129	1
valid_sources[0x6d]	674	1			T25	3		T125	3		T49	4
valid_sources[0x6e]	1209	1			T18	1		T25	3		T125	2
valid_sources[0x6f]	945	1			T2	1		T9	138		T25	2
valid_sources[0x70]	1055	1			T5	2		T9	1		T42	1
valid_sources[0x71]	1123	1			T5	1		T9	3		T25	37
valid_sources[0x72]	790	1			T2	1		T4	1		T8	103
valid_sources[0x73]	993	1			T4	1		T8	100		T9	1
valid_sources[0x74]	1045	1			T5	1		T8	256		T9	3
valid_sources[0x75]	897	1			T3	2		T95	1		T25	21
valid_sources[0x76]	845	1			T25	14		T49	10		T48	24
valid_sources[0x77]	719	1			T25	1		T49	29		T55	3
valid_sources[0x78]	793	1			T25	15		T20	1		T49	23
valid_sources[0x79]	569	1			T9	109		T10	5		T25	12
valid_sources[0x7a]	1224	1			T5	1		T9	25		T136	2
valid_sources[0x7b]	806	1			T5	1		T9	106		T25	2
valid_sources[0x7c]	762	1			T8	73		T25	10		T46	1
valid_sources[0x7d]	582	1			T9	1		T25	3		T133	1
valid_sources[0x7e]	862	1			T5	2		T25	15		T49	24
valid_sources[0x7f]	903	1			T8	127		T25	15		T20	1
valid_sources[0x80]	933	1			T5	1		T8	102		T25	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46113

1

T4

9

T5

26

T8

1152

values[0x0]

all_enables

biggest_size

62665

1

T2

6

T4

4

T5

7

values[0x1]

all_enables

biggest_size

60885

1

T2

1

T4

1

T5

2