Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16673091

1

T1

138

T2

15524

T3

842

full_word

146882457

1

T1

1411

T2

154039

T3

8492

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	163555218	1			T1	1549		T2	169563		T3	9334
auto[TlIntgErrCmd]	118	1			T103	9		T104	5		T105	3
auto[TlIntgErrData]	113	1			T103	8		T104	10		T105	6
auto[TlIntgErrBoth]	99	1			T103	3		T104	5		T105	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78469500

1

T1

772

T2

71055

T3

4675

auto[1]

85086048

1

T1

777

T2

98508

T3

4659

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8139560	1			T1	65		T2	6484		T3	426
auto[TlIntgErrNone]	partial	auto[1]	8533229	1			T1	73		T2	9040		T3	416
auto[TlIntgErrNone]	full_word	auto[0]	70329782	1			T1	707		T2	64571		T3	4249
auto[TlIntgErrNone]	full_word	auto[1]	76552647	1			T1	704		T2	89468		T3	4243
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T103	2		T104	3		T112	4
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T103	7		T104	2		T105	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T116	1		T121	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T112	1		T119	1		T122	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T103	1		T104	7		T105	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T103	7		T104	3		T105	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T105	1		T117	2		T114	3
auto[TlIntgErrData]	full_word	auto[1]	4	1			T123	1		T120	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T103	2		T112	3		T113	1
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T103	1		T104	4		T112	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T123	1		T117	1		T118	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T104	1		T105	1		T118	1