Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	846635	1			T1	187		T3	1362		T7	351
auto[1]	11127805	1			T1	57		T2	9392		T3	353
auto[2]	639406	1			T1	188		T3	1207		T7	281
auto[3]	10821914	1			T1	25		T2	6623		T3	192

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14996023	1			T1	363		T2	13418		T3	2406
auto[1]	2120961	1			T1	56		T2	1230		T3	352
auto[2]	2151606	1			T1	35		T2	1284		T3	314
auto[3]	4167170	1			T1	3		T2	83		T3	42

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10215217

1

T1

457

T2

16014

T3

3114

auto[1]

13220543

1

T2

1

T12

20633

T43

160843

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	337900	1			T1	160		T3	1117		T7	8
auto[0]	auto[0]	auto[1]	34629	1			T1	13		T3	127		T7	60
auto[0]	auto[0]	auto[2]	34779	1			T1	14		T3	109		T7	61
auto[0]	auto[0]	auto[3]	65262	1			T3	9		T7	222		T13	399
auto[0]	auto[1]	auto[0]	3477822	1			T1	32		T2	7870		T3	218
auto[0]	auto[1]	auto[1]	368351	1			T1	22		T2	683		T3	105
auto[0]	auto[1]	auto[2]	396529	1			T1	3		T2	795		T3	14
auto[0]	auto[1]	auto[3]	577253	1			T2	43		T3	16		T7	241
auto[0]	auto[2]	auto[0]	240432	1			T1	156		T3	988		T7	15
auto[0]	auto[2]	auto[1]	28860	1			T1	20		T3	105		T7	53
auto[0]	auto[2]	auto[2]	24228	1			T1	10		T3	103		T7	38
auto[0]	auto[2]	auto[3]	44191	1			T1	2		T3	11		T7	175
auto[0]	auto[3]	auto[0]	3297265	1			T1	15		T2	5547		T3	83
auto[0]	auto[3]	auto[1]	374137	1			T1	1		T2	547		T3	15
auto[0]	auto[3]	auto[2]	389330	1			T1	8		T2	489		T3	88
auto[0]	auto[3]	auto[3]	524249	1			T1	1		T2	40		T3	6
auto[1]	auto[0]	auto[0]	12296	1			T99	1027		T130	793		T131	1029
auto[1]	auto[0]	auto[1]	55584	1			T99	4639		T130	3559		T131	4466
auto[1]	auto[0]	auto[2]	55576	1			T99	4515		T132	1		T130	3665
auto[1]	auto[0]	auto[3]	250609	1			T72	4		T99	20818		T81	2
auto[1]	auto[1]	auto[0]	3810210	1			T2	1		T12	131		T43	67276
auto[1]	auto[1]	auto[1]	628932	1			T12	1741		T43	5872		T95	6429
auto[1]	auto[1]	auto[2]	587898	1			T12	620		T43	6656		T95	6501
auto[1]	auto[1]	auto[3]	1280810	1			T12	7855		T43	582		T95	646
auto[1]	auto[2]	auto[0]	11037	1			T99	862		T130	772		T131	919
auto[1]	auto[2]	auto[1]	49857	1			T99	4334		T130	3418		T131	4130
auto[1]	auto[2]	auto[2]	43516	1			T99	3956		T130	2394		T131	3782
auto[1]	auto[2]	auto[3]	197285	1			T99	17698		T130	11057		T131	16839
auto[1]	auto[3]	auto[0]	3809061	1			T12	117		T43	67159		T95	65103
auto[1]	auto[3]	auto[1]	580611	1			T12	578		T43	6615		T95	6472
auto[1]	auto[3]	auto[2]	619750	1			T12	1709		T43	6032		T95	6458
auto[1]	auto[3]	auto[3]	1227511	1			T12	7882		T43	651		T95	661