Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1099881741	168345	0	0
ctrl_regwen_rd_A	1099881741	6828	0	0
exec_rd_A	1099881741	5804	0	0
exec_regwen_rd_A	1099881741	6617	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1099881741	168345	0	0
T8	236836	4928	0	0
T9	52567	1255	0	0
T10	473168	0	0	0
T11	137489	0	0	0
T12	121629	0	0	0
T13	62144	0	0	0
T17	1854	0	0	0
T25	0	3015	0	0
T27	33670	0	0	0
T42	214366	0	0	0
T43	262595	0	0	0
T48	0	5058	0	0
T49	0	4791	0	0
T50	0	5585	0	0
T51	0	1910	0	0
T52	0	1713	0	0
T53	0	709	0	0
T54	0	3298	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1099881741	6828	0	0
T9	52567	407	0	0
T10	473168	0	0	0
T11	137489	0	0	0
T12	121629	0	0	0
T13	62144	0	0	0
T17	1854	0	0	0
T25	0	259	0	0
T27	33670	0	0	0
T42	214366	0	0	0
T43	262595	0	0	0
T48	0	1089	0	0
T59	0	33	0	0
T94	125840	0	0	0
T106	0	359	0	0
T107	0	689	0	0
T108	0	270	0	0
T109	0	854	0	0
T110	0	232	0	0
T111	0	329	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1099881741	5804	0	0
T9	52567	337	0	0
T10	473168	0	0	0
T11	137489	0	0	0
T12	121629	0	0	0
T13	62144	0	0	0
T17	1854	0	0	0
T25	0	223	0	0
T27	33670	0	0	0
T42	214366	0	0	0
T43	262595	0	0	0
T48	0	863	0	0
T59	0	40	0	0
T94	125840	0	0	0
T106	0	252	0	0
T107	0	438	0	0
T108	0	197	0	0
T109	0	666	0	0
T110	0	187	0	0
T111	0	298	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1099881741	6617	0	0
T9	52567	392	0	0
T10	473168	0	0	0
T11	137489	0	0	0
T12	121629	0	0	0
T13	62144	0	0	0
T17	1854	0	0	0
T25	0	320	0	0
T27	33670	0	0	0
T42	214366	0	0	0
T43	262595	0	0	0
T48	0	1049	0	0
T59	0	24	0	0
T94	125840	0	0	0
T106	0	384	0	0
T107	0	556	0	0
T108	0	225	0	0
T109	0	885	0	0
T110	0	244	0	0
T111	0	214	0	0