Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15780295	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

164297045

1

T1

242253

T2

5538

T3

144299

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88677033	1			T1	122708		T2	3090		T3	734877
values[0x0]	44127870	1			T1	610663		T2	1427		T3	364039
values[0x1]	47272437	1			T1	617182		T2	1593		T3	370890

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8035616	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

172041724

1

T1

243891

T2

5828

T3

145639

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	612078	1			T1	9586		T2	12		T3	8205
valid_sources[0x01]	697836	1			T1	9500		T2	14		T3	725
valid_sources[0x02]	579136	1			T1	9566		T2	29		T3	629
valid_sources[0x03]	571141	1			T1	9571		T2	4		T3	499
valid_sources[0x04]	1450345	1			T1	9913		T2	12		T3	620
valid_sources[0x05]	650536	1			T1	9636		T2	12		T3	572
valid_sources[0x06]	788891	1			T1	9623		T2	28		T3	636
valid_sources[0x07]	636843	1			T1	9642		T2	17		T3	582
valid_sources[0x08]	623034	1			T1	9641		T2	25		T3	543
valid_sources[0x09]	626310	1			T1	9815		T2	17		T3	431
valid_sources[0x0a]	629045	1			T1	9431		T2	33		T3	561
valid_sources[0x0b]	976555	1			T1	9644		T2	5		T3	487
valid_sources[0x0c]	573030	1			T1	9433		T2	7		T3	600
valid_sources[0x0d]	629671	1			T1	9772		T2	27		T3	1163
valid_sources[0x0e]	589268	1			T1	9571		T2	25		T3	523
valid_sources[0x0f]	624383	1			T1	9605		T2	22		T3	683
valid_sources[0x10]	636839	1			T1	9718		T2	18		T3	491
valid_sources[0x11]	593383	1			T1	9745		T2	27		T3	10702
valid_sources[0x12]	660983	1			T1	9761		T2	15		T3	8051
valid_sources[0x13]	596816	1			T1	9571		T2	29		T3	602
valid_sources[0x14]	598727	1			T1	9488		T2	48		T3	573
valid_sources[0x15]	598550	1			T1	9748		T2	18		T3	400
valid_sources[0x16]	623256	1			T1	9712		T2	11		T3	574
valid_sources[0x17]	591705	1			T1	9492		T2	21		T3	543
valid_sources[0x18]	608836	1			T1	9853		T2	15		T3	676
valid_sources[0x19]	578793	1			T1	9646		T2	24		T3	597
valid_sources[0x1a]	616752	1			T1	9530		T2	18		T3	588
valid_sources[0x1b]	708286	1			T1	9762		T2	36		T3	774
valid_sources[0x1c]	660204	1			T1	9434		T2	13		T3	599
valid_sources[0x1d]	1765481	1			T1	9487		T2	21		T3	118019
valid_sources[0x1e]	586206	1			T1	9603		T2	15		T3	603
valid_sources[0x1f]	614584	1			T1	9659		T2	18		T3	5928
valid_sources[0x20]	584151	1			T1	9654		T2	26		T3	506
valid_sources[0x21]	580725	1			T1	9402		T2	20		T3	516
valid_sources[0x22]	627704	1			T1	9594		T2	16		T3	733
valid_sources[0x23]	584032	1			T1	9321		T2	23		T3	507
valid_sources[0x24]	600044	1			T1	9409		T2	3		T3	764
valid_sources[0x25]	586025	1			T1	9691		T2	33		T3	561
valid_sources[0x26]	616661	1			T1	9510		T2	38		T3	12617
valid_sources[0x27]	634456	1			T1	9636		T2	18		T3	531
valid_sources[0x28]	608305	1			T1	9410		T2	44		T3	549
valid_sources[0x29]	648992	1			T1	9589		T2	20		T3	616
valid_sources[0x2a]	626301	1			T1	9796		T2	4		T3	6888
valid_sources[0x2b]	614695	1			T1	9857		T2	18		T3	476
valid_sources[0x2c]	605021	1			T1	9643		T2	17		T3	631
valid_sources[0x2d]	577341	1			T1	9734		T2	17		T3	658
valid_sources[0x2e]	596056	1			T1	9542		T2	23		T3	763
valid_sources[0x2f]	585761	1			T1	9497		T2	11		T3	521
valid_sources[0x30]	578173	1			T1	9573		T2	26		T3	603
valid_sources[0x31]	594479	1			T1	9543		T2	23		T3	19984
valid_sources[0x32]	579775	1			T1	9395		T2	8		T3	453
valid_sources[0x33]	589692	1			T1	9819		T2	17		T3	450
valid_sources[0x34]	692652	1			T1	9505		T2	16		T3	610
valid_sources[0x35]	615007	1			T1	9623		T2	14		T3	531
valid_sources[0x36]	613193	1			T1	9484		T2	32		T3	17891
valid_sources[0x37]	622829	1			T1	9919		T2	37		T3	569
valid_sources[0x38]	612334	1			T1	9422		T2	40		T3	524
valid_sources[0x39]	591280	1			T1	9538		T2	29		T3	568
valid_sources[0x3a]	599234	1			T1	9715		T2	8		T3	599
valid_sources[0x3b]	578963	1			T1	9603		T2	32		T3	745
valid_sources[0x3c]	613660	1			T1	9649		T2	17		T3	863
valid_sources[0x3d]	600123	1			T1	9535		T2	51		T3	489
valid_sources[0x3e]	670556	1			T1	9669		T2	24		T3	619
valid_sources[0x3f]	609438	1			T1	9453		T2	31		T3	651
valid_sources[0x40]	604924	1			T1	9782		T2	7		T3	606
valid_sources[0x41]	635991	1			T1	9719		T2	21		T3	622
valid_sources[0x42]	774124	1			T1	9403		T2	8		T3	594
valid_sources[0x43]	782512	1			T1	9327		T2	15		T3	585
valid_sources[0x44]	628409	1			T1	9268		T2	10		T3	650
valid_sources[0x45]	657916	1			T1	9720		T2	36		T3	538
valid_sources[0x46]	596439	1			T1	9241		T2	32		T3	623
valid_sources[0x47]	591124	1			T1	9398		T2	31		T3	530
valid_sources[0x48]	616831	1			T1	9536		T2	7		T3	562
valid_sources[0x49]	580903	1			T1	9631		T2	20		T3	606
valid_sources[0x4a]	605892	1			T1	9429		T2	51		T3	408
valid_sources[0x4b]	669071	1			T1	9645		T2	11		T3	693
valid_sources[0x4c]	586681	1			T1	9615		T2	19		T3	515
valid_sources[0x4d]	571487	1			T1	9595		T2	22		T3	693
valid_sources[0x4e]	614822	1			T1	9648		T2	38		T3	557
valid_sources[0x4f]	622918	1			T1	9202		T2	14		T3	580
valid_sources[0x50]	579910	1			T1	9460		T2	20		T3	631
valid_sources[0x51]	570203	1			T1	9828		T2	24		T3	591
valid_sources[0x52]	647298	1			T1	9714		T2	29		T3	598
valid_sources[0x53]	574484	1			T1	9534		T2	22		T3	562
valid_sources[0x54]	595471	1			T1	9921		T2	16		T3	683
valid_sources[0x55]	1494012	1			T1	9628		T2	25		T3	488
valid_sources[0x56]	594853	1			T1	9830		T2	12		T3	531
valid_sources[0x57]	574396	1			T1	9662		T2	42		T3	718
valid_sources[0x58]	618150	1			T1	9666		T2	11		T3	3235
valid_sources[0x59]	654060	1			T1	9558		T2	18		T3	643
valid_sources[0x5a]	581051	1			T1	9507		T2	22		T3	665
valid_sources[0x5b]	657602	1			T1	9775		T2	23		T3	573
valid_sources[0x5c]	585181	1			T1	9511		T2	18		T3	588
valid_sources[0x5d]	653326	1			T1	9767		T2	5		T3	674
valid_sources[0x5e]	581767	1			T1	9849		T2	29		T3	705
valid_sources[0x5f]	610106	1			T1	9595		T2	41		T3	470
valid_sources[0x60]	648314	1			T1	9547		T2	23		T3	652
valid_sources[0x61]	1269695	1			T1	9558		T2	34		T3	566
valid_sources[0x62]	624215	1			T1	9693		T2	44		T3	574
valid_sources[0x63]	591934	1			T1	9473		T2	22		T3	574
valid_sources[0x64]	629358	1			T1	9528		T2	17		T3	532
valid_sources[0x65]	625012	1			T1	9485		T2	21		T3	537
valid_sources[0x66]	586771	1			T1	9837		T2	17		T3	525
valid_sources[0x67]	588991	1			T1	9435		T2	25		T3	557
valid_sources[0x68]	625095	1			T1	9604		T2	47		T3	657
valid_sources[0x69]	602181	1			T1	9579		T2	12		T3	502
valid_sources[0x6a]	571844	1			T1	9646		T2	19		T3	663
valid_sources[0x6b]	605187	1			T1	9581		T2	10		T3	909
valid_sources[0x6c]	1305538	1			T1	9506		T2	33		T3	554
valid_sources[0x6d]	587127	1			T1	9736		T2	6		T3	562
valid_sources[0x6e]	770310	1			T1	9882		T2	26		T3	535
valid_sources[0x6f]	642433	1			T1	9471		T2	22		T3	451
valid_sources[0x70]	596662	1			T1	9446		T2	16		T3	507
valid_sources[0x71]	575864	1			T1	9676		T2	19		T3	586
valid_sources[0x72]	604159	1			T1	9292		T2	28		T3	603
valid_sources[0x73]	2147352	1			T1	9330		T2	11		T3	578
valid_sources[0x74]	629005	1			T1	9486		T2	16		T3	531
valid_sources[0x75]	631369	1			T1	9752		T2	12		T3	600
valid_sources[0x76]	592274	1			T1	9549		T2	22		T3	545
valid_sources[0x77]	573097	1			T1	9428		T2	5		T3	527
valid_sources[0x78]	2129485	1			T1	9554		T2	36		T3	608
valid_sources[0x79]	1331475	1			T1	9856		T2	18		T3	528
valid_sources[0x7a]	836408	1			T1	9721		T2	32		T3	513
valid_sources[0x7b]	579852	1			T1	9673		T2	21		T3	568
valid_sources[0x7c]	626233	1			T1	9711		T2	33		T3	483
valid_sources[0x7d]	620760	1			T1	9579		T2	14		T3	742
valid_sources[0x7e]	621678	1			T1	9583		T2	25		T3	648
valid_sources[0x7f]	581273	1			T1	9463		T2	38		T3	460
valid_sources[0x80]	742811	1			T1	9599		T2	19		T3	476

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80745221

1

T1

121074

T2

2828

T3

721625

values[0x0]

all_enables

biggest_size

41774160

1

T1

605913

T2

1344

T3

359930

values[0x1]

all_enables

biggest_size

41777664

1

T1

605878

T2

1366

T3

361439

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33167	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149225

1

T1

84

T2

1

T3

69

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53056	1			T1	70		T3	53		T5	54
values[0x0]	62692	1			T1	95		T3	57		T6	4
values[0x1]	66644	1			T1	80		T2	2		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

157404

1

T1

109

T2

1

T3

79

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	562	1			T25	1		T21	3		T23	18
valid_sources[0x01]	696	1			T3	7		T23	9		T57	1
valid_sources[0x02]	959	1			T23	14		T115	1		T42	8
valid_sources[0x03]	454	1			T25	1		T23	10		T115	1
valid_sources[0x04]	562	1			T22	1		T23	14		T42	6
valid_sources[0x05]	825	1			T21	4		T23	10		T131	3
valid_sources[0x06]	739	1			T22	49		T23	12		T57	1
valid_sources[0x07]	841	1			T116	1		T21	1		T22	118
valid_sources[0x08]	723	1			T21	3		T71	2		T23	1
valid_sources[0x09]	600	1			T23	8		T115	1		T131	1
valid_sources[0x0a]	1061	1			T1	245		T23	16		T51	1
valid_sources[0x0b]	855	1			T21	2		T23	9		T98	1
valid_sources[0x0c]	685	1			T41	1		T23	9		T51	7
valid_sources[0x0d]	881	1			T21	3		T23	14		T52	2
valid_sources[0x0e]	657	1			T23	9		T42	4		T43	8
valid_sources[0x0f]	653	1			T23	3		T132	6		T42	5
valid_sources[0x10]	835	1			T21	2		T23	11		T24	46
valid_sources[0x11]	642	1			T22	2		T23	12		T49	1
valid_sources[0x12]	667	1			T23	13		T51	1		T57	2
valid_sources[0x13]	476	1			T11	1		T23	8		T133	1
valid_sources[0x14]	782	1			T21	4		T23	13		T133	1
valid_sources[0x15]	564	1			T23	7		T131	6		T134	2
valid_sources[0x16]	891	1			T21	2		T23	13		T54	1
valid_sources[0x17]	702	1			T23	13		T42	10		T34	1
valid_sources[0x18]	596	1			T23	11		T58	1		T42	4
valid_sources[0x19]	768	1			T3	1		T21	1		T23	15
valid_sources[0x1a]	620	1			T21	1		T23	11		T51	6
valid_sources[0x1b]	551	1			T22	1		T23	16		T135	1
valid_sources[0x1c]	605	1			T95	5		T23	6		T42	4
valid_sources[0x1d]	713	1			T136	1		T23	7		T133	3
valid_sources[0x1e]	1037	1			T23	13		T24	175		T42	7
valid_sources[0x1f]	594	1			T3	1		T25	2		T23	8
valid_sources[0x20]	736	1			T3	1		T23	1		T51	1
valid_sources[0x21]	747	1			T23	9		T133	2		T131	1
valid_sources[0x22]	808	1			T25	2		T70	1		T23	8
valid_sources[0x23]	608	1			T23	13		T51	1		T24	1
valid_sources[0x24]	822	1			T23	7		T115	2		T137	1
valid_sources[0x25]	787	1			T13	2		T23	7		T58	5
valid_sources[0x26]	855	1			T21	1		T23	13		T77	1
valid_sources[0x27]	941	1			T23	8		T51	2		T42	9
valid_sources[0x28]	682	1			T21	1		T23	12		T51	2
valid_sources[0x29]	1066	1			T3	4		T10	1		T25	4
valid_sources[0x2a]	647	1			T21	2		T23	3		T58	1
valid_sources[0x2b]	627	1			T21	4		T23	18		T50	1
valid_sources[0x2c]	914	1			T21	7		T22	3		T23	7
valid_sources[0x2d]	654	1			T22	165		T23	7		T58	1
valid_sources[0x2e]	691	1			T23	7		T51	2		T58	2
valid_sources[0x2f]	724	1			T23	8		T98	1		T24	91
valid_sources[0x30]	692	1			T21	1		T23	15		T57	1
valid_sources[0x31]	599	1			T23	10		T132	1		T42	5
valid_sources[0x32]	882	1			T87	1		T23	12		T40	2
valid_sources[0x33]	662	1			T39	1		T21	2		T23	9
valid_sources[0x34]	856	1			T21	2		T23	11		T133	1
valid_sources[0x35]	817	1			T23	7		T24	120		T42	14
valid_sources[0x36]	769	1			T21	1		T23	6		T24	1
valid_sources[0x37]	488	1			T7	7		T15	1		T23	15
valid_sources[0x38]	449	1			T23	9		T58	1		T42	6
valid_sources[0x39]	794	1			T21	2		T41	1		T23	11
valid_sources[0x3a]	692	1			T39	1		T23	11		T51	1
valid_sources[0x3b]	548	1			T21	2		T23	11		T137	2
valid_sources[0x3c]	588	1			T3	2		T25	1		T136	1
valid_sources[0x3d]	1038	1			T23	7		T51	1		T24	5
valid_sources[0x3e]	508	1			T21	2		T23	16		T24	2
valid_sources[0x3f]	570	1			T26	1		T23	9		T133	1
valid_sources[0x40]	743	1			T23	24		T24	3		T133	1
valid_sources[0x41]	690	1			T21	2		T23	8		T42	5
valid_sources[0x42]	983	1			T23	9		T97	1		T138	2
valid_sources[0x43]	640	1			T23	11		T51	1		T42	3
valid_sources[0x44]	507	1			T15	1		T23	15		T139	1
valid_sources[0x45]	622	1			T27	1		T41	2		T23	7
valid_sources[0x46]	603	1			T21	4		T23	15		T140	2
valid_sources[0x47]	954	1			T23	18		T42	1		T33	1
valid_sources[0x48]	641	1			T23	7		T133	1		T42	5
valid_sources[0x49]	504	1			T25	1		T23	16		T115	1
valid_sources[0x4a]	711	1			T3	12		T23	7		T42	4
valid_sources[0x4b]	910	1			T25	1		T23	8		T141	2
valid_sources[0x4c]	699	1			T21	2		T23	14		T51	1
valid_sources[0x4d]	564	1			T21	2		T23	4		T142	1
valid_sources[0x4e]	726	1			T13	3		T23	9		T24	44
valid_sources[0x4f]	506	1			T23	18		T57	1		T115	3
valid_sources[0x50]	586	1			T23	5		T131	1		T134	1
valid_sources[0x51]	578	1			T23	8		T42	6		T30	1
valid_sources[0x52]	691	1			T21	1		T23	7		T42	4
valid_sources[0x53]	662	1			T22	2		T23	22		T115	1
valid_sources[0x54]	671	1			T23	8		T51	1		T42	5
valid_sources[0x55]	770	1			T23	11		T24	81		T133	1
valid_sources[0x56]	878	1			T3	4		T23	7		T131	4
valid_sources[0x57]	593	1			T41	1		T143	5		T131	6
valid_sources[0x58]	1023	1			T23	16		T51	2		T57	2
valid_sources[0x59]	793	1			T3	5		T21	4		T23	9
valid_sources[0x5a]	442	1			T21	1		T23	9		T51	1
valid_sources[0x5b]	478	1			T25	4		T23	4		T51	1
valid_sources[0x5c]	1021	1			T86	5		T22	179		T23	3
valid_sources[0x5d]	559	1			T21	4		T23	10		T144	2
valid_sources[0x5e]	774	1			T23	11		T57	1		T145	20
valid_sources[0x5f]	625	1			T6	1		T25	5		T23	14
valid_sources[0x60]	753	1			T3	1		T21	1		T23	23
valid_sources[0x61]	687	1			T23	15		T51	3		T137	1
valid_sources[0x62]	581	1			T3	3		T21	2		T23	7
valid_sources[0x63]	640	1			T23	8		T58	2		T131	3
valid_sources[0x64]	1019	1			T39	1		T22	46		T23	8
valid_sources[0x65]	1027	1			T5	143		T22	3		T23	14
valid_sources[0x66]	476	1			T3	7		T6	1		T41	2
valid_sources[0x67]	680	1			T23	12		T115	3		T42	6
valid_sources[0x68]	721	1			T10	1		T21	1		T23	9
valid_sources[0x69]	763	1			T21	2		T23	5		T42	2
valid_sources[0x6a]	815	1			T21	1		T23	9		T115	1
valid_sources[0x6b]	879	1			T21	2		T23	12		T58	2
valid_sources[0x6c]	729	1			T70	1		T23	11		T57	1
valid_sources[0x6d]	907	1			T23	10		T133	1		T42	3
valid_sources[0x6e]	670	1			T23	8		T42	9		T43	12
valid_sources[0x6f]	518	1			T13	1		T23	16		T131	4
valid_sources[0x70]	829	1			T23	9		T40	1		T131	2
valid_sources[0x71]	940	1			T21	4		T22	1		T23	17
valid_sources[0x72]	567	1			T21	2		T23	10		T57	1
valid_sources[0x73]	854	1			T3	20		T23	15		T50	1
valid_sources[0x74]	622	1			T21	4		T22	1		T23	9
valid_sources[0x75]	901	1			T21	6		T91	1		T22	1
valid_sources[0x76]	907	1			T21	1		T23	9		T40	4
valid_sources[0x77]	834	1			T23	17		T115	1		T42	5
valid_sources[0x78]	524	1			T21	5		T22	1		T23	10
valid_sources[0x79]	574	1			T116	1		T105	1		T23	9
valid_sources[0x7a]	607	1			T25	1		T21	1		T22	3
valid_sources[0x7b]	535	1			T21	4		T23	17		T146	16
valid_sources[0x7c]	507	1			T21	1		T22	1		T23	12
valid_sources[0x7d]	449	1			T147	1		T22	1		T23	3
valid_sources[0x7e]	699	1			T21	4		T23	4		T51	1
valid_sources[0x7f]	505	1			T23	7		T115	3		T42	3
valid_sources[0x80]	617	1			T23	1		T57	1		T58	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40966

1

T1

35

T3

32

T5

21

values[0x0]

all_enables

biggest_size

55151

1

T1

35

T3

22

T6

3

values[0x1]

all_enables

biggest_size

53108

1

T1

14

T2

1

T3

15