Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15690451

1

T1

27211

T2

572

T3

24252

full_word

161314972

1

T1

237072

T2

5538

T3

141752

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	177005123	1			T1	239793		T2	6110		T3	144177
auto[TlIntgErrCmd]	103	1			T102	8		T103	6		T104	7
auto[TlIntgErrData]	98	1			T102	3		T103	2		T104	7
auto[TlIntgErrBoth]	99	1			T102	9		T103	2		T104	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85512906

1

T1

117239

T2

3090

T3

709365

auto[1]

91492517

1

T1

122554

T2

3020

T3

732410

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7682501	1			T1	11371		T2	262		T3	10946
auto[TlIntgErrNone]	partial	auto[1]	8007679	1			T1	15840		T2	310		T3	13306
auto[TlIntgErrNone]	full_word	auto[0]	77830263	1			T1	116102		T2	2828		T3	698419
auto[TlIntgErrNone]	full_word	auto[1]	83484680	1			T1	120970		T2	2710		T3	719104
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T102	3		T103	2		T104	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T102	5		T103	4		T104	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T117	1		T121	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T104	2		T118	1		T123	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T102	1		T104	3		T117	3
auto[TlIntgErrData]	partial	auto[1]	39	1			T102	1		T103	1		T104	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T102	1		T103	1		T104	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T124	1		T125	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T102	5		T103	1		T104	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T102	4		T103	1		T104	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T125	1		T123	1		T126	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T104	1		T126	1		T127	1