Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	760275	1			T3	10588		T5	25169		T11	218
auto[1]	11303504	1			T1	12961		T2	8		T3	1525
auto[2]	591277	1			T3	5899		T5	22892		T11	224
auto[3]	11037754	1			T1	9260		T2	16		T3	621

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14400003	1			T1	18553		T2	17		T3	14736
auto[1]	2230306	1			T1	1716		T2	3		T3	1937
auto[2]	2264412	1			T1	1799		T2	4		T3	1750
auto[3]	4798089	1			T1	153		T3	210		T6	88

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9525606

1

T1

22220

T2

24

T3

18632

auto[1]

14167204

1

T1

1

T3

1

T5

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	358297	1			T3	8806		T5	20825		T11	178
auto[0]	auto[0]	auto[1]	37267	1			T3	841		T5	2080		T11	20
auto[0]	auto[0]	auto[2]	37321	1			T3	867		T5	2082		T11	17
auto[0]	auto[0]	auto[3]	96761	1			T3	74		T5	182		T11	3
auto[0]	auto[1]	auto[0]	3132250	1			T1	10787		T2	7		T3	835
auto[0]	auto[1]	auto[1]	339897	1			T1	949		T3	555		T6	439
auto[0]	auto[1]	auto[2]	360905	1			T1	1132		T2	1		T3	77
auto[0]	auto[1]	auto[3]	574363	1			T1	93		T3	57		T6	43
auto[0]	auto[2]	auto[0]	272577	1			T3	4870		T5	19409		T11	193
auto[0]	auto[2]	auto[1]	34443	1			T3	514		T5	1923		T11	16
auto[0]	auto[2]	auto[2]	27297	1			T3	466		T5	1417		T11	15
auto[0]	auto[2]	auto[3]	70039	1			T3	49		T5	143		T71	260
auto[0]	auto[3]	auto[0]	2963610	1			T1	7765		T2	10		T3	224
auto[0]	auto[3]	auto[1]	339172	1			T1	767		T2	3		T3	27
auto[0]	auto[3]	auto[2]	361284	1			T1	667		T2	3		T3	340
auto[0]	auto[3]	auto[3]	520123	1			T1	60		T3	30		T6	45
auto[1]	auto[0]	auto[0]	7652	1			T98	453		T33	448		T128	1
auto[1]	auto[0]	auto[1]	34096	1			T98	1955		T33	1887		T129	1649
auto[1]	auto[0]	auto[2]	34311	1			T98	2052		T33	1874		T129	1647
auto[1]	auto[0]	auto[3]	154570	1			T53	3		T77	4		T98	9146
auto[1]	auto[1]	auto[0]	3831197	1			T3	1		T5	1		T9	1
auto[1]	auto[1]	auto[1]	711074	1			T86	7788		T95	6325		T50	6348
auto[1]	auto[1]	auto[2]	710915	1			T86	8074		T95	6870		T50	7058
auto[1]	auto[1]	auto[3]	1642903	1			T86	773		T21	1		T95	658
auto[1]	auto[2]	auto[0]	6329	1			T98	257		T33	237		T129	335
auto[1]	auto[2]	auto[1]	28466	1			T98	1170		T33	1138		T130	1
auto[1]	auto[2]	auto[2]	27723	1			T98	1920		T33	1864		T129	1335
auto[1]	auto[2]	auto[3]	124403	1			T53	1		T98	8738		T33	8177
auto[1]	auto[3]	auto[0]	3828091	1			T1	1		T86	79953		T21	1
auto[1]	auto[3]	auto[1]	705891	1			T86	7955		T95	6831		T50	6969
auto[1]	auto[3]	auto[2]	704656	1			T86	7944		T95	6248		T50	6275
auto[1]	auto[3]	auto[3]	1614927	1			T86	769		T95	614		T50	624