Module Definition
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Module : prim_lc_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_lc_sync 100.00 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync 100.00 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.39 100.00 94.62 100.00 100.00 92.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
89.00 100.00 100.00 100.00 95.00 50.00 u_tlul_lc_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.39 100.00 94.62 100.00 100.00 92.31 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 2700 2700 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.OutputDelay_A 2147483647 2147483647 0 5400
gen_no_flops.OutputDelay_A 1111644246 1111518189 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2700 2700 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T7 3 3 0 0
T8 3 3 0 0
T9 3 3 0 0
T10 3 3 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 2213529 2212527 0 0
T2 240282 240078 0 0
T3 513780 513762 0 0
T4 310287 310269 0 0
T5 544293 544239 0 0
T6 1097913 1097730 0 0
T7 3414 3255 0 0
T8 100809 100569 0 0
T9 122484 122271 0 0
T10 209976 209817 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 5400
T1 1475686 1474980 0 6
T2 160188 160046 0 6
T3 342520 342504 0 6
T4 206858 206846 0 6
T5 362862 362822 0 6
T6 731942 731814 0 6
T7 2276 2164 0 6
T8 67206 67040 0 6
T9 81656 81508 0 6
T10 139984 139872 0 6

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1111644246 1111518189 0 0
T1 737843 737509 0 0
T2 80094 80026 0 0
T3 171260 171254 0 0
T4 103429 103423 0 0
T5 181431 181413 0 0
T6 365971 365910 0 0
T7 1138 1085 0 0
T8 33603 33523 0 0
T9 40828 40757 0 0
T10 69992 69939 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 900 900 0 0
OutputsKnown_A 1111644246 1111518189 0 0
gen_flops.OutputDelay_A 1111644246 1111505280 0 2700


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1111644246 1111518189 0 0
T1 737843 737509 0 0
T2 80094 80026 0 0
T3 171260 171254 0 0
T4 103429 103423 0 0
T5 181431 181413 0 0
T6 365971 365910 0 0
T7 1138 1085 0 0
T8 33603 33523 0 0
T9 40828 40757 0 0
T10 69992 69939 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1111644246 1111505280 0 2700
T1 737843 737490 0 3
T2 80094 80023 0 3
T3 171260 171252 0 3
T4 103429 103423 0 3
T5 181431 181411 0 3
T6 365971 365907 0 3
T7 1138 1082 0 3
T8 33603 33520 0 3
T9 40828 40754 0 3
T10 69992 69936 0 3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 900 900 0 0
OutputsKnown_A 1111644246 1111518189 0 0
gen_no_flops.OutputDelay_A 1111644246 1111518189 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1111644246 1111518189 0 0
T1 737843 737509 0 0
T2 80094 80026 0 0
T3 171260 171254 0 0
T4 103429 103423 0 0
T5 181431 181413 0 0
T6 365971 365910 0 0
T7 1138 1085 0 0
T8 33603 33523 0 0
T9 40828 40757 0 0
T10 69992 69939 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1111644246 1111518189 0 0
T1 737843 737509 0 0
T2 80094 80026 0 0
T3 171260 171254 0 0
T4 103429 103423 0 0
T5 181431 181413 0 0
T6 365971 365910 0 0
T7 1138 1085 0 0
T8 33603 33523 0 0
T9 40828 40757 0 0
T10 69992 69939 0 0

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 900 900 0 0
OutputsKnown_A 1111644246 1111518189 0 0
gen_flops.OutputDelay_A 1111644246 1111505280 0 2700


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1111644246 1111518189 0 0
T1 737843 737509 0 0
T2 80094 80026 0 0
T3 171260 171254 0 0
T4 103429 103423 0 0
T5 181431 181413 0 0
T6 365971 365910 0 0
T7 1138 1085 0 0
T8 33603 33523 0 0
T9 40828 40757 0 0
T10 69992 69939 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1111644246 1111505280 0 2700
T1 737843 737490 0 3
T2 80094 80023 0 3
T3 171260 171252 0 3
T4 103429 103423 0 3
T5 181431 181411 0 3
T6 365971 365907 0 3
T7 1138 1082 0 3
T8 33603 33520 0 3
T9 40828 40754 0 3
T10 69992 69936 0 3

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