Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1123691823	140504	0	0
ctrl_regwen_rd_A	1123691823	5700	0	0
exec_rd_A	1123691823	5190	0	0
exec_regwen_rd_A	1123691823	5694	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123691823	140504	0	0
T22	22075	654	0	0
T23	88723	2375	0	0
T24	0	2983	0	0
T40	320812	0	0	0
T42	0	861	0	0
T43	0	4110	0	0
T44	0	4323	0	0
T45	0	1257	0	0
T46	0	1022	0	0
T47	0	3483	0	0
T48	0	1176	0	0
T49	94822	0	0	0
T50	436800	0	0	0
T51	117400	0	0	0
T52	67095	0	0	0
T53	489454	0	0	0
T54	234247	0	0	0
T55	206576	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123691823	5700	0	0
T22	22075	120	0	0
T23	88723	0	0	0
T40	320812	0	0	0
T46	0	272	0	0
T49	94822	0	0	0
T50	436800	0	0	0
T51	117400	0	0	0
T52	67095	0	0	0
T53	489454	0	0	0
T54	234247	0	0	0
T55	206576	0	0	0
T107	0	187	0	0
T108	0	266	0	0
T109	0	156	0	0
T110	0	944	0	0
T111	0	467	0	0
T112	0	80	0	0
T113	0	78	0	0
T114	0	233	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123691823	5190	0	0
T22	22075	90	0	0
T23	88723	0	0	0
T40	320812	0	0	0
T46	0	232	0	0
T49	94822	0	0	0
T50	436800	0	0	0
T51	117400	0	0	0
T52	67095	0	0	0
T53	489454	0	0	0
T54	234247	0	0	0
T55	206576	0	0	0
T107	0	162	0	0
T108	0	240	0	0
T109	0	129	0	0
T110	0	842	0	0
T111	0	364	0	0
T112	0	90	0	0
T113	0	113	0	0
T114	0	233	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123691823	5694	0	0
T22	22075	53	0	0
T23	88723	0	0	0
T40	320812	0	0	0
T46	0	269	0	0
T49	94822	0	0	0
T50	436800	0	0	0
T51	117400	0	0	0
T52	67095	0	0	0
T53	489454	0	0	0
T54	234247	0	0	0
T55	206576	0	0	0
T107	0	170	0	0
T108	0	258	0	0
T109	0	146	0	0
T110	0	1112	0	0
T111	0	429	0	0
T112	0	46	0	0
T113	0	124	0	0
T114	0	224	0	0