| T791 |
/workspace/coverage/default/16.sram_ctrl_regwen.3407304372 |
|
|
May 07 12:47:44 PM PDT 24 |
May 07 01:09:41 PM PDT 24 |
27577300074 ps |
| T792 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.4130046049 |
|
|
May 07 12:47:12 PM PDT 24 |
May 07 12:49:43 PM PDT 24 |
4431742053 ps |
| T793 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3085009959 |
|
|
May 07 12:49:39 PM PDT 24 |
May 07 12:50:13 PM PDT 24 |
1801994129 ps |
| T794 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.979474565 |
|
|
May 07 12:51:18 PM PDT 24 |
May 07 12:52:21 PM PDT 24 |
965008407 ps |
| T795 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.4048986114 |
|
|
May 07 12:47:25 PM PDT 24 |
May 07 12:53:29 PM PDT 24 |
50972346502 ps |
| T796 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.4162704803 |
|
|
May 07 12:47:24 PM PDT 24 |
May 07 12:50:06 PM PDT 24 |
19523804711 ps |
| T797 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.1028974565 |
|
|
May 07 12:48:33 PM PDT 24 |
May 07 12:53:39 PM PDT 24 |
30861015042 ps |
| T798 |
/workspace/coverage/default/39.sram_ctrl_alert_test.2913327379 |
|
|
May 07 12:50:26 PM PDT 24 |
May 07 12:50:28 PM PDT 24 |
17845339 ps |
| T799 |
/workspace/coverage/default/12.sram_ctrl_partial_access.615901474 |
|
|
May 07 12:47:37 PM PDT 24 |
May 07 12:47:50 PM PDT 24 |
4949198105 ps |
| T800 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2310685302 |
|
|
May 07 12:47:33 PM PDT 24 |
May 07 12:47:38 PM PDT 24 |
723621824 ps |
| T801 |
/workspace/coverage/default/31.sram_ctrl_stress_all.590255326 |
|
|
May 07 12:49:31 PM PDT 24 |
May 07 01:40:20 PM PDT 24 |
111013065268 ps |
| T802 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1542968940 |
|
|
May 07 12:49:12 PM PDT 24 |
May 07 12:49:22 PM PDT 24 |
694521545 ps |
| T803 |
/workspace/coverage/default/9.sram_ctrl_executable.3035024626 |
|
|
May 07 12:47:16 PM PDT 24 |
May 07 12:56:42 PM PDT 24 |
6110086367 ps |
| T804 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3258985168 |
|
|
May 07 12:51:34 PM PDT 24 |
May 07 12:52:13 PM PDT 24 |
16695514477 ps |
| T805 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2069386520 |
|
|
May 07 12:50:07 PM PDT 24 |
May 07 12:50:24 PM PDT 24 |
3001030893 ps |
| T806 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.199168870 |
|
|
May 07 12:48:25 PM PDT 24 |
May 07 01:11:10 PM PDT 24 |
39324328944 ps |
| T807 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1725351954 |
|
|
May 07 12:46:46 PM PDT 24 |
May 07 12:46:48 PM PDT 24 |
11677217 ps |
| T808 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.747824861 |
|
|
May 07 12:47:32 PM PDT 24 |
May 07 12:48:48 PM PDT 24 |
3072429614 ps |
| T809 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.3859014218 |
|
|
May 07 12:50:37 PM PDT 24 |
May 07 12:50:41 PM PDT 24 |
1356421831 ps |
| T810 |
/workspace/coverage/default/31.sram_ctrl_bijection.3761093031 |
|
|
May 07 12:49:19 PM PDT 24 |
May 07 01:05:23 PM PDT 24 |
59064463827 ps |
| T811 |
/workspace/coverage/default/30.sram_ctrl_stress_all.162090181 |
|
|
May 07 12:49:18 PM PDT 24 |
May 07 02:15:16 PM PDT 24 |
54724547101 ps |
| T812 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3983294627 |
|
|
May 07 12:49:50 PM PDT 24 |
May 07 12:50:16 PM PDT 24 |
1546860948 ps |
| T813 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3061456443 |
|
|
May 07 12:51:04 PM PDT 24 |
May 07 12:52:01 PM PDT 24 |
757421020 ps |
| T814 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2996517945 |
|
|
May 07 12:50:57 PM PDT 24 |
May 07 12:51:34 PM PDT 24 |
2170137413 ps |
| T815 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.562026768 |
|
|
May 07 12:48:28 PM PDT 24 |
May 07 12:49:52 PM PDT 24 |
1625979374 ps |
| T816 |
/workspace/coverage/default/42.sram_ctrl_alert_test.2608991213 |
|
|
May 07 12:50:48 PM PDT 24 |
May 07 12:50:49 PM PDT 24 |
12865183 ps |
| T817 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1106223285 |
|
|
May 07 12:49:58 PM PDT 24 |
May 07 12:50:03 PM PDT 24 |
429290112 ps |
| T818 |
/workspace/coverage/default/32.sram_ctrl_partial_access.2053469410 |
|
|
May 07 12:49:32 PM PDT 24 |
May 07 12:50:56 PM PDT 24 |
3068159794 ps |
| T819 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3858401664 |
|
|
May 07 12:49:59 PM PDT 24 |
May 07 12:54:17 PM PDT 24 |
62960953196 ps |
| T820 |
/workspace/coverage/default/3.sram_ctrl_regwen.1133063351 |
|
|
May 07 12:46:58 PM PDT 24 |
May 07 01:01:13 PM PDT 24 |
11831190904 ps |
| T821 |
/workspace/coverage/default/36.sram_ctrl_partial_access.2944632501 |
|
|
May 07 12:50:01 PM PDT 24 |
May 07 12:50:09 PM PDT 24 |
2180513360 ps |
| T822 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1315913257 |
|
|
May 07 12:46:53 PM PDT 24 |
May 07 12:55:03 PM PDT 24 |
44677071277 ps |
| T823 |
/workspace/coverage/default/18.sram_ctrl_stress_all.1658175436 |
|
|
May 07 12:47:57 PM PDT 24 |
May 07 01:57:55 PM PDT 24 |
54170683873 ps |
| T824 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1345377280 |
|
|
May 07 12:49:48 PM PDT 24 |
May 07 12:51:00 PM PDT 24 |
23054175297 ps |
| T825 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3663366907 |
|
|
May 07 12:47:25 PM PDT 24 |
May 07 12:52:17 PM PDT 24 |
19899552636 ps |
| T826 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1274524284 |
|
|
May 07 12:46:54 PM PDT 24 |
May 07 12:46:59 PM PDT 24 |
363236770 ps |
| T827 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3474163429 |
|
|
May 07 12:49:52 PM PDT 24 |
May 07 12:54:01 PM PDT 24 |
4092197332 ps |
| T828 |
/workspace/coverage/default/19.sram_ctrl_stress_all.109529461 |
|
|
May 07 12:48:05 PM PDT 24 |
May 07 02:15:57 PM PDT 24 |
218575564506 ps |
| T829 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.4289501592 |
|
|
May 07 12:48:19 PM PDT 24 |
May 07 12:50:41 PM PDT 24 |
6603565391 ps |
| T80 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.4031150408 |
|
|
May 07 12:48:03 PM PDT 24 |
May 07 12:48:59 PM PDT 24 |
1014458324 ps |
| T830 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.694449847 |
|
|
May 07 12:47:19 PM PDT 24 |
May 07 12:48:01 PM PDT 24 |
25748466028 ps |
| T831 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.3661357614 |
|
|
May 07 12:48:59 PM PDT 24 |
May 07 12:49:51 PM PDT 24 |
7905796861 ps |
| T832 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2036814502 |
|
|
May 07 12:49:19 PM PDT 24 |
May 07 12:51:07 PM PDT 24 |
1509988146 ps |
| T833 |
/workspace/coverage/default/46.sram_ctrl_executable.4005249454 |
|
|
May 07 12:51:10 PM PDT 24 |
May 07 12:53:08 PM PDT 24 |
6169704410 ps |
| T834 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1762139891 |
|
|
May 07 12:48:18 PM PDT 24 |
May 07 12:53:40 PM PDT 24 |
29354714148 ps |
| T835 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.1110335189 |
|
|
May 07 12:47:59 PM PDT 24 |
May 07 12:50:31 PM PDT 24 |
13390803148 ps |
| T836 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.4024069747 |
|
|
May 07 12:47:51 PM PDT 24 |
May 07 12:57:01 PM PDT 24 |
64113970137 ps |
| T837 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.3205290688 |
|
|
May 07 12:50:31 PM PDT 24 |
May 07 12:55:14 PM PDT 24 |
13769220745 ps |
| T838 |
/workspace/coverage/default/49.sram_ctrl_alert_test.315867350 |
|
|
May 07 12:51:33 PM PDT 24 |
May 07 12:51:35 PM PDT 24 |
41906891 ps |
| T839 |
/workspace/coverage/default/40.sram_ctrl_regwen.3126639244 |
|
|
May 07 12:50:24 PM PDT 24 |
May 07 01:13:55 PM PDT 24 |
17646532487 ps |
| T840 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1974977632 |
|
|
May 07 12:46:58 PM PDT 24 |
May 07 12:47:17 PM PDT 24 |
3070253579 ps |
| T841 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3476305820 |
|
|
May 07 12:47:12 PM PDT 24 |
May 07 12:47:22 PM PDT 24 |
1076788566 ps |
| T842 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3344267873 |
|
|
May 07 12:49:52 PM PDT 24 |
May 07 12:50:05 PM PDT 24 |
6783785966 ps |
| T843 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1142630483 |
|
|
May 07 12:49:53 PM PDT 24 |
May 07 03:13:36 PM PDT 24 |
440180864649 ps |
| T844 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1686961275 |
|
|
May 07 12:48:00 PM PDT 24 |
May 07 12:48:32 PM PDT 24 |
1403798562 ps |
| T845 |
/workspace/coverage/default/49.sram_ctrl_regwen.4254664183 |
|
|
May 07 12:51:35 PM PDT 24 |
May 07 12:59:40 PM PDT 24 |
8058671110 ps |
| T846 |
/workspace/coverage/default/22.sram_ctrl_stress_all.4180852159 |
|
|
May 07 12:48:25 PM PDT 24 |
May 07 02:33:49 PM PDT 24 |
274142549798 ps |
| T847 |
/workspace/coverage/default/37.sram_ctrl_smoke.22267642 |
|
|
May 07 12:50:09 PM PDT 24 |
May 07 12:50:18 PM PDT 24 |
752022998 ps |
| T848 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.387665835 |
|
|
May 07 12:48:40 PM PDT 24 |
May 07 12:49:50 PM PDT 24 |
3797781737 ps |
| T849 |
/workspace/coverage/default/5.sram_ctrl_executable.3147695909 |
|
|
May 07 12:47:04 PM PDT 24 |
May 07 01:07:32 PM PDT 24 |
37275047641 ps |
| T850 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3799795165 |
|
|
May 07 12:47:27 PM PDT 24 |
May 07 12:47:34 PM PDT 24 |
2788097964 ps |
| T851 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3984288174 |
|
|
May 07 12:51:03 PM PDT 24 |
May 07 12:54:52 PM PDT 24 |
23488066482 ps |
| T852 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.1302846344 |
|
|
May 07 12:49:46 PM PDT 24 |
May 07 12:52:20 PM PDT 24 |
29969405976 ps |
| T853 |
/workspace/coverage/default/26.sram_ctrl_partial_access.132495246 |
|
|
May 07 12:48:44 PM PDT 24 |
May 07 12:49:06 PM PDT 24 |
1220866062 ps |
| T854 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.224678859 |
|
|
May 07 12:51:04 PM PDT 24 |
May 07 12:53:36 PM PDT 24 |
21107500254 ps |
| T855 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.715094631 |
|
|
May 07 12:48:21 PM PDT 24 |
May 07 12:53:28 PM PDT 24 |
10154487853 ps |
| T856 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.1165826972 |
|
|
May 07 12:47:57 PM PDT 24 |
May 07 12:48:01 PM PDT 24 |
358330232 ps |
| T857 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.1997787936 |
|
|
May 07 12:50:04 PM PDT 24 |
May 07 12:51:19 PM PDT 24 |
46764769428 ps |
| T858 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.326718276 |
|
|
May 07 12:48:47 PM PDT 24 |
May 07 12:51:58 PM PDT 24 |
17312852217 ps |
| T859 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2404826962 |
|
|
May 07 12:47:53 PM PDT 24 |
May 07 01:07:51 PM PDT 24 |
33831340503 ps |
| T860 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.2420816936 |
|
|
May 07 12:50:57 PM PDT 24 |
May 07 12:55:25 PM PDT 24 |
14474465279 ps |
| T861 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1386933545 |
|
|
May 07 12:47:27 PM PDT 24 |
May 07 12:58:24 PM PDT 24 |
14827796052 ps |
| T862 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.1340486595 |
|
|
May 07 12:49:08 PM PDT 24 |
May 07 12:57:23 PM PDT 24 |
61737824713 ps |
| T863 |
/workspace/coverage/default/45.sram_ctrl_smoke.3206041932 |
|
|
May 07 12:50:56 PM PDT 24 |
May 07 12:51:23 PM PDT 24 |
1596758523 ps |
| T864 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1166052611 |
|
|
May 07 12:49:59 PM PDT 24 |
May 07 12:55:05 PM PDT 24 |
9883742244 ps |
| T865 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2621280954 |
|
|
May 07 12:51:05 PM PDT 24 |
May 07 12:51:13 PM PDT 24 |
693466190 ps |
| T866 |
/workspace/coverage/default/37.sram_ctrl_executable.812631763 |
|
|
May 07 12:50:08 PM PDT 24 |
May 07 01:02:05 PM PDT 24 |
13295402218 ps |
| T867 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3649667922 |
|
|
May 07 12:47:19 PM PDT 24 |
May 07 12:47:24 PM PDT 24 |
691689269 ps |
| T868 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1925595356 |
|
|
May 07 12:49:12 PM PDT 24 |
May 07 12:51:11 PM PDT 24 |
1654299900 ps |
| T869 |
/workspace/coverage/default/3.sram_ctrl_bijection.1669236019 |
|
|
May 07 12:46:55 PM PDT 24 |
May 07 12:59:10 PM PDT 24 |
240567140177 ps |
| T870 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.4090356810 |
|
|
May 07 12:49:08 PM PDT 24 |
May 07 12:56:20 PM PDT 24 |
18979061446 ps |
| T871 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1450299884 |
|
|
May 07 12:50:58 PM PDT 24 |
May 07 12:56:31 PM PDT 24 |
23398757962 ps |
| T872 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.48159008 |
|
|
May 07 12:46:50 PM PDT 24 |
May 07 12:47:56 PM PDT 24 |
3105677782 ps |
| T873 |
/workspace/coverage/default/22.sram_ctrl_alert_test.3896753475 |
|
|
May 07 12:48:24 PM PDT 24 |
May 07 12:48:25 PM PDT 24 |
12617619 ps |
| T874 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4159589158 |
|
|
May 07 12:47:23 PM PDT 24 |
May 07 12:50:37 PM PDT 24 |
17099689140 ps |
| T875 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2406623081 |
|
|
May 07 12:49:21 PM PDT 24 |
May 07 12:51:35 PM PDT 24 |
1573688843 ps |
| T876 |
/workspace/coverage/default/3.sram_ctrl_executable.3794515520 |
|
|
May 07 12:46:59 PM PDT 24 |
May 07 12:58:12 PM PDT 24 |
38006208027 ps |
| T877 |
/workspace/coverage/default/9.sram_ctrl_regwen.2991314958 |
|
|
May 07 12:47:16 PM PDT 24 |
May 07 01:04:57 PM PDT 24 |
59957628218 ps |
| T878 |
/workspace/coverage/default/32.sram_ctrl_smoke.3401470660 |
|
|
May 07 12:49:25 PM PDT 24 |
May 07 12:50:04 PM PDT 24 |
12548283833 ps |
| T879 |
/workspace/coverage/default/20.sram_ctrl_smoke.2911923030 |
|
|
May 07 12:48:03 PM PDT 24 |
May 07 12:50:20 PM PDT 24 |
3088143528 ps |
| T880 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3636307081 |
|
|
May 07 12:49:56 PM PDT 24 |
May 07 12:51:20 PM PDT 24 |
46459331348 ps |
| T881 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.8553548 |
|
|
May 07 12:51:20 PM PDT 24 |
May 07 12:53:19 PM PDT 24 |
2628988237 ps |
| T882 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.2506167304 |
|
|
May 07 12:51:09 PM PDT 24 |
May 07 12:51:24 PM PDT 24 |
698801551 ps |
| T883 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2193883675 |
|
|
May 07 12:49:11 PM PDT 24 |
May 07 12:49:19 PM PDT 24 |
2916528663 ps |
| T884 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1402759477 |
|
|
May 07 12:50:09 PM PDT 24 |
May 07 12:50:14 PM PDT 24 |
4195884104 ps |
| T885 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2924293226 |
|
|
May 07 12:47:06 PM PDT 24 |
May 07 12:52:45 PM PDT 24 |
52506492722 ps |
| T886 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2056752309 |
|
|
May 07 12:49:13 PM PDT 24 |
May 07 01:11:01 PM PDT 24 |
35047714445 ps |
| T887 |
/workspace/coverage/default/44.sram_ctrl_partial_access.858252747 |
|
|
May 07 12:50:59 PM PDT 24 |
May 07 12:51:15 PM PDT 24 |
3557196091 ps |
| T888 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3403442817 |
|
|
May 07 12:50:19 PM PDT 24 |
May 07 01:07:38 PM PDT 24 |
16761978612 ps |
| T889 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.4257447883 |
|
|
May 07 12:51:09 PM PDT 24 |
May 07 12:56:15 PM PDT 24 |
153746040774 ps |
| T890 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1238428827 |
|
|
May 07 12:51:02 PM PDT 24 |
May 07 12:52:07 PM PDT 24 |
4125571005 ps |
| T891 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.22689487 |
|
|
May 07 12:51:33 PM PDT 24 |
May 07 12:52:48 PM PDT 24 |
5302022424 ps |
| T892 |
/workspace/coverage/default/48.sram_ctrl_regwen.3612202293 |
|
|
May 07 12:51:29 PM PDT 24 |
May 07 01:07:12 PM PDT 24 |
11289689535 ps |
| T893 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2169751910 |
|
|
May 07 12:46:54 PM PDT 24 |
May 07 12:48:59 PM PDT 24 |
2123131586 ps |
| T894 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1105823131 |
|
|
May 07 12:49:18 PM PDT 24 |
May 07 12:51:54 PM PDT 24 |
2867106596 ps |
| T895 |
/workspace/coverage/default/38.sram_ctrl_regwen.1374736085 |
|
|
May 07 12:50:11 PM PDT 24 |
May 07 01:14:22 PM PDT 24 |
20508247417 ps |
| T896 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.66536866 |
|
|
May 07 12:50:38 PM PDT 24 |
May 07 12:52:43 PM PDT 24 |
1602332473 ps |
| T897 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3970388056 |
|
|
May 07 12:47:07 PM PDT 24 |
May 07 12:48:16 PM PDT 24 |
37464635421 ps |
| T898 |
/workspace/coverage/default/30.sram_ctrl_alert_test.4101159326 |
|
|
May 07 12:49:23 PM PDT 24 |
May 07 12:49:24 PM PDT 24 |
42144306 ps |
| T899 |
/workspace/coverage/default/2.sram_ctrl_stress_all.2174006439 |
|
|
May 07 12:46:55 PM PDT 24 |
May 07 01:37:15 PM PDT 24 |
142605234139 ps |
| T900 |
/workspace/coverage/default/0.sram_ctrl_partial_access.986362139 |
|
|
May 07 12:46:46 PM PDT 24 |
May 07 12:47:03 PM PDT 24 |
4388886604 ps |
| T901 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.887730837 |
|
|
May 07 12:51:33 PM PDT 24 |
May 07 12:56:11 PM PDT 24 |
14490699014 ps |
| T902 |
/workspace/coverage/default/41.sram_ctrl_stress_all.1130561113 |
|
|
May 07 12:50:38 PM PDT 24 |
May 07 01:24:04 PM PDT 24 |
125382895634 ps |
| T903 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3773155648 |
|
|
May 07 12:48:22 PM PDT 24 |
May 07 12:49:00 PM PDT 24 |
3086567415 ps |
| T904 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1434513863 |
|
|
May 07 12:47:50 PM PDT 24 |
May 07 12:48:19 PM PDT 24 |
1490378202 ps |
| T905 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3420257154 |
|
|
May 07 12:50:13 PM PDT 24 |
May 07 01:06:29 PM PDT 24 |
19463854032 ps |
| T906 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4178545402 |
|
|
May 07 12:50:45 PM PDT 24 |
May 07 12:51:43 PM PDT 24 |
4388541140 ps |
| T907 |
/workspace/coverage/default/0.sram_ctrl_regwen.824271130 |
|
|
May 07 12:46:59 PM PDT 24 |
May 07 01:05:55 PM PDT 24 |
50967511368 ps |
| T908 |
/workspace/coverage/default/20.sram_ctrl_regwen.3676007053 |
|
|
May 07 12:48:10 PM PDT 24 |
May 07 12:50:10 PM PDT 24 |
17629689131 ps |
| T909 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.572359123 |
|
|
May 07 12:50:05 PM PDT 24 |
May 07 01:03:45 PM PDT 24 |
21373698817 ps |
| T910 |
/workspace/coverage/default/38.sram_ctrl_bijection.351962569 |
|
|
May 07 12:50:12 PM PDT 24 |
May 07 01:25:16 PM PDT 24 |
31808267392 ps |
| T911 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2846301763 |
|
|
May 07 12:47:05 PM PDT 24 |
May 07 12:48:24 PM PDT 24 |
9736227637 ps |
| T912 |
/workspace/coverage/default/23.sram_ctrl_partial_access.2180533937 |
|
|
May 07 12:48:25 PM PDT 24 |
May 07 12:50:33 PM PDT 24 |
5026737911 ps |
| T913 |
/workspace/coverage/default/18.sram_ctrl_alert_test.33009770 |
|
|
May 07 12:48:06 PM PDT 24 |
May 07 12:48:07 PM PDT 24 |
50666576 ps |
| T914 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.1115315906 |
|
|
May 07 12:48:05 PM PDT 24 |
May 07 12:49:27 PM PDT 24 |
52446051017 ps |
| T915 |
/workspace/coverage/default/27.sram_ctrl_partial_access.2646103671 |
|
|
May 07 12:48:52 PM PDT 24 |
May 07 12:50:35 PM PDT 24 |
1807291310 ps |
| T916 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.239881818 |
|
|
May 07 12:48:25 PM PDT 24 |
May 07 12:51:17 PM PDT 24 |
6777087149 ps |
| T917 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.538055318 |
|
|
May 07 12:49:05 PM PDT 24 |
May 07 12:54:57 PM PDT 24 |
65757561764 ps |
| T918 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.696127132 |
|
|
May 07 12:46:57 PM PDT 24 |
May 07 12:47:36 PM PDT 24 |
6269620454 ps |
| T919 |
/workspace/coverage/default/47.sram_ctrl_regwen.2055054375 |
|
|
May 07 12:51:20 PM PDT 24 |
May 07 01:03:39 PM PDT 24 |
38120992609 ps |
| T920 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3048577183 |
|
|
May 07 12:49:00 PM PDT 24 |
May 07 01:14:56 PM PDT 24 |
52787149134 ps |
| T921 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3101285855 |
|
|
May 07 12:48:05 PM PDT 24 |
May 07 12:51:51 PM PDT 24 |
13269062408 ps |
| T922 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.370342871 |
|
|
May 07 12:50:27 PM PDT 24 |
May 07 12:53:01 PM PDT 24 |
17901983038 ps |
| T923 |
/workspace/coverage/default/8.sram_ctrl_regwen.966783231 |
|
|
May 07 12:47:25 PM PDT 24 |
May 07 01:13:54 PM PDT 24 |
20860587681 ps |
| T924 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3199962712 |
|
|
May 07 12:50:23 PM PDT 24 |
May 07 12:54:51 PM PDT 24 |
4282385050 ps |
| T925 |
/workspace/coverage/default/29.sram_ctrl_alert_test.601555913 |
|
|
May 07 12:49:12 PM PDT 24 |
May 07 12:49:13 PM PDT 24 |
23143912 ps |
| T926 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2548986658 |
|
|
May 07 12:47:13 PM PDT 24 |
May 07 12:47:37 PM PDT 24 |
1409684859 ps |
| T927 |
/workspace/coverage/default/31.sram_ctrl_regwen.2129575233 |
|
|
May 07 12:49:27 PM PDT 24 |
May 07 01:01:22 PM PDT 24 |
9853233146 ps |
| T928 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.938781400 |
|
|
May 07 12:47:44 PM PDT 24 |
May 07 12:52:28 PM PDT 24 |
13902936082 ps |
| T929 |
/workspace/coverage/default/21.sram_ctrl_smoke.2997498054 |
|
|
May 07 12:48:10 PM PDT 24 |
May 07 12:50:33 PM PDT 24 |
965383808 ps |
| T930 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3269578743 |
|
|
May 07 12:47:25 PM PDT 24 |
May 07 12:51:19 PM PDT 24 |
11993059017 ps |
| T931 |
/workspace/coverage/default/29.sram_ctrl_stress_all.2537972043 |
|
|
May 07 12:49:11 PM PDT 24 |
May 07 01:21:03 PM PDT 24 |
81182470991 ps |
| T932 |
/workspace/coverage/default/18.sram_ctrl_executable.94693727 |
|
|
May 07 12:47:59 PM PDT 24 |
May 07 12:53:54 PM PDT 24 |
5624210391 ps |
| T933 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.4183873503 |
|
|
May 07 12:48:25 PM PDT 24 |
May 07 12:49:34 PM PDT 24 |
49811160744 ps |
| T934 |
/workspace/coverage/default/40.sram_ctrl_bijection.1610173366 |
|
|
May 07 12:50:24 PM PDT 24 |
May 07 01:36:06 PM PDT 24 |
298914966479 ps |
| T935 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.470231187 |
|
|
May 07 12:47:15 PM PDT 24 |
May 07 01:04:00 PM PDT 24 |
15128228090 ps |
| T936 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1164426144 |
|
|
May 07 12:47:44 PM PDT 24 |
May 07 01:08:46 PM PDT 24 |
27662963003 ps |
| T937 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.819758087 |
|
|
May 07 12:48:40 PM PDT 24 |
May 07 12:50:39 PM PDT 24 |
1624006665 ps |
| T938 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3469264954 |
|
|
May 07 12:47:43 PM PDT 24 |
May 07 12:47:52 PM PDT 24 |
4506657242 ps |
| T939 |
/workspace/coverage/default/45.sram_ctrl_bijection.3580401705 |
|
|
May 07 12:51:04 PM PDT 24 |
May 07 01:24:11 PM PDT 24 |
416922940831 ps |
| T92 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1252852820 |
|
|
May 07 01:26:06 PM PDT 24 |
May 07 01:26:08 PM PDT 24 |
14246638 ps |
| T60 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3090323318 |
|
|
May 07 01:25:57 PM PDT 24 |
May 07 01:26:47 PM PDT 24 |
7442963866 ps |
| T102 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1719894618 |
|
|
May 07 01:25:49 PM PDT 24 |
May 07 01:25:54 PM PDT 24 |
449420519 ps |
| T940 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4180091926 |
|
|
May 07 01:25:57 PM PDT 24 |
May 07 01:26:03 PM PDT 24 |
89521194 ps |
| T61 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1481642151 |
|
|
May 07 01:26:16 PM PDT 24 |
May 07 01:27:13 PM PDT 24 |
28192930612 ps |
| T62 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.50303502 |
|
|
May 07 01:25:56 PM PDT 24 |
May 07 01:26:48 PM PDT 24 |
7128047022 ps |
| T63 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1165291607 |
|
|
May 07 01:25:44 PM PDT 24 |
May 07 01:26:12 PM PDT 24 |
3844081824 ps |
| T99 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4150569023 |
|
|
May 07 01:26:03 PM PDT 24 |
May 07 01:26:05 PM PDT 24 |
18622167 ps |
| T93 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3901832201 |
|
|
May 07 01:26:03 PM PDT 24 |
May 07 01:26:05 PM PDT 24 |
23619703 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1709724405 |
|
|
May 07 01:25:53 PM PDT 24 |
May 07 01:25:56 PM PDT 24 |
85003277 ps |
| T100 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.403401266 |
|
|
May 07 01:25:49 PM PDT 24 |
May 07 01:25:52 PM PDT 24 |
16176619 ps |
| T103 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2281435357 |
|
|
May 07 01:25:56 PM PDT 24 |
May 07 01:25:59 PM PDT 24 |
117379004 ps |
| T941 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.405371972 |
|
|
May 07 01:25:49 PM PDT 24 |
May 07 01:25:53 PM PDT 24 |
81484436 ps |
| T101 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3435900400 |
|
|
May 07 01:26:03 PM PDT 24 |
May 07 01:26:05 PM PDT 24 |
28130069 ps |
| T65 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2589214981 |
|
|
May 07 01:26:12 PM PDT 24 |
May 07 01:26:42 PM PDT 24 |
12289399820 ps |
| T942 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3414764606 |
|
|
May 07 01:25:51 PM PDT 24 |
May 07 01:25:54 PM PDT 24 |
17104930 ps |
| T94 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.574833407 |
|
|
May 07 01:26:15 PM PDT 24 |
May 07 01:26:17 PM PDT 24 |
84872275 ps |
| T66 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1682871703 |
|
|
May 07 01:25:50 PM PDT 24 |
May 07 01:25:53 PM PDT 24 |
37613411 ps |
| T67 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1951567487 |
|
|
May 07 01:26:11 PM PDT 24 |
May 07 01:27:03 PM PDT 24 |
16017661420 ps |
| T104 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.862223345 |
|
|
May 07 01:25:50 PM PDT 24 |
May 07 01:25:54 PM PDT 24 |
1013867610 ps |
| T68 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4272419900 |
|
|
May 07 01:25:50 PM PDT 24 |
May 07 01:25:53 PM PDT 24 |
14623024 ps |
| T943 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.386674 |
|
|
May 07 01:25:58 PM PDT 24 |
May 07 01:26:03 PM PDT 24 |
358564272 ps |
| T944 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1980035090 |
|
|
May 07 01:26:18 PM PDT 24 |
May 07 01:26:23 PM PDT 24 |
362359202 ps |
| T945 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4111784618 |
|
|
May 07 01:25:45 PM PDT 24 |
May 07 01:26:44 PM PDT 24 |
26094276556 ps |
| T69 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1179840324 |
|
|
May 07 01:26:00 PM PDT 24 |
May 07 01:26:01 PM PDT 24 |
45335700 ps |
| T946 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3297223196 |
|
|
May 07 01:25:52 PM PDT 24 |
May 07 01:25:54 PM PDT 24 |
42373586 ps |
| T947 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1555167086 |
|
|
May 07 01:25:56 PM PDT 24 |
May 07 01:26:00 PM PDT 24 |
26410116 ps |
| T948 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.965994347 |
|
|
May 07 01:26:04 PM PDT 24 |
May 07 01:26:09 PM PDT 24 |
3430407020 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2022674636 |
|
|
May 07 01:25:53 PM PDT 24 |
May 07 01:25:56 PM PDT 24 |
130007059 ps |
| T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2424911804 |
|
|
May 07 01:25:50 PM PDT 24 |
May 07 01:25:56 PM PDT 24 |
1392762191 ps |
| T951 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2918565319 |
|
|
May 07 01:26:14 PM PDT 24 |
May 07 01:26:17 PM PDT 24 |
37932254 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3006137844 |
|
|
May 07 01:25:57 PM PDT 24 |
May 07 01:26:02 PM PDT 24 |
353080322 ps |
| T953 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.434853014 |
|
|
May 07 01:26:00 PM PDT 24 |
May 07 01:26:02 PM PDT 24 |
45348764 ps |
| T954 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1570045520 |
|
|
May 07 01:25:55 PM PDT 24 |
May 07 01:25:58 PM PDT 24 |
22196171 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.583810449 |
|
|
May 07 01:26:15 PM PDT 24 |
May 07 01:26:19 PM PDT 24 |
733052561 ps |
| T956 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3798722070 |
|
|
May 07 01:25:57 PM PDT 24 |
May 07 01:26:02 PM PDT 24 |
43747578 ps |
| T72 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.470506200 |
|
|
May 07 01:25:50 PM PDT 24 |
May 07 01:26:58 PM PDT 24 |
88225309450 ps |
| T957 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3258475254 |
|
|
May 07 01:26:06 PM PDT 24 |
May 07 01:26:36 PM PDT 24 |
7567758933 ps |
| T958 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3427663262 |
|
|
May 07 01:26:10 PM PDT 24 |
May 07 01:26:15 PM PDT 24 |
1387817370 ps |
| T73 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.700062641 |
|
|
May 07 01:25:57 PM PDT 24 |
May 07 01:26:52 PM PDT 24 |
7429120852 ps |
| T959 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1732833058 |
|
|
May 07 01:25:49 PM PDT 24 |
May 07 01:25:52 PM PDT 24 |
26061574 ps |
| T960 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2669517502 |
|
|
May 07 01:26:12 PM PDT 24 |
May 07 01:26:16 PM PDT 24 |
161983141 ps |
| T961 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.73692789 |
|
|
May 07 01:26:11 PM PDT 24 |
May 07 01:26:12 PM PDT 24 |
67236331 ps |
| T962 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3547876999 |
|
|
May 07 01:25:52 PM PDT 24 |
May 07 01:26:21 PM PDT 24 |
3845260847 ps |
| T963 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.534563273 |
|
|
May 07 01:26:14 PM PDT 24 |
May 07 01:26:20 PM PDT 24 |
3417550406 ps |
| T74 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.745123545 |
|
|
May 07 01:26:05 PM PDT 24 |
May 07 01:26:34 PM PDT 24 |
15334155758 ps |
| T117 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.188519720 |
|
|
May 07 01:26:13 PM PDT 24 |
May 07 01:26:17 PM PDT 24 |
182995238 ps |
| T964 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4145059860 |
|
|
May 07 01:26:12 PM PDT 24 |
May 07 01:26:14 PM PDT 24 |
59531574 ps |
| T965 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2870643705 |
|
|
May 07 01:25:43 PM PDT 24 |
May 07 01:25:49 PM PDT 24 |
495338707 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2676911393 |
|
|
May 07 01:25:45 PM PDT 24 |
May 07 01:25:50 PM PDT 24 |
356956855 ps |
| T967 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2300760303 |
|
|
May 07 01:26:05 PM PDT 24 |
May 07 01:26:07 PM PDT 24 |
28216206 ps |
| T968 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2229379001 |
|
|
May 07 01:26:05 PM PDT 24 |
May 07 01:26:07 PM PDT 24 |
15133575 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2769110863 |
|
|
May 07 01:26:12 PM PDT 24 |
May 07 01:26:14 PM PDT 24 |
18762387 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2928339758 |
|
|
May 07 01:25:49 PM PDT 24 |
May 07 01:25:51 PM PDT 24 |
35451440 ps |
| T124 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2859565069 |
|
|
May 07 01:25:44 PM PDT 24 |
May 07 01:25:48 PM PDT 24 |
335607756 ps |
| T118 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3143992845 |
|
|
May 07 01:26:05 PM PDT 24 |
May 07 01:26:07 PM PDT 24 |
89445612 ps |
| T971 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1671285903 |
|
|
May 07 01:25:50 PM PDT 24 |
May 07 01:25:53 PM PDT 24 |
82932677 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2162263234 |
|
|
May 07 01:25:51 PM PDT 24 |
May 07 01:25:57 PM PDT 24 |
717947383 ps |
| T973 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1761189294 |
|
|
May 07 01:26:13 PM PDT 24 |
May 07 01:26:18 PM PDT 24 |
177168038 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3417933455 |
|
|
May 07 01:26:11 PM PDT 24 |
May 07 01:26:15 PM PDT 24 |
357093494 ps |
| T75 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4290549692 |
|
|
May 07 01:25:50 PM PDT 24 |
May 07 01:26:45 PM PDT 24 |
41503144927 ps |
| T975 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3750194686 |
|
|
May 07 01:26:05 PM PDT 24 |
May 07 01:26:10 PM PDT 24 |
1908644727 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3521626398 |
|
|
May 07 01:25:46 PM PDT 24 |
May 07 01:25:48 PM PDT 24 |
42395070 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1190703758 |
|
|
May 07 01:25:51 PM PDT 24 |
May 07 01:25:55 PM PDT 24 |
117604412 ps |
| T978 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.827987564 |
|
|
May 07 01:25:54 PM PDT 24 |
May 07 01:25:58 PM PDT 24 |
84152743 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2776662784 |
|
|
May 07 01:25:44 PM PDT 24 |
May 07 01:25:51 PM PDT 24 |
124249611 ps |
| T980 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1587910231 |
|
|
May 07 01:25:56 PM PDT 24 |
May 07 01:26:01 PM PDT 24 |
353116847 ps |
| T84 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4256929996 |
|
|
May 07 01:26:06 PM PDT 24 |
May 07 01:26:38 PM PDT 24 |
10004887315 ps |
| T981 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2486481764 |
|
|
May 07 01:26:12 PM PDT 24 |
May 07 01:26:15 PM PDT 24 |
33362103 ps |
| T982 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2857280522 |
|
|
May 07 01:26:05 PM PDT 24 |
May 07 01:26:06 PM PDT 24 |
24133241 ps |
| T983 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1234969251 |
|
|
May 07 01:25:58 PM PDT 24 |
May 07 01:26:03 PM PDT 24 |
692885530 ps |
| T125 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2943073955 |
|
|
May 07 01:26:13 PM PDT 24 |
May 07 01:26:17 PM PDT 24 |
205348867 ps |
| T123 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3745842665 |
|
|
May 07 01:26:04 PM PDT 24 |
May 07 01:26:07 PM PDT 24 |
305935838 ps |
| T984 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.14931125 |
|
|
May 07 01:25:49 PM PDT 24 |
May 07 01:25:55 PM PDT 24 |
310828242 ps |
| T985 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1194199816 |
|
|
May 07 01:25:58 PM PDT 24 |
May 07 01:26:00 PM PDT 24 |
20612312 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3418206365 |
|
|
May 07 01:25:55 PM PDT 24 |
May 07 01:25:57 PM PDT 24 |
39948948 ps |
| T81 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2399778998 |
|
|
May 07 01:25:55 PM PDT 24 |
May 07 01:25:57 PM PDT 24 |
15423946 ps |
| T987 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3576433576 |
|
|
May 07 01:26:05 PM PDT 24 |
May 07 01:26:10 PM PDT 24 |
130086845 ps |
| T988 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3610518459 |
|
|
May 07 01:25:59 PM PDT 24 |
May 07 01:26:04 PM PDT 24 |
345514396 ps |
| T82 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1578705285 |
|
|
May 07 01:26:05 PM PDT 24 |
May 07 01:26:35 PM PDT 24 |
41013785346 ps |
| T119 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3384448275 |
|
|
May 07 01:26:00 PM PDT 24 |
May 07 01:26:04 PM PDT 24 |
225386617 ps |
| T989 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.996859745 |
|
|
May 07 01:25:49 PM PDT 24 |
May 07 01:25:52 PM PDT 24 |
235281927 ps |
| T990 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1665857458 |
|
|
May 07 01:25:50 PM PDT 24 |
May 07 01:25:53 PM PDT 24 |
68627128 ps |
| T991 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3203734657 |
|
|
May 07 01:26:06 PM PDT 24 |
May 07 01:26:12 PM PDT 24 |
191635028 ps |
| T992 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2366988805 |
|
|
May 07 01:26:06 PM PDT 24 |
May 07 01:26:11 PM PDT 24 |
39575045 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3814782755 |
|
|
May 07 01:25:55 PM PDT 24 |
May 07 01:25:57 PM PDT 24 |
33095983 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1217003442 |
|
|
May 07 01:26:10 PM PDT 24 |
May 07 01:26:12 PM PDT 24 |
75547536 ps |
| T126 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3789812197 |
|
|
May 07 01:26:05 PM PDT 24 |
May 07 01:26:08 PM PDT 24 |
187376467 ps |
| T995 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3282782053 |
|
|
May 07 01:26:04 PM PDT 24 |
May 07 01:26:09 PM PDT 24 |
1416054035 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2614050234 |
|
|
May 07 01:25:49 PM PDT 24 |
May 07 01:25:51 PM PDT 24 |
71202094 ps |
| T996 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2267755700 |
|
|
May 07 01:26:13 PM PDT 24 |
May 07 01:26:18 PM PDT 24 |
342607518 ps |
| T997 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1858364643 |
|
|
May 07 01:26:03 PM PDT 24 |
May 07 01:26:05 PM PDT 24 |
53572494 ps |
| T998 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1433230983 |
|
|
May 07 01:26:06 PM PDT 24 |
May 07 01:26:08 PM PDT 24 |
45628061 ps |
| T999 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2521790499 |
|
|
May 07 01:26:13 PM PDT 24 |
May 07 01:26:17 PM PDT 24 |
79157897 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3312099052 |
|
|
May 07 01:25:53 PM PDT 24 |
May 07 01:25:56 PM PDT 24 |
18674568 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3851972541 |
|
|
May 07 01:25:54 PM PDT 24 |
May 07 01:25:57 PM PDT 24 |
282176433 ps |
| T1002 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4018296717 |
|
|
May 07 01:26:15 PM PDT 24 |
May 07 01:26:17 PM PDT 24 |
88295171 ps |
| T1003 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.310991318 |
|
|
May 07 01:26:03 PM PDT 24 |
May 07 01:26:31 PM PDT 24 |
22164417902 ps |
| T1004 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1256101435 |
|
|
May 07 01:25:49 PM PDT 24 |
May 07 01:25:55 PM PDT 24 |
711545849 ps |
| T127 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3393968711 |
|
|
May 07 01:25:59 PM PDT 24 |
May 07 01:26:03 PM PDT 24 |
1029638419 ps |