Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16436108	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

158910336

1

T1

1543

T2

128643

T3

6663

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86324757	1			T1	16177		T2	70415		T3	3664
values[0x0]	42871010	1			T1	5231		T2	34340		T3	1771
values[0x1]	46150677	1			T1	11152		T2	36547		T3	1901

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8366473	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

166979971

1

T1

14713

T2

134950

T3

7003

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	663772	1			T1	136		T2	630		T3	32
valid_sources[0x01]	700202	1			T1	109		T2	495		T3	23
valid_sources[0x02]	635707	1			T1	144		T2	571		T3	39
valid_sources[0x03]	650277	1			T1	110		T2	554		T3	28
valid_sources[0x04]	747070	1			T1	135		T2	546		T3	33
valid_sources[0x05]	607698	1			T1	130		T2	532		T3	27
valid_sources[0x06]	602379	1			T1	137		T2	619		T3	34
valid_sources[0x07]	706050	1			T1	140		T2	475		T3	20
valid_sources[0x08]	594779	1			T1	141		T2	601		T3	29
valid_sources[0x09]	623364	1			T1	130		T2	557		T3	46
valid_sources[0x0a]	629063	1			T1	104		T2	540		T3	37
valid_sources[0x0b]	665935	1			T1	130		T2	545		T3	19
valid_sources[0x0c]	607410	1			T1	122		T2	589		T3	32
valid_sources[0x0d]	666344	1			T1	152		T2	526		T3	20
valid_sources[0x0e]	695824	1			T1	130		T2	541		T3	30
valid_sources[0x0f]	622458	1			T1	122		T2	518		T3	35
valid_sources[0x10]	611678	1			T1	120		T2	547		T3	35
valid_sources[0x11]	607715	1			T1	102		T2	598		T3	26
valid_sources[0x12]	609981	1			T1	127		T2	566		T3	32
valid_sources[0x13]	627901	1			T1	150		T2	566		T3	28
valid_sources[0x14]	653550	1			T1	126		T2	568		T3	34
valid_sources[0x15]	618911	1			T1	115		T2	533		T3	24
valid_sources[0x16]	1193723	1			T1	141		T2	624		T3	16
valid_sources[0x17]	696200	1			T1	133		T2	514		T3	25
valid_sources[0x18]	616201	1			T1	132		T2	594		T3	31
valid_sources[0x19]	628781	1			T1	95		T2	534		T3	21
valid_sources[0x1a]	651839	1			T1	133		T2	571		T3	26
valid_sources[0x1b]	605116	1			T1	126		T2	513		T3	30
valid_sources[0x1c]	652705	1			T1	116		T2	515		T3	22
valid_sources[0x1d]	643386	1			T1	132		T2	581		T3	27
valid_sources[0x1e]	1045299	1			T1	126		T2	536		T3	35
valid_sources[0x1f]	621911	1			T1	115		T2	655		T3	27
valid_sources[0x20]	617083	1			T1	162		T2	548		T3	27
valid_sources[0x21]	618295	1			T1	160		T2	623		T3	32
valid_sources[0x22]	631994	1			T1	130		T2	538		T3	31
valid_sources[0x23]	1606909	1			T1	113		T2	542		T3	40
valid_sources[0x24]	621087	1			T1	101		T2	533		T3	30
valid_sources[0x25]	625743	1			T1	134		T2	502		T3	26
valid_sources[0x26]	607989	1			T1	125		T2	538		T3	19
valid_sources[0x27]	821872	1			T1	124		T2	554		T3	32
valid_sources[0x28]	673321	1			T1	150		T2	573		T3	32
valid_sources[0x29]	725632	1			T1	131		T2	521		T3	28
valid_sources[0x2a]	612773	1			T1	135		T2	584		T3	28
valid_sources[0x2b]	619739	1			T1	128		T2	603		T3	23
valid_sources[0x2c]	616074	1			T1	117		T2	525		T3	32
valid_sources[0x2d]	664262	1			T1	119		T2	547		T3	25
valid_sources[0x2e]	639248	1			T1	119		T2	570		T3	23
valid_sources[0x2f]	662786	1			T1	98		T2	585		T3	19
valid_sources[0x30]	602989	1			T1	99		T2	565		T3	25
valid_sources[0x31]	596338	1			T1	120		T2	518		T3	24
valid_sources[0x32]	600166	1			T1	125		T2	586		T3	25
valid_sources[0x33]	618847	1			T1	136		T2	578		T3	25
valid_sources[0x34]	592813	1			T1	136		T2	532		T3	22
valid_sources[0x35]	635058	1			T1	130		T2	590		T3	30
valid_sources[0x36]	617611	1			T1	125		T2	573		T3	34
valid_sources[0x37]	637400	1			T1	115		T2	529		T3	15
valid_sources[0x38]	603761	1			T1	83		T2	547		T3	35
valid_sources[0x39]	667023	1			T1	121		T2	586		T3	32
valid_sources[0x3a]	643022	1			T1	120		T2	555		T3	41
valid_sources[0x3b]	632683	1			T1	148		T2	544		T3	36
valid_sources[0x3c]	611397	1			T1	123		T2	526		T3	28
valid_sources[0x3d]	601080	1			T1	124		T2	583		T3	37
valid_sources[0x3e]	640522	1			T1	119		T2	524		T3	29
valid_sources[0x3f]	614606	1			T1	133		T2	525		T3	21
valid_sources[0x40]	2078875	1			T1	142		T2	498		T3	33
valid_sources[0x41]	672669	1			T1	139		T2	582		T3	30
valid_sources[0x42]	1956812	1			T1	146		T2	617		T3	44
valid_sources[0x43]	599221	1			T1	125		T2	592		T3	23
valid_sources[0x44]	650990	1			T1	159		T2	547		T3	19
valid_sources[0x45]	612224	1			T1	127		T2	571		T3	22
valid_sources[0x46]	654546	1			T1	115		T2	551		T3	33
valid_sources[0x47]	623643	1			T1	120		T2	520		T3	23
valid_sources[0x48]	636934	1			T1	130		T2	578		T3	27
valid_sources[0x49]	662562	1			T1	124		T2	569		T3	28
valid_sources[0x4a]	601831	1			T1	118		T2	553		T3	32
valid_sources[0x4b]	706224	1			T1	137		T2	537		T3	21
valid_sources[0x4c]	606262	1			T1	168		T2	523		T3	21
valid_sources[0x4d]	1076443	1			T1	114		T2	580		T3	25
valid_sources[0x4e]	593568	1			T1	156		T2	581		T3	20
valid_sources[0x4f]	628791	1			T1	121		T2	578		T3	21
valid_sources[0x50]	674772	1			T1	109		T2	559		T3	32
valid_sources[0x51]	627800	1			T1	152		T2	513		T3	36
valid_sources[0x52]	682952	1			T1	141		T2	560		T3	25
valid_sources[0x53]	624271	1			T1	115		T2	539		T3	27
valid_sources[0x54]	630068	1			T1	112		T2	509		T3	19
valid_sources[0x55]	595970	1			T1	127		T2	554		T3	38
valid_sources[0x56]	603048	1			T1	165		T2	639		T3	25
valid_sources[0x57]	650634	1			T1	125		T2	527		T3	29
valid_sources[0x58]	661294	1			T1	104		T2	560		T3	40
valid_sources[0x59]	624720	1			T1	118		T2	550		T3	31
valid_sources[0x5a]	619872	1			T1	141		T2	547		T3	23
valid_sources[0x5b]	597179	1			T1	119		T2	562		T3	21
valid_sources[0x5c]	594318	1			T1	118		T2	505		T3	27
valid_sources[0x5d]	629815	1			T1	147		T2	490		T3	27
valid_sources[0x5e]	620960	1			T1	145		T2	599		T3	31
valid_sources[0x5f]	591650	1			T1	113		T2	596		T3	32
valid_sources[0x60]	668037	1			T1	139		T2	534		T3	18
valid_sources[0x61]	681657	1			T1	109		T2	539		T3	18
valid_sources[0x62]	694175	1			T1	125		T2	610		T3	18
valid_sources[0x63]	615990	1			T1	124		T2	634		T3	37
valid_sources[0x64]	605883	1			T1	118		T2	600		T3	29
valid_sources[0x65]	624052	1			T1	115		T2	510		T3	29
valid_sources[0x66]	620465	1			T1	132		T2	518		T3	29
valid_sources[0x67]	593744	1			T1	134		T2	598		T3	26
valid_sources[0x68]	601972	1			T1	150		T2	553		T3	26
valid_sources[0x69]	600724	1			T1	118		T2	546		T3	24
valid_sources[0x6a]	642614	1			T1	122		T2	562		T3	25
valid_sources[0x6b]	618272	1			T1	121		T2	540		T3	31
valid_sources[0x6c]	611530	1			T1	122		T2	496		T3	39
valid_sources[0x6d]	621263	1			T1	117		T2	565		T3	29
valid_sources[0x6e]	603521	1			T1	140		T2	557		T3	44
valid_sources[0x6f]	670867	1			T1	151		T2	588		T3	35
valid_sources[0x70]	632658	1			T1	153		T2	543		T3	28
valid_sources[0x71]	637691	1			T1	129		T2	532		T3	49
valid_sources[0x72]	851976	1			T1	109		T2	531		T3	30
valid_sources[0x73]	2267435	1			T1	120		T2	535		T3	32
valid_sources[0x74]	613307	1			T1	119		T2	572		T3	36
valid_sources[0x75]	663827	1			T1	112		T2	553		T3	24
valid_sources[0x76]	645031	1			T1	107		T2	563		T3	40
valid_sources[0x77]	602808	1			T1	110		T2	491		T3	22
valid_sources[0x78]	604775	1			T1	125		T2	558		T3	30
valid_sources[0x79]	646064	1			T1	143		T2	550		T3	35
valid_sources[0x7a]	629017	1			T1	143		T2	558		T3	28
valid_sources[0x7b]	696392	1			T1	130		T2	529		T3	29
valid_sources[0x7c]	626603	1			T1	124		T2	503		T3	30
valid_sources[0x7d]	620809	1			T1	134		T2	496		T3	32
valid_sources[0x7e]	683652	1			T1	125		T2	563		T3	27
valid_sources[0x7f]	626408	1			T1	104		T2	561		T3	27
valid_sources[0x80]	597323	1			T1	146		T2	520		T3	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

78065088

1

T1

146

T2

64189

T3

3301

values[0x0]

all_enables

biggest_size

40418594

1

T1

723

T2

32380

T3

1682

values[0x1]

all_enables

biggest_size

40426654

1

T1

674

T2

32074

T3

1680

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33523	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

142975

1

T2

15

T3

1

T8

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51163	1			T2	10		T26	256		T22	1
values[0x0]	60860	1			T1	1		T2	23		T3	1
values[0x1]	64475	1			T2	21		T8	9		T4	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25458	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151040

1

T2

18

T3

1

T8

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	709	1			T2	2		T121	1		T130	1
valid_sources[0x01]	581	1			T26	1		T59	1		T130	1
valid_sources[0x02]	544	1			T8	1		T26	3		T6	2
valid_sources[0x03]	902	1			T2	1		T26	3		T27	167
valid_sources[0x04]	698	1			T26	1		T132	2		T133	3
valid_sources[0x05]	813	1			T26	3		T130	2		T25	1
valid_sources[0x06]	776	1			T26	1		T23	1		T134	1
valid_sources[0x07]	821	1			T26	3		T57	3		T121	1
valid_sources[0x08]	469	1			T26	3		T23	1		T6	3
valid_sources[0x09]	681	1			T26	1		T27	92		T6	1
valid_sources[0x0a]	480	1			T43	4		T23	1		T6	1
valid_sources[0x0b]	533	1			T26	3		T27	3		T6	1
valid_sources[0x0c]	703	1			T26	4		T6	3		T129	5
valid_sources[0x0d]	595	1			T2	2		T26	2		T46	60
valid_sources[0x0e]	563	1			T2	1		T26	3		T27	7
valid_sources[0x0f]	638	1			T57	2		T23	1		T6	1
valid_sources[0x10]	495	1			T2	1		T26	5		T135	1
valid_sources[0x11]	1003	1			T26	5		T5	4		T77	1
valid_sources[0x12]	608	1			T2	1		T26	4		T43	2
valid_sources[0x13]	762	1			T26	2		T5	2		T59	2
valid_sources[0x14]	565	1			T26	7		T23	3		T6	1
valid_sources[0x15]	624	1			T26	6		T135	1		T47	122
valid_sources[0x16]	1096	1			T26	2		T31	1		T6	1
valid_sources[0x17]	683	1			T26	3		T58	4		T6	1
valid_sources[0x18]	570	1			T26	2		T5	4		T122	1
valid_sources[0x19]	1345	1			T26	3		T19	1		T23	1
valid_sources[0x1a]	780	1			T26	2		T24	1		T6	2
valid_sources[0x1b]	846	1			T26	3		T6	2		T136	2
valid_sources[0x1c]	708	1			T26	2		T59	1		T137	1
valid_sources[0x1d]	863	1			T26	2		T130	1		T133	1
valid_sources[0x1e]	582	1			T2	2		T26	3		T58	8
valid_sources[0x1f]	576	1			T26	2		T27	55		T5	8
valid_sources[0x20]	776	1			T26	3		T19	1		T5	1
valid_sources[0x21]	825	1			T26	4		T23	1		T6	1
valid_sources[0x22]	674	1			T2	1		T26	5		T5	4
valid_sources[0x23]	568	1			T2	1		T26	6		T6	2
valid_sources[0x24]	644	1			T26	1		T5	4		T6	2
valid_sources[0x25]	890	1			T26	1		T58	2		T28	55
valid_sources[0x26]	702	1			T26	7		T24	1		T6	1
valid_sources[0x27]	604	1			T26	6		T43	12		T57	2
valid_sources[0x28]	995	1			T26	2		T6	3		T132	1
valid_sources[0x29]	526	1			T26	4		T60	1		T130	4
valid_sources[0x2a]	493	1			T2	1		T26	10		T122	1
valid_sources[0x2b]	541	1			T26	1		T6	1		T137	1
valid_sources[0x2c]	737	1			T2	1		T26	6		T58	2
valid_sources[0x2d]	476	1			T2	1		T26	9		T5	9
valid_sources[0x2e]	543	1			T26	5		T58	3		T28	20
valid_sources[0x2f]	1201	1			T26	5		T45	1		T47	1
valid_sources[0x30]	706	1			T26	4		T6	4		T138	2
valid_sources[0x31]	564	1			T26	2		T139	1		T130	1
valid_sources[0x32]	580	1			T26	3		T57	1		T59	5
valid_sources[0x33]	645	1			T26	4		T27	3		T45	1
valid_sources[0x34]	574	1			T26	6		T140	1		T133	2
valid_sources[0x35]	817	1			T2	1		T6	1		T47	4
valid_sources[0x36]	740	1			T2	1		T26	1		T43	3
valid_sources[0x37]	685	1			T26	7		T20	1		T45	1
valid_sources[0x38]	604	1			T12	1		T26	2		T5	1
valid_sources[0x39]	651	1			T26	8		T27	50		T23	1
valid_sources[0x3a]	870	1			T26	7		T23	1		T45	1
valid_sources[0x3b]	750	1			T26	1		T59	5		T6	3
valid_sources[0x3c]	778	1			T26	7		T27	120		T28	5
valid_sources[0x3d]	566	1			T26	5		T27	70		T6	1
valid_sources[0x3e]	610	1			T26	2		T27	128		T44	1
valid_sources[0x3f]	969	1			T2	3		T26	5		T59	5
valid_sources[0x40]	775	1			T26	1		T27	164		T55	1
valid_sources[0x41]	446	1			T26	2		T58	2		T28	3
valid_sources[0x42]	712	1			T14	4		T26	7		T28	3
valid_sources[0x43]	929	1			T2	1		T26	1		T44	2
valid_sources[0x44]	624	1			T26	5		T59	1		T137	1
valid_sources[0x45]	697	1			T26	2		T6	2		T141	2
valid_sources[0x46]	647	1			T26	5		T27	136		T121	1
valid_sources[0x47]	917	1			T2	1		T26	2		T6	1
valid_sources[0x48]	766	1			T26	9		T6	1		T130	1
valid_sources[0x49]	691	1			T26	3		T57	1		T122	1
valid_sources[0x4a]	634	1			T26	4		T57	1		T24	1
valid_sources[0x4b]	961	1			T2	1		T26	8		T23	1
valid_sources[0x4c]	757	1			T26	1		T57	4		T59	2
valid_sources[0x4d]	692	1			T13	1		T26	6		T6	1
valid_sources[0x4e]	562	1			T2	1		T26	1		T22	42
valid_sources[0x4f]	576	1			T26	8		T43	1		T23	1
valid_sources[0x50]	636	1			T2	1		T27	201		T43	3
valid_sources[0x51]	654	1			T26	2		T27	3		T58	6
valid_sources[0x52]	937	1			T26	7		T6	1		T28	54
valid_sources[0x53]	653	1			T26	8		T47	3		T121	1
valid_sources[0x54]	711	1			T26	3		T6	3		T61	9
valid_sources[0x55]	436	1			T26	5		T6	1		T25	1
valid_sources[0x56]	555	1			T2	1		T26	4		T58	1
valid_sources[0x57]	565	1			T26	9		T19	5		T135	1
valid_sources[0x58]	762	1			T26	4		T142	7		T48	12
valid_sources[0x59]	484	1			T26	5		T19	1		T57	1
valid_sources[0x5a]	522	1			T26	4		T27	3		T25	6
valid_sources[0x5b]	491	1			T26	7		T132	1		T121	1
valid_sources[0x5c]	738	1			T26	3		T23	1		T28	4
valid_sources[0x5d]	996	1			T26	1		T24	1		T47	27
valid_sources[0x5e]	490	1			T26	1		T23	1		T6	1
valid_sources[0x5f]	776	1			T26	2		T27	3		T143	1
valid_sources[0x60]	552	1			T26	3		T59	6		T144	1
valid_sources[0x61]	1111	1			T8	1		T26	3		T6	1
valid_sources[0x62]	625	1			T2	1		T26	7		T58	2
valid_sources[0x63]	672	1			T26	4		T5	2		T59	1
valid_sources[0x64]	880	1			T26	1		T6	2		T45	1
valid_sources[0x65]	726	1			T26	1		T59	1		T6	2
valid_sources[0x66]	537	1			T26	10		T43	1		T59	1
valid_sources[0x67]	590	1			T2	1		T15	1		T26	4
valid_sources[0x68]	693	1			T26	4		T60	3		T61	5
valid_sources[0x69]	823	1			T26	7		T6	3		T129	7
valid_sources[0x6a]	615	1			T28	2		T47	17		T140	1
valid_sources[0x6b]	631	1			T26	7		T60	26		T47	24
valid_sources[0x6c]	695	1			T26	8		T59	8		T6	1
valid_sources[0x6d]	678	1			T26	2		T23	1		T136	1
valid_sources[0x6e]	561	1			T2	2		T26	3		T130	1
valid_sources[0x6f]	997	1			T26	5		T27	87		T5	1
valid_sources[0x70]	866	1			T59	7		T6	5		T48	1
valid_sources[0x71]	772	1			T26	4		T58	8		T45	1
valid_sources[0x72]	536	1			T145	1		T146	1		T136	1
valid_sources[0x73]	583	1			T26	2		T45	1		T141	6
valid_sources[0x74]	805	1			T26	1		T19	4		T147	1
valid_sources[0x75]	529	1			T56	2		T121	1		T130	6
valid_sources[0x76]	622	1			T2	2		T26	1		T25	1
valid_sources[0x77]	946	1			T2	2		T8	4		T26	4
valid_sources[0x78]	840	1			T26	1		T6	1		T130	1
valid_sources[0x79]	756	1			T26	6		T122	1		T24	1
valid_sources[0x7a]	806	1			T2	1		T26	5		T27	51
valid_sources[0x7b]	583	1			T26	3		T58	8		T6	2
valid_sources[0x7c]	983	1			T26	6		T23	3		T6	1
valid_sources[0x7d]	591	1			T26	4		T23	1		T148	1
valid_sources[0x7e]	719	1			T26	3		T43	2		T5	2
valid_sources[0x7f]	581	1			T13	1		T26	3		T143	1
valid_sources[0x80]	735	1			T26	5		T43	7		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39240

1

T2

6

T26

237

T27

515

values[0x0]

all_enables

biggest_size

52991

1

T2

6

T3

1

T8

4

values[0x1]

all_enables

biggest_size

50744

1

T2

3

T8

2

T4

3