Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16312247

1

T1

31017

T2

10608

T3

673

full_word

155715703

1

T1

1543

T2

108205

T3

6663

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	172027660	1			T1	32560		T2	118813		T3	7336
auto[TlIntgErrCmd]	81	1			T95	8		T96	4		T97	5
auto[TlIntgErrData]	103	1			T95	4		T96	5		T97	2
auto[TlIntgErrBoth]	106	1			T95	8		T96	1		T97	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82938411

1

T1

16177

T2

47926

T3

3664

auto[1]

89089539

1

T1

16383

T2

70887

T3

3672

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7987672	1			T1	16031		T2	4175		T3	363
auto[TlIntgErrNone]	partial	auto[1]	8324304	1			T1	14986		T2	6433		T3	310
auto[TlIntgErrNone]	full_word	auto[0]	74950606	1			T1	146		T2	43751		T3	3301
auto[TlIntgErrNone]	full_word	auto[1]	80765078	1			T1	1397		T2	64454		T3	3362
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T95	5		T96	1		T97	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T95	3		T96	3		T97	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T108	1		T116	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T109	1		T117	1		-	-
auto[TlIntgErrData]	partial	auto[0]	46	1			T95	2		T96	2		T111	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T95	1		T96	3		T97	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T113	1		T116	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T95	1		T108	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T95	4		T97	2		T111	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T95	4		T96	1		T97	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T112	1		T107	1		T114	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T119	1		T108	1		T120	1