Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	986658	1			T4	17572		T12	2		T13	625
auto[1]	10602252	1			T1	2007		T2	280		T4	2755
auto[2]	743248	1			T4	10904		T12	4		T13	337
auto[3]	10273782	1			T1	2018		T2	225		T4	1291

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13666463	1			T1	4		T2	373		T4	25994
auto[1]	2117421	1			T1	85		T2	68		T4	3364
auto[2]	2136615	1			T1	236		T2	57		T4	2824
auto[3]	4685441	1			T1	3700		T2	7		T4	340

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9532659

1

T1

4025

T2

505

T4

32522

auto[1]

13073281

1

T9

19229

T14

22035

T15

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	395923	1			T4	14469		T13	526		T46	5193
auto[0]	auto[0]	auto[1]	41250	1			T4	1486		T12	1		T13	46
auto[0]	auto[0]	auto[2]	41133	1			T4	1475		T13	46		T77	46
auto[0]	auto[0]	auto[3]	86717	1			T4	142		T12	1		T13	7
auto[0]	auto[1]	auto[0]	3102939	1			T1	1		T2	207		T4	1571
auto[0]	auto[1]	auto[1]	338492	1			T1	18		T2	57		T4	936
auto[0]	auto[1]	auto[2]	360379	1			T1	69		T2	13		T4	143
auto[0]	auto[1]	auto[3]	600724	1			T1	1919		T2	3		T4	105
auto[0]	auto[2]	auto[0]	284284	1			T4	9301		T13	273		T77	6
auto[0]	auto[2]	auto[1]	35483	1			T4	878		T12	1		T13	33
auto[0]	auto[2]	auto[2]	28023	1			T4	672		T12	1		T13	29
auto[0]	auto[2]	auto[3]	60244	1			T4	53		T12	2		T13	2
auto[0]	auto[3]	auto[0]	2918541	1			T1	3		T2	166		T4	653
auto[0]	auto[3]	auto[1]	338319	1			T1	67		T2	11		T4	64
auto[0]	auto[3]	auto[2]	360076	1			T1	167		T2	44		T4	534
auto[0]	auto[3]	auto[3]	540132	1			T1	1781		T2	4		T4	40
auto[1]	auto[0]	auto[0]	13932	1			T125	1		T126	1		T124	510
auto[1]	auto[0]	auto[1]	62928	1			T124	2254		T127	1660		T128	4519
auto[1]	auto[0]	auto[2]	62869	1			T124	2280		T127	1676		T128	4666
auto[1]	auto[0]	auto[3]	281906	1			T77	3		T123	3		T124	10214
auto[1]	auto[1]	auto[0]	3470990	1			T9	140		T14	140		T55	78182
auto[1]	auto[1]	auto[1]	646129	1			T9	1564		T14	1866		T55	7991
auto[1]	auto[1]	auto[2]	603478	1			T9	593		T14	721		T55	7904
auto[1]	auto[1]	auto[3]	1479121	1			T9	7342		T14	8259		T55	803
auto[1]	auto[2]	auto[0]	12546	1			T124	481		T127	204		T128	913
auto[1]	auto[2]	auto[1]	56410	1			T124	2072		T127	1050		T128	4246
auto[1]	auto[2]	auto[2]	48419	1			T124	1824		T127	1575		T128	3835
auto[1]	auto[2]	auto[3]	217839	1			T124	8591		T127	7129		T128	17433
auto[1]	auto[3]	auto[0]	3467308	1			T9	149		T14	137		T55	78225
auto[1]	auto[3]	auto[1]	598410	1			T9	576		T14	651		T55	7914
auto[1]	auto[3]	auto[2]	632238	1			T9	1601		T14	1823		T55	7882
auto[1]	auto[3]	auto[3]	1418758	1			T9	7264		T14	8438		T15	2