Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1209799808	145803	0	0
ctrl_regwen_rd_A	1209799808	7343	0	0
exec_rd_A	1209799808	7032	0	0
exec_regwen_rd_A	1209799808	7222	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1209799808	145803	0	0
T5	917517	0	0	0
T19	2086	0	0	0
T22	523778	0	0	0
T26	21032	513	0	0
T27	37761	2042	0	0
T28	0	529	0	0
T43	195191	0	0	0
T47	0	323	0	0
T48	0	2773	0	0
T49	0	2365	0	0
T50	0	313	0	0
T51	0	2282	0	0
T52	0	8084	0	0
T53	0	6806	0	0
T54	71895	0	0	0
T55	363564	0	0	0
T56	68062	0	0	0
T57	847157	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1209799808	7343	0	0
T5	917517	0	0	0
T19	2086	0	0	0
T22	523778	0	0	0
T26	21032	172	0	0
T27	37761	0	0	0
T43	195191	0	0	0
T47	0	136	0	0
T51	0	335	0	0
T54	71895	0	0	0
T55	363564	0	0	0
T56	68062	0	0	0
T57	847157	0	0	0
T98	0	299	0	0
T99	0	536	0	0
T100	0	1110	0	0
T101	0	159	0	0
T102	0	299	0	0
T103	0	237	0	0
T104	0	189	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1209799808	7032	0	0
T5	917517	0	0	0
T19	2086	0	0	0
T22	523778	0	0	0
T26	21032	145	0	0
T27	37761	0	0	0
T43	195191	0	0	0
T47	0	101	0	0
T51	0	291	0	0
T54	71895	0	0	0
T55	363564	0	0	0
T56	68062	0	0	0
T57	847157	0	0	0
T98	0	282	0	0
T99	0	606	0	0
T100	0	933	0	0
T101	0	117	0	0
T102	0	220	0	0
T103	0	275	0	0
T104	0	222	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1209799808	7222	0	0
T5	917517	0	0	0
T19	2086	0	0	0
T22	523778	0	0	0
T26	21032	123	0	0
T27	37761	0	0	0
T43	195191	0	0	0
T47	0	132	0	0
T51	0	362	0	0
T54	71895	0	0	0
T55	363564	0	0	0
T56	68062	0	0	0
T57	847157	0	0	0
T98	0	268	0	0
T99	0	621	0	0
T100	0	956	0	0
T101	0	100	0	0
T102	0	238	0	0
T103	0	264	0	0
T104	0	153	0	0