Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16630526	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152847611

1

T1

196120

T2

149083

T3

8168

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	83292920	1			T1	107414		T2	82171		T3	5050
values[0x0]	41424536	1			T1	52220		T2	39500		T3	2294
values[0x1]	44760681	1			T1	56065		T2	42392		T3	2656

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8450730	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161027407

1

T1

205995

T2

156669

T3

9098

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	568405	1			T1	866		T2	595		T3	42
valid_sources[0x01]	590300	1			T1	882		T2	577		T3	57
valid_sources[0x02]	566205	1			T1	826		T2	631		T3	42
valid_sources[0x03]	1419314	1			T1	818		T2	628		T3	36
valid_sources[0x04]	593151	1			T1	900		T2	672		T3	64
valid_sources[0x05]	572471	1			T1	875		T2	691		T3	59
valid_sources[0x06]	590280	1			T1	847		T2	606		T3	42
valid_sources[0x07]	659998	1			T1	888		T2	713		T3	22
valid_sources[0x08]	571565	1			T1	798		T2	602		T3	34
valid_sources[0x09]	1055084	1			T1	826		T2	683		T3	33
valid_sources[0x0a]	585015	1			T1	895		T2	630		T3	30
valid_sources[0x0b]	577072	1			T1	867		T2	627		T3	37
valid_sources[0x0c]	551790	1			T1	801		T2	653		T3	25
valid_sources[0x0d]	2256662	1			T1	824		T2	609		T3	59
valid_sources[0x0e]	606393	1			T1	782		T2	647		T3	38
valid_sources[0x0f]	555963	1			T1	810		T2	647		T3	43
valid_sources[0x10]	635460	1			T1	858		T2	595		T3	33
valid_sources[0x11]	564172	1			T1	799		T2	646		T3	54
valid_sources[0x12]	589498	1			T1	828		T2	631		T3	45
valid_sources[0x13]	596762	1			T1	903		T2	649		T3	51
valid_sources[0x14]	575165	1			T1	816		T2	631		T3	31
valid_sources[0x15]	1922461	1			T1	865		T2	642		T3	35
valid_sources[0x16]	1771138	1			T1	871		T2	700		T3	34
valid_sources[0x17]	594927	1			T1	862		T2	588		T3	35
valid_sources[0x18]	607085	1			T1	843		T2	635		T3	51
valid_sources[0x19]	563753	1			T1	809		T2	667		T3	41
valid_sources[0x1a]	678451	1			T1	808		T2	673		T3	31
valid_sources[0x1b]	724050	1			T1	805		T2	628		T3	43
valid_sources[0x1c]	607928	1			T1	883		T2	608		T3	37
valid_sources[0x1d]	597498	1			T1	859		T2	573		T3	62
valid_sources[0x1e]	594122	1			T1	830		T2	632		T3	40
valid_sources[0x1f]	587632	1			T1	826		T2	649		T3	41
valid_sources[0x20]	573237	1			T1	802		T2	624		T3	25
valid_sources[0x21]	607775	1			T1	809		T2	591		T3	42
valid_sources[0x22]	671514	1			T1	847		T2	714		T3	42
valid_sources[0x23]	600639	1			T1	825		T2	599		T3	44
valid_sources[0x24]	550054	1			T1	818		T2	708		T3	34
valid_sources[0x25]	637638	1			T1	860		T2	656		T3	59
valid_sources[0x26]	654611	1			T1	835		T2	649		T3	51
valid_sources[0x27]	570496	1			T1	829		T2	655		T3	24
valid_sources[0x28]	1804067	1			T1	807		T2	659		T3	45
valid_sources[0x29]	576480	1			T1	827		T2	680		T3	28
valid_sources[0x2a]	546436	1			T1	879		T2	571		T3	26
valid_sources[0x2b]	568781	1			T1	795		T2	619		T3	33
valid_sources[0x2c]	589481	1			T1	862		T2	657		T3	34
valid_sources[0x2d]	594914	1			T1	814		T2	630		T3	43
valid_sources[0x2e]	613640	1			T1	843		T2	673		T3	40
valid_sources[0x2f]	695471	1			T1	902		T2	663		T3	41
valid_sources[0x30]	615144	1			T1	881		T2	649		T3	17
valid_sources[0x31]	632130	1			T1	899		T2	598		T3	49
valid_sources[0x32]	562381	1			T1	776		T2	651		T3	37
valid_sources[0x33]	594732	1			T1	825		T2	584		T3	42
valid_sources[0x34]	606762	1			T1	877		T2	674		T3	39
valid_sources[0x35]	597549	1			T1	816		T2	584		T3	40
valid_sources[0x36]	678350	1			T1	848		T2	619		T3	65
valid_sources[0x37]	603555	1			T1	807		T2	615		T3	50
valid_sources[0x38]	576485	1			T1	894		T2	597		T3	39
valid_sources[0x39]	557770	1			T1	848		T2	597		T3	30
valid_sources[0x3a]	820451	1			T1	866		T2	709		T3	39
valid_sources[0x3b]	604896	1			T1	840		T2	649		T3	41
valid_sources[0x3c]	553261	1			T1	900		T2	664		T3	40
valid_sources[0x3d]	572984	1			T1	814		T2	685		T3	31
valid_sources[0x3e]	561803	1			T1	892		T2	623		T3	36
valid_sources[0x3f]	574573	1			T1	767		T2	585		T3	46
valid_sources[0x40]	557252	1			T1	854		T2	666		T3	34
valid_sources[0x41]	570886	1			T1	874		T2	597		T3	32
valid_sources[0x42]	564219	1			T1	853		T2	647		T3	38
valid_sources[0x43]	598125	1			T1	852		T2	641		T3	33
valid_sources[0x44]	570408	1			T1	798		T2	665		T3	30
valid_sources[0x45]	551372	1			T1	792		T2	666		T3	47
valid_sources[0x46]	574958	1			T1	780		T2	700		T3	28
valid_sources[0x47]	615750	1			T1	804		T2	674		T3	30
valid_sources[0x48]	581995	1			T1	856		T2	632		T3	35
valid_sources[0x49]	637366	1			T1	847		T2	600		T3	37
valid_sources[0x4a]	585648	1			T1	797		T2	652		T3	32
valid_sources[0x4b]	609564	1			T1	817		T2	656		T3	46
valid_sources[0x4c]	555736	1			T1	909		T2	663		T3	38
valid_sources[0x4d]	551385	1			T1	854		T2	638		T3	40
valid_sources[0x4e]	581443	1			T1	830		T2	617		T3	48
valid_sources[0x4f]	557415	1			T1	849		T2	635		T3	48
valid_sources[0x50]	613914	1			T1	804		T2	619		T3	37
valid_sources[0x51]	584825	1			T1	842		T2	640		T3	46
valid_sources[0x52]	566261	1			T1	877		T2	615		T3	38
valid_sources[0x53]	580845	1			T1	855		T2	601		T3	30
valid_sources[0x54]	755250	1			T1	844		T2	647		T3	31
valid_sources[0x55]	591520	1			T1	826		T2	600		T3	39
valid_sources[0x56]	640771	1			T1	832		T2	594		T3	37
valid_sources[0x57]	1485688	1			T1	869		T2	609		T3	35
valid_sources[0x58]	578459	1			T1	874		T2	644		T3	28
valid_sources[0x59]	619229	1			T1	864		T2	683		T3	66
valid_sources[0x5a]	565516	1			T1	817		T2	595		T3	43
valid_sources[0x5b]	605384	1			T1	868		T2	605		T3	21
valid_sources[0x5c]	552777	1			T1	899		T2	619		T3	40
valid_sources[0x5d]	551369	1			T1	875		T2	765		T3	39
valid_sources[0x5e]	594658	1			T1	822		T2	685		T3	42
valid_sources[0x5f]	559621	1			T1	855		T2	664		T3	27
valid_sources[0x60]	665424	1			T1	840		T2	660		T3	32
valid_sources[0x61]	659451	1			T1	873		T2	659		T3	34
valid_sources[0x62]	569360	1			T1	835		T2	679		T3	27
valid_sources[0x63]	762952	1			T1	849		T2	589		T3	31
valid_sources[0x64]	604840	1			T1	848		T2	574		T3	49
valid_sources[0x65]	572478	1			T1	880		T2	666		T3	43
valid_sources[0x66]	559368	1			T1	865		T2	572		T3	34
valid_sources[0x67]	551545	1			T1	834		T2	642		T3	19
valid_sources[0x68]	572168	1			T1	826		T2	628		T3	34
valid_sources[0x69]	561207	1			T1	866		T2	652		T3	28
valid_sources[0x6a]	1391286	1			T1	853		T2	629		T3	24
valid_sources[0x6b]	562821	1			T1	780		T2	652		T3	42
valid_sources[0x6c]	616550	1			T1	840		T2	615		T3	42
valid_sources[0x6d]	1543362	1			T1	795		T2	685		T3	46
valid_sources[0x6e]	590247	1			T1	909		T2	577		T3	46
valid_sources[0x6f]	544408	1			T1	912		T2	690		T3	39
valid_sources[0x70]	646153	1			T1	873		T2	655		T3	37
valid_sources[0x71]	609449	1			T1	818		T2	653		T3	40
valid_sources[0x72]	573403	1			T1	804		T2	621		T3	46
valid_sources[0x73]	754480	1			T1	810		T2	605		T3	26
valid_sources[0x74]	558504	1			T1	820		T2	638		T3	38
valid_sources[0x75]	669393	1			T1	909		T2	623		T3	38
valid_sources[0x76]	575290	1			T1	821		T2	660		T3	31
valid_sources[0x77]	560217	1			T1	856		T2	622		T3	36
valid_sources[0x78]	643657	1			T1	800		T2	620		T3	66
valid_sources[0x79]	617816	1			T1	895		T2	669		T3	30
valid_sources[0x7a]	657051	1			T1	874		T2	648		T3	44
valid_sources[0x7b]	581916	1			T1	847		T2	642		T3	47
valid_sources[0x7c]	617933	1			T1	893		T2	554		T3	30
valid_sources[0x7d]	624070	1			T1	823		T2	602		T3	37
valid_sources[0x7e]	573693	1			T1	804		T2	607		T3	65
valid_sources[0x7f]	569714	1			T1	881		T2	605		T3	40
valid_sources[0x80]	553261	1			T1	888		T2	582		T3	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74936030

1

T1

97782

T2

74578

T3

4134

values[0x0]

all_enables

biggest_size

38946927

1

T1

49218

T2

37327

T3

2048

values[0x1]

all_enables

biggest_size

38964654

1

T1

49120

T2

37178

T3

1986

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36237	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

177394

1

T1

32

T2

1

T4

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	60764	1			T1	18		T4	19		T6	484
values[0x0]	74057	1			T1	43		T3	1		T4	39
values[0x1]	78810	1			T1	27		T2	3		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

186456

1

T1

36

T2

1

T4

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	700	1			T6	13		T7	1		T25	16
valid_sources[0x01]	1092	1			T6	5		T15	1		T25	10
valid_sources[0x02]	744	1			T6	7		T25	7		T26	8
valid_sources[0x03]	678	1			T1	2		T6	2		T25	6
valid_sources[0x04]	688	1			T6	2		T10	3		T13	2
valid_sources[0x05]	850	1			T6	7		T14	1		T15	1
valid_sources[0x06]	873	1			T6	9		T14	3		T25	8
valid_sources[0x07]	710	1			T6	6		T10	1		T25	11
valid_sources[0x08]	966	1			T6	3		T11	2		T25	10
valid_sources[0x09]	706	1			T6	8		T15	2		T25	8
valid_sources[0x0a]	887	1			T1	1		T6	12		T15	7
valid_sources[0x0b]	816	1			T6	11		T15	2		T25	13
valid_sources[0x0c]	588	1			T1	2		T6	19		T25	7
valid_sources[0x0d]	891	1			T6	11		T25	4		T26	9
valid_sources[0x0e]	642	1			T6	8		T25	11		T26	5
valid_sources[0x0f]	683	1			T6	11		T15	1		T25	12
valid_sources[0x10]	962	1			T6	4		T25	12		T42	2
valid_sources[0x11]	770	1			T6	7		T25	7		T26	7
valid_sources[0x12]	842	1			T6	9		T10	5		T13	1
valid_sources[0x13]	905	1			T6	5		T10	3		T25	8
valid_sources[0x14]	1215	1			T6	9		T15	3		T25	9
valid_sources[0x15]	1054	1			T6	11		T25	9		T26	7
valid_sources[0x16]	782	1			T1	1		T6	8		T14	6
valid_sources[0x17]	1217	1			T6	13		T15	3		T25	12
valid_sources[0x18]	682	1			T6	4		T25	11		T26	7
valid_sources[0x19]	896	1			T6	9		T25	7		T26	7
valid_sources[0x1a]	655	1			T6	7		T25	12		T26	6
valid_sources[0x1b]	1162	1			T1	1		T6	2		T25	5
valid_sources[0x1c]	1359	1			T1	7		T6	14		T10	3
valid_sources[0x1d]	865	1			T1	1		T6	11		T7	2
valid_sources[0x1e]	586	1			T1	1		T6	7		T25	5
valid_sources[0x1f]	609	1			T6	4		T25	6		T26	7
valid_sources[0x20]	825	1			T6	5		T25	3		T48	1
valid_sources[0x21]	1116	1			T6	7		T25	8		T26	4
valid_sources[0x22]	748	1			T1	2		T6	5		T14	1
valid_sources[0x23]	903	1			T6	4		T25	5		T26	11
valid_sources[0x24]	724	1			T6	8		T25	4		T26	7
valid_sources[0x25]	695	1			T6	5		T15	1		T25	6
valid_sources[0x26]	1044	1			T6	10		T7	1		T25	6
valid_sources[0x27]	785	1			T1	1		T6	6		T25	8
valid_sources[0x28]	1178	1			T6	5		T10	6		T14	2
valid_sources[0x29]	779	1			T1	4		T6	7		T25	7
valid_sources[0x2a]	730	1			T1	2		T6	10		T13	1
valid_sources[0x2b]	713	1			T6	14		T14	3		T25	14
valid_sources[0x2c]	853	1			T6	6		T25	8		T26	8
valid_sources[0x2d]	785	1			T1	2		T6	5		T25	7
valid_sources[0x2e]	755	1			T6	4		T25	9		T48	1
valid_sources[0x2f]	858	1			T1	6		T6	4		T15	4
valid_sources[0x30]	727	1			T6	4		T25	8		T26	5
valid_sources[0x31]	1017	1			T2	1		T6	2		T13	1
valid_sources[0x32]	744	1			T6	4		T25	6		T26	7
valid_sources[0x33]	889	1			T6	6		T25	8		T26	7
valid_sources[0x34]	834	1			T1	5		T6	10		T10	1
valid_sources[0x35]	782	1			T6	9		T14	1		T15	2
valid_sources[0x36]	625	1			T6	10		T15	2		T25	15
valid_sources[0x37]	683	1			T6	5		T25	6		T61	1
valid_sources[0x38]	1050	1			T6	4		T25	12		T26	6
valid_sources[0x39]	953	1			T6	5		T25	10		T26	11
valid_sources[0x3a]	1034	1			T6	8		T25	5		T26	8
valid_sources[0x3b]	872	1			T6	2		T7	1		T25	5
valid_sources[0x3c]	1241	1			T6	6		T25	6		T20	1
valid_sources[0x3d]	617	1			T1	1		T2	1		T6	4
valid_sources[0x3e]	603	1			T6	6		T15	2		T25	5
valid_sources[0x3f]	782	1			T6	13		T15	3		T25	8
valid_sources[0x40]	913	1			T6	10		T15	1		T25	5
valid_sources[0x41]	783	1			T6	13		T25	6		T26	2
valid_sources[0x42]	803	1			T6	11		T25	7		T26	5
valid_sources[0x43]	558	1			T1	1		T6	3		T25	10
valid_sources[0x44]	1054	1			T6	11		T10	1		T25	8
valid_sources[0x45]	642	1			T6	8		T25	5		T48	1
valid_sources[0x46]	970	1			T6	9		T16	1		T14	1
valid_sources[0x47]	1004	1			T6	7		T25	4		T26	5
valid_sources[0x48]	748	1			T6	9		T25	7		T26	8
valid_sources[0x49]	566	1			T6	3		T25	4		T26	1
valid_sources[0x4a]	714	1			T6	5		T13	1		T25	12
valid_sources[0x4b]	624	1			T6	10		T25	11		T42	1
valid_sources[0x4c]	933	1			T6	11		T15	1		T25	3
valid_sources[0x4d]	646	1			T6	3		T25	5		T26	12
valid_sources[0x4e]	934	1			T6	7		T15	1		T25	9
valid_sources[0x4f]	870	1			T6	6		T25	9		T48	1
valid_sources[0x50]	656	1			T1	2		T6	6		T25	11
valid_sources[0x51]	883	1			T6	7		T25	10		T26	8
valid_sources[0x52]	955	1			T6	10		T25	3		T26	6
valid_sources[0x53]	718	1			T6	7		T25	9		T26	2
valid_sources[0x54]	1058	1			T1	1		T6	9		T25	9
valid_sources[0x55]	878	1			T6	10		T25	5		T26	6
valid_sources[0x56]	789	1			T6	7		T15	1		T25	6
valid_sources[0x57]	959	1			T6	9		T25	5		T26	9
valid_sources[0x58]	1043	1			T6	11		T15	1		T25	8
valid_sources[0x59]	770	1			T1	1		T6	6		T25	11
valid_sources[0x5a]	569	1			T6	5		T25	14		T48	2
valid_sources[0x5b]	739	1			T6	6		T25	5		T26	6
valid_sources[0x5c]	921	1			T6	11		T15	3		T25	7
valid_sources[0x5d]	718	1			T6	8		T25	7		T48	2
valid_sources[0x5e]	876	1			T6	11		T25	11		T26	7
valid_sources[0x5f]	694	1			T6	6		T25	6		T66	1
valid_sources[0x60]	911	1			T6	10		T25	4		T26	11
valid_sources[0x61]	928	1			T6	7		T25	6		T26	7
valid_sources[0x62]	761	1			T6	11		T13	2		T25	11
valid_sources[0x63]	836	1			T6	8		T25	9		T26	6
valid_sources[0x64]	633	1			T6	4		T10	1		T25	7
valid_sources[0x65]	801	1			T6	6		T25	10		T48	1
valid_sources[0x66]	673	1			T1	3		T6	7		T25	7
valid_sources[0x67]	791	1			T6	6		T25	9		T26	4
valid_sources[0x68]	844	1			T6	11		T25	7		T26	6
valid_sources[0x69]	683	1			T6	3		T25	7		T60	1
valid_sources[0x6a]	670	1			T2	1		T6	8		T25	7
valid_sources[0x6b]	981	1			T6	9		T25	7		T26	4
valid_sources[0x6c]	1231	1			T6	5		T10	2		T25	11
valid_sources[0x6d]	805	1			T1	1		T6	6		T25	14
valid_sources[0x6e]	636	1			T6	10		T25	7		T26	3
valid_sources[0x6f]	904	1			T6	9		T15	1		T25	4
valid_sources[0x70]	652	1			T6	2		T25	12		T26	5
valid_sources[0x71]	687	1			T6	2		T15	1		T25	7
valid_sources[0x72]	1389	1			T1	2		T6	4		T14	1
valid_sources[0x73]	1079	1			T6	4		T25	11		T89	1
valid_sources[0x74]	630	1			T6	8		T25	6		T26	8
valid_sources[0x75]	797	1			T1	2		T6	10		T25	7
valid_sources[0x76]	654	1			T6	8		T10	4		T13	1
valid_sources[0x77]	533	1			T6	13		T15	1		T25	6
valid_sources[0x78]	1010	1			T6	7		T25	6		T26	7
valid_sources[0x79]	931	1			T1	4		T6	6		T15	1
valid_sources[0x7a]	614	1			T6	6		T10	3		T25	4
valid_sources[0x7b]	915	1			T6	8		T25	11		T26	6
valid_sources[0x7c]	1191	1			T6	7		T25	15		T67	1
valid_sources[0x7d]	814	1			T6	12		T25	6		T26	4
valid_sources[0x7e]	810	1			T6	8		T15	1		T25	7
valid_sources[0x7f]	597	1			T6	2		T25	10		T26	6
valid_sources[0x80]	798	1			T6	9		T14	1		T25	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47798

1

T1

8

T4

10

T6

461

values[0x0]

all_enables

biggest_size

65814

1

T1

17

T4

13

T5

4

values[0x1]

all_enables

biggest_size

63782

1

T1

7

T2

1

T4

8