Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16550360

1

T1

16916

T2

14980

T3

1832

full_word

149618415

1

T1

168270

T2

149083

T3

8168

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	166168495	1			T1	185186		T2	164063		T3	10000
auto[TlIntgErrCmd]	96	1			T97	3		T98	4		T99	9
auto[TlIntgErrData]	82	1			T97	3		T98	3		T99	6
auto[TlIntgErrBoth]	102	1			T97	4		T98	3		T99	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79869427

1

T1

76901

T2

82171

T3

5050

auto[1]

86299348

1

T1

108285

T2

81892

T3

4950

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8090820	1			T1	6969		T2	7593		T3	916
auto[TlIntgErrNone]	partial	auto[1]	8459285	1			T1	9947		T2	7387		T3	916
auto[TlIntgErrNone]	full_word	auto[0]	71778475	1			T1	69932		T2	74578		T3	4134
auto[TlIntgErrNone]	full_word	auto[1]	77839915	1			T1	98338		T2	74505		T3	4034
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T97	1		T98	1		T99	4
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T97	2		T98	3		T99	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T99	1		T107	1		T111	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T112	1		T115	1		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1			T97	1		T98	2		T99	4
auto[TlIntgErrData]	partial	auto[1]	32	1			T97	2		T98	1		T99	2
auto[TlIntgErrData]	full_word	auto[0]	9	1			T108	2		T110	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T116	1		T109	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T97	2		T98	1		T99	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T97	2		T98	2		T99	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T111	1		T118	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T110	1		T120	1		T121	1