Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	829693	1			T4	9246		T14	3220		T15	2026
auto[1]	10717014	1			T1	8910		T2	68550		T3	5049
auto[2]	649774	1			T4	5047		T14	2316		T15	1045
auto[3]	10438149	1			T1	6670		T2	68189		T3	4949

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13885040	1			T1	12921		T2	114213		T3	6686
auto[1]	2089286	1			T1	1275		T2	10544		T3	1481
auto[2]	2122549	1			T1	1250		T2	10984		T3	1504
auto[3]	4537755	1			T1	134		T2	998		T3	327

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9394032

1

T1

15579

T2

45

T3

9998

auto[1]

13240598

1

T1

1

T2

136694

T4

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	286812	1			T4	7724		T14	2659		T15	1664
auto[0]	auto[0]	auto[1]	30767	1			T4	710		T14	276		T15	169
auto[0]	auto[0]	auto[2]	30619	1			T4	741		T14	265		T15	171
auto[0]	auto[0]	auto[3]	117726	1			T4	70		T14	20		T15	22
auto[0]	auto[1]	auto[0]	3118994	1			T1	7410		T2	14		T3	3400
auto[0]	auto[1]	auto[1]	338817	1			T1	718		T2	4		T3	733
auto[0]	auto[1]	auto[2]	357761	1			T1	709		T2	3		T3	757
auto[0]	auto[1]	auto[3]	587479	1			T1	72		T3	159		T4	55
auto[0]	auto[2]	auto[0]	211569	1			T4	4184		T14	1954		T15	807
auto[0]	auto[2]	auto[1]	31014	1			T4	452		T14	204		T15	80
auto[0]	auto[2]	auto[2]	21504	1			T4	377		T14	146		T15	139
auto[0]	auto[2]	auto[3]	81253	1			T4	33		T14	12		T15	19
auto[0]	auto[3]	auto[0]	2956059	1			T1	5511		T2	18		T3	3286
auto[0]	auto[3]	auto[1]	336963	1			T1	556		T2	3		T3	748
auto[0]	auto[3]	auto[2]	362235	1			T1	541		T2	3		T3	747
auto[0]	auto[3]	auto[3]	524460	1			T1	62		T3	168		T4	31
auto[1]	auto[0]	auto[0]	12046	1			T4	1		T126	1		T92	804
auto[1]	auto[0]	auto[1]	53963	1			T92	3839		T127	2935		T128	5228
auto[1]	auto[0]	auto[2]	53706	1			T92	3705		T124	1		T127	2878
auto[1]	auto[0]	auto[3]	244054	1			T92	17190		T124	4		T129	1
auto[1]	auto[1]	auto[0]	3645486	1			T2	57202		T5	45720		T12	1935
auto[1]	auto[1]	auto[1]	647967	1			T1	1		T2	4954		T5	4233
auto[1]	auto[1]	auto[2]	611308	1			T2	5876		T5	4575		T12	8519
auto[1]	auto[1]	auto[3]	1409202	1			T2	497		T5	425		T12	33888
auto[1]	auto[2]	auto[0]	10406	1			T4	1		T92	853		T130	1
auto[1]	auto[2]	auto[1]	46674	1			T92	3634		T127	2639		T128	4882
auto[1]	auto[2]	auto[2]	45370	1			T92	2544		T127	1950		T128	4454
auto[1]	auto[2]	auto[3]	201984	1			T92	11411		T127	8822		T128	20014
auto[1]	auto[3]	auto[0]	3643668	1			T2	56979		T5	46084		T12	1916
auto[1]	auto[3]	auto[1]	603121	1			T2	5583		T5	4579		T12	8378
auto[1]	auto[3]	auto[2]	640046	1			T2	5102		T5	4170		T12	7553
auto[1]	auto[3]	auto[3]	1371597	1			T2	501		T5	409		T12	34254